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authorSebastian Huber <sebastian.huber@embedded-brains.de>2016-01-25 10:20:28 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2016-01-26 09:07:30 +0100
commita8865f8b415788c4e9bb7f68e38d41aec0e485db (patch)
treed7b70c608239be68c6476b0d9e9893e099ec8be6 /cpukit/score/cpu/lm32/rtems
parentscore: Add RTEMS_ALIGNED() (diff)
downloadrtems-a8865f8b415788c4e9bb7f68e38d41aec0e485db.tar.bz2
score: Introduce CPU_CACHE_LINE_BYTES
Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
Diffstat (limited to 'cpukit/score/cpu/lm32/rtems')
-rw-r--r--cpukit/score/cpu/lm32/rtems/score/cpu.h28
1 files changed, 4 insertions, 24 deletions
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index 1a6147565a..dd0ec47898 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -289,30 +289,10 @@ extern "C" {
*/
#define CPU_STACK_GROWS_UP FALSE
-/**
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
- *
- * __attribute__ ((aligned (32)))
- *
- * NOTE: Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
- *
- * Port Specific Information:
- *
- * L2 cache lines are 32 bytes in Milkymist SoC
- */
-#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
+/* L2 cache lines are 32 bytes in Milkymist SoC */
+#define CPU_CACHE_LINE_BYTES 32
+
+#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
/**
* @defgroup CPUEndian Processor Dependent Endianness Support