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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-11-28 18:16:00 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-11-28 18:16:00 +0000 |
| commit | 4db302830436a61c9af69d0b393f9ac44a558c2e (patch) | |
| tree | cf5f2b3c3fd87618d3f0bebf9b4e203933c7fb49 /cpukit/score/cpu/i960 | |
| parent | 2001-11-28 Joel Sherrill <joel@OARcorp.com>, (diff) | |
| download | rtems-4db302830436a61c9af69d0b393f9ac44a558c2e.tar.bz2 | |
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
Diffstat (limited to 'cpukit/score/cpu/i960')
| -rw-r--r-- | cpukit/score/cpu/i960/ChangeLog | 7 | ||||
| -rw-r--r-- | cpukit/score/cpu/i960/rtems/score/cpu.h | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/cpukit/score/cpu/i960/ChangeLog b/cpukit/score/cpu/i960/ChangeLog index 39b01acded..2811facb54 100644 --- a/cpukit/score/cpu/i960/ChangeLog +++ b/cpukit/score/cpu/i960/ChangeLog @@ -1,3 +1,10 @@ +2001-11-28 Joel Sherrill <joel@OARcorp.com>, + + This was tracked as PR91. + * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which + is used to specify if the port uses the standard macro for this (FALSE). + A TRUE setting indicates the port provides its own implementation. + 2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * .cvsignore: Add autom4te.cache for autoconf > 2.52. diff --git a/cpukit/score/cpu/i960/rtems/score/cpu.h b/cpukit/score/cpu/i960/rtems/score/cpu.h index bc13335e92..98b098ad2f 100644 --- a/cpukit/score/cpu/i960/rtems/score/cpu.h +++ b/cpukit/score/cpu/i960/rtems/score/cpu.h @@ -215,6 +215,13 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) /* + * This is defined if the port has a special way to report the ISR nesting + * level. Most ports maintain the variable _ISR_Nest_level. + */ + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +/* * Minimum size of a thread's stack. * * NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK |