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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-01-03 16:32:23 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-01-03 16:32:23 +0000
commitac0043451dfa122d628ba73e8250b9b707295fea (patch)
treea853232ac16337af6053ca6dfc6fd43e839fdded /cpukit/score/cpu/i960/cpu_asm.S
parent2001-01-03 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-ac0043451dfa122d628ba73e8250b9b707295fea.tar.bz2
2001-01-03 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Added _CPU_Initialize_vectors(). * cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
Diffstat (limited to 'cpukit/score/cpu/i960/cpu_asm.S')
-rw-r--r--cpukit/score/cpu/i960/cpu_asm.S8
1 files changed, 5 insertions, 3 deletions
diff --git a/cpukit/score/cpu/i960/cpu_asm.S b/cpukit/score/cpu/i960/cpu_asm.S
index 91b4b6112f..82906ad4ff 100644
--- a/cpukit/score/cpu/i960/cpu_asm.S
+++ b/cpukit/score/cpu/i960/cpu_asm.S
@@ -128,10 +128,12 @@ __ISR_Handler:
lda 1(r4),r4 # increment dispatch disable level
movl g6,r14 # save g6-g7
- stq g8, _ISR_reg_save # save g8-g11
- stl g12, _ISR_reg_save+16 # save g12-g13
+ ld __ISR_Vector_table,g1 # g1 = base of vector table
- ld __ISR_Vector_table[g0*4],g1 # g1 = Users handler
+ stq g8, _ISR_reg_save # save g8-g11
+ stl g12, _ISR_reg_save+16 # save g12-g13
+
+ ld (g1)[g0*4],g1 # g1 = Users handler
addo 1,r5,r5 # increment ISR level
st r4,__Thread_Dispatch_disable_level