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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-07-11 19:31:04 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-07-11 19:31:04 +0000
commitbc85fd5a6df8753543ba55c98a588e255471752b (patch)
treeb51e3eb5c77cca042081bb7ba88e5515560451d2 /cpukit/score/cpu/i960/cpu.c
parentPatch rtems-rc-20000711-2-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff)
downloadrtems-bc85fd5a6df8753543ba55c98a588e255471752b.tar.bz2
Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information are now in libcpu. This required significant rework of the score/cpu header files and the creation of multiple header files and subdirectories in libcpu/i960.
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/i960/cpu.c108
1 files changed, 0 insertions, 108 deletions
diff --git a/cpukit/score/cpu/i960/cpu.c b/cpukit/score/cpu/i960/cpu.c
index 009e0d3ca4..78eeb3c5f2 100644
--- a/cpukit/score/cpu/i960/cpu.c
+++ b/cpukit/score/cpu/i960/cpu.c
@@ -11,18 +11,6 @@
*
* $Id$
*/
-/*
- * 1999/04/26: added support for Intel i960RP
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#elif defined(__i960RP__)
-#elif defined(__i960KA__)
-
-#else
-#warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***"
-#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
-#endif
#include <rtems/system.h>
#include <rtems/score/isr.h>
@@ -64,45 +52,6 @@ unsigned32 _CPU_ISR_Get_level( void )
/*PAGE
*
- * _CPU_ISR_install_raw_handler
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define i960_vector_caching_enabled( _prcb ) \
- ((_prcb)->control_tbl->icon & 0x2000)
-#elif defined(__i960RP__)
-#define i960_vector_caching_enabled( _prcb ) \
- ((*((unsigned int *) ICON_ADDR)) & 0x2000)
-#elif defined(__i960KA__)
-#define i960_vector_caching_enabled( _prcb ) 0
-#endif
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- i960_PRCB *prcb = _CPU_Table.Prcb;
- proc_ptr *cached_intr_tbl = NULL;
-
- /* The i80960CA does not support vectors 0-7. The first 9 entries
- * in the Interrupt Table are used to manage pending interrupts.
- * Thus vector 8, the first valid vector number, is actually in
- * slot 9 in the table.
- */
-
- *old_handler = prcb->intr_tbl[ vector + 1 ];
-
- prcb->intr_tbl[ vector + 1 ] = new_handler;
-
- if ( i960_vector_caching_enabled( prcb ) )
- if ( (vector & 0xf) == 0x2 ) /* cacheable? */
- cached_intr_tbl[ vector >> 4 ] = new_handler;
-}
-
-/*PAGE
- *
* _CPU__ISR_install_vector
*
* Install the RTEMS vector wrapper in the CPU's interrupt table.
@@ -130,60 +79,3 @@ void _CPU_ISR_install_vector(
_ISR_Vector_table[ vector ] = new_handler;
}
-
-/*PAGE
- *
- * _CPU_Install_interrupt_stack
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define soft_reset( prcb ) \
- { register i960_PRCB *_prcb = (prcb); \
- register unsigned32 *_next=0; \
- register unsigned32 _cmd = 0x30000; \
- asm volatile( "lda next,%1; \
- sysctl %0,%1,%2; \
- next: mov g0,g0" \
- : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
- : "0" (_cmd), "1" (_next), "2" (_prcb) ); \
- }
-#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
-#define soft_reset( prcb ) \
- { register i960_PRCB *_prcb = (prcb); \
- register unsigned32 *_next=0; \
- register unsigned32 _cmd = 0x300; \
- asm volatile( "lda next,%1; \
- sysctl %0,%1,%2; \
- next: mov g0,g0" \
- : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
- : "0" (_cmd), "1" (_next), "2" (_prcb) ); \
- }
-#elif defined(__i960KA__)
-#define soft_reset( prcb )
-#endif
-
-void _CPU_Install_interrupt_stack( void )
-{
- i960_PRCB *prcb = _CPU_Table.Prcb;
- unsigned32 level;
-#if defined(__i960RP__) || defined(__i960_RP__)
- unsigned32 *isp = (int *) ISP_ADDR;
-#endif
-
- /*
- * Set the Interrupt Stack in the PRCB and force a reload of it.
- * Interrupts are disabled for safety.
- */
-
- _CPU_ISR_Disable( level );
-
- prcb->intr_stack = _CPU_Interrupt_stack_low;
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
- soft_reset( prcb );
-#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
- *isp = (unsigned32) prcb->intr_stack;
-#endif
-
- _CPU_ISR_Enable( level );
-}