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authorJoel Sherrill <joel.sherrill@OARcorp.com>1999-02-18 18:28:24 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1999-02-18 18:28:24 +0000
commit7908ba5b8139c73cc45bacb686199ca48c0d803c (patch)
tree62de3f920a3b3d270db9185f4d8a64b5d7136a8f /cpukit/score/cpu/hppa1.1
parentAnother part of automake VI patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff)
downloadrtems-7908ba5b8139c73cc45bacb686199ca48c0d803c.tar.bz2
Part of the automake VI patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:
> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh > > reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a > similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff > contains the diffs after reorg-score-cpu.sh has been run on a > rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff. > > This patch is rather nasty and may break something. However, I've tested > it for about 10 different target/bsp pairs and believe to have shaken > out most bugs. I wonder about the following .h files that were not moved: a29k/asm.h a29k/cpu_asm.h i386/asm.h i960/asm.h m68k/asm.h m68k/m68302.h m68k/m68360.h m68k/qsm.h m68k/sim.h mips64orion/asm.h mips64orion/cpu_asm.h mips64orion/mips64orion.h no_cpu/asm.h no_cpu/cpu_asm.h powerpc/asm.h powerpc/mpc860.h sh/asm.h sparc/asm.h sparc/erc32.h
Diffstat (limited to 'cpukit/score/cpu/hppa1.1')
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/cpu.h620
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h73
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/hppa.h716
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/types.h46
4 files changed, 1455 insertions, 0 deletions
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h b/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h
new file mode 100644
index 0000000000..ea13c01a66
--- /dev/null
+++ b/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h
@@ -0,0 +1,620 @@
+/* cpu.h
+ *
+ * This include file contains information pertaining to the HP
+ * PA-RISC processor (Level 1.1).
+ *
+ * COPYRIGHT (c) 1994 by Division Incorporated
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Note:
+ * This file is included by both C and assembler code ( -DASM )
+ *
+ * $Id$
+ */
+
+#ifndef __CPU_h
+#define __CPU_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/hppa.h> /* pick up machine definitions */
+#ifndef ASM
+#include <rtems/score/hppatypes.h>
+#endif
+
+/* conditional compilation parameters */
+
+#define CPU_INLINE_ENABLE_DISPATCH FALSE
+#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
+
+/*
+ * RTEMS manages an interrupt stack in software for the HPPA.
+ */
+
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
+
+/*
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
+ * HPPA has hardware FP, it is assumed to exist by GCC so all tasks
+ * may implicitly use it (especially for integer multiplies). Because
+ * the FP context is technically part of the basic integer context
+ * on this CPU, we cannot use the deferred FP context switch algorithm.
+ */
+
+#define CPU_HARDWARE_FP TRUE
+#define CPU_ALL_TASKS_ARE_FP TRUE
+#define CPU_IDLE_TASK_IS_FP FALSE
+#define CPU_USE_DEFERRED_FP_SWITCH FALSE
+
+#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
+#define CPU_STACK_GROWS_UP TRUE
+#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32)))
+
+/*
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
+ */
+
+#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
+#define CPU_BIG_ENDIAN TRUE
+#define CPU_LITTLE_ENDIAN FALSE
+
+/* constants */
+
+#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */
+#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
+
+/*
+ * PSW contstants
+ */
+
+#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
+#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I)
+#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE)
+
+#define CPU_PSW_DEFAULT CPU_PSW_BASE
+
+
+#ifndef ASM
+
+/*
+ * Contexts
+ *
+ * This means we have the following context items:
+ * 1. task level context stuff:: Context_Control
+ * 2. floating point task stuff:: Context_Control_fp
+ *
+ * The PA-RISC is very fast so the expense of saving an extra register
+ * or two is not of great concern at the present. So we are not making
+ * a distinction between what is saved during a task switch and what is
+ * saved at each interrupt. Plus saving the entire context should make
+ * it easier to make gdb aware of RTEMS tasks.
+ */
+
+typedef struct {
+ unsigned32 flags; /* whatever */
+ unsigned32 gr1; /* scratch -- caller saves */
+ unsigned32 gr2; /* RP -- return pointer */
+ unsigned32 gr3; /* scratch -- callee saves */
+ unsigned32 gr4; /* scratch -- callee saves */
+ unsigned32 gr5; /* scratch -- callee saves */
+ unsigned32 gr6; /* scratch -- callee saves */
+ unsigned32 gr7; /* scratch -- callee saves */
+ unsigned32 gr8; /* scratch -- callee saves */
+ unsigned32 gr9; /* scratch -- callee saves */
+ unsigned32 gr10; /* scratch -- callee saves */
+ unsigned32 gr11; /* scratch -- callee saves */
+ unsigned32 gr12; /* scratch -- callee saves */
+ unsigned32 gr13; /* scratch -- callee saves */
+ unsigned32 gr14; /* scratch -- callee saves */
+ unsigned32 gr15; /* scratch -- callee saves */
+ unsigned32 gr16; /* scratch -- callee saves */
+ unsigned32 gr17; /* scratch -- callee saves */
+ unsigned32 gr18; /* scratch -- callee saves */
+ unsigned32 gr19; /* scratch -- caller saves */
+ unsigned32 gr20; /* scratch -- caller saves */
+ unsigned32 gr21; /* scratch -- caller saves */
+ unsigned32 gr22; /* scratch -- caller saves */
+ unsigned32 gr23; /* argument 3 */
+ unsigned32 gr24; /* argument 2 */
+ unsigned32 gr25; /* argument 1 */
+ unsigned32 gr26; /* argument 0 */
+ unsigned32 gr27; /* DP -- global data pointer */
+ unsigned32 gr28; /* return values -- caller saves */
+ unsigned32 gr29; /* return values -- caller saves */
+ unsigned32 sp; /* gr30 */
+ unsigned32 gr31;
+
+ /* Various control registers */
+
+ unsigned32 sar; /* cr11 */
+ unsigned32 ipsw; /* cr22; full 32 bits of psw */
+ unsigned32 iir; /* cr19; interrupt instruction register */
+ unsigned32 ior; /* cr21; interrupt offset register */
+ unsigned32 isr; /* cr20; interrupt space register (not used) */
+ unsigned32 pcoqfront; /* cr18; front que offset */
+ unsigned32 pcoqback; /* cr18; back que offset */
+ unsigned32 pcsqfront; /* cr17; front que space (not used) */
+ unsigned32 pcsqback; /* cr17; back que space (not used) */
+ unsigned32 itimer; /* cr16; itimer value */
+
+} Context_Control;
+
+
+/* Must be double word aligned.
+ * This will be ok since our allocator returns 8 byte aligned chunks
+ */
+
+typedef struct {
+ double fr0; /* status */
+ double fr1; /* exception information */
+ double fr2; /* exception information */
+ double fr3; /* exception information */
+ double fr4; /* argument */
+ double fr5; /* argument */
+ double fr6; /* argument */
+ double fr7; /* argument */
+ double fr8; /* scratch -- caller saves */
+ double fr9; /* scratch -- caller saves */
+ double fr10; /* scratch -- caller saves */
+ double fr11; /* scratch -- caller saves */
+ double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */
+ double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */
+ double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */
+} Context_Control_fp;
+
+/*
+ * The following structure defines the set of information saved
+ * on the current stack by RTEMS upon receipt of each interrupt.
+ */
+
+typedef struct {
+ Context_Control Integer;
+ Context_Control_fp Floating_Point;
+} CPU_Interrupt_frame;
+
+/*
+ * Our interrupt handlers take a 2nd argument:
+ * a pointer to a CPU_Interrupt_frame
+ * So we use our own prototype instead of rtems_isr_entry
+ */
+
+typedef void ( *hppa_rtems_isr_entry )(
+ unsigned32,
+ CPU_Interrupt_frame *
+ );
+
+/*
+ * The following table contains the information required to configure
+ * the HPPA specific parameters.
+ */
+
+typedef struct {
+ void (*pretasking_hook)( void );
+ void (*predriver_hook)( void );
+ void (*postdriver_hook)( void );
+ void (*idle_task)( void );
+ boolean do_zero_of_workspace;
+ unsigned32 idle_task_stack_size;
+ unsigned32 interrupt_stack_size;
+ unsigned32 extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( unsigned32 );
+ void (*stack_free_hook)( void * );
+ /* end of fields required on all CPUs */
+
+ hppa_rtems_isr_entry spurious_handler;
+
+ unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */
+} rtems_cpu_table;
+
+/* variables */
+
+SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
+SCORE_EXTERN unsigned32 _CPU_Default_gr27;
+SCORE_EXTERN void *_CPU_Interrupt_stack_low;
+SCORE_EXTERN void *_CPU_Interrupt_stack_high;
+
+#endif /* ! ASM */
+
+/*
+ * context sizes
+ */
+
+#ifndef ASM
+#define CPU_CONTEXT_SIZE sizeof( Context_Control )
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+#endif
+
+/*
+ * size of a frame on the stack
+ */
+
+#define CPU_FRAME_SIZE (16 * 4)
+
+/*
+ * (Optional) # of bytes for libmisc/stackchk to check
+ * If not specifed, then it defaults to something reasonable
+ * for most architectures.
+ */
+
+#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2)
+
+/*
+ * extra stack required by the MPCI receive server thread
+ */
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/*
+ * HPPA has 32 traps, then 32 external interrupts
+ * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
+ * The BSP is aware of the external interrupts and possibly more.
+ *
+ */
+
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS)
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/*
+ * Don't be chintzy here; we don't want to debug these problems
+ * Some of the tests eat almost 4k.
+ * Plus, the HPPA always allocates chunks of 64 bytes for stack
+ * growth.
+ */
+
+#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
+
+/*
+ * HPPA double's must be on 8 byte boundary
+ */
+
+#define CPU_ALIGNMENT 8
+
+/*
+ * just follow the basic HPPA alignment for the heap and partition
+ */
+
+#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
+#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
+
+/*
+ * HPPA stack is best when 64 byte aligned.
+ */
+
+#define CPU_STACK_ALIGNMENT 64
+
+#ifndef ASM
+
+/* macros */
+
+/*
+ * ISR handler macros
+ *
+ * These macros perform the following functions:
+ * + disable all maskable CPU interrupts
+ * + restore previous interrupt level (enable)
+ * + temporarily restore interrupts (flash)
+ * + set a particular level
+ */
+
+/* Disable interrupts; returning previous psw bits in _isr_level */
+#define _CPU_ISR_Disable( _isr_level ) \
+ do { \
+ HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \
+ if (_isr_level & HPPA_PSW_I) _isr_level = 0; \
+ else _isr_level = 1; \
+ } while(0)
+
+/* Enable interrupts to previous level from _CPU_ISR_Disable
+ * does not change 'level' */
+#define _CPU_ISR_Enable( _isr_level ) \
+ { \
+ register int _ignore; \
+ if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
+ else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
+ }
+
+/* restore, then disable interrupts; does not change level */
+#define _CPU_ISR_Flash( _isr_level ) \
+ { \
+ if (_isr_level == 0) \
+ { \
+ register int _ignore; \
+ HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
+ HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
+ } \
+ }
+
+/*
+ * Interrupt task levels
+ *
+ * Future scheme proposal
+ * level will be an index into a array.
+ * Each entry of array will be the interrupt bits
+ * enabled for that level. There will be 32 bits of external
+ * interrupts (to be placed in EIEM) and some (optional) bsp
+ * specific bits
+ *
+ * For pixel flow this *may* mean something like:
+ * level 0: all interrupts enabled (external + rhino)
+ * level 1: rhino disabled
+ * level 2: all io interrupts disabled (timer still enabled)
+ * level 7: *ALL* disabled (timer disabled)
+ */
+
+/* set interrupts on or off; does not return new level */
+#define _CPU_ISR_Set_level( new_level ) \
+ { \
+ volatile int ignore; \
+ if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
+ else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
+ }
+
+/* return current level */
+unsigned32 _CPU_ISR_Get_level( void );
+
+/* end of ISR handler macros */
+
+/*
+ * Context handler macros
+ *
+ * These macros perform the following functions:
+ * + initialize a context area
+ * + restart the current thread
+ * + calculate the initial pointer into a FP context area
+ * + initialize an FP context area
+ *
+ * HPPA port adds two macros which hide the "indirectness" of the
+ * pointer passed the save/restore FP context assembly routines.
+ */
+
+#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
+ _new_level, _entry_point, _is_fp ) \
+ do { \
+ unsigned32 _stack; \
+ \
+ (_the_context)->flags = 0xfeedf00d; \
+ (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
+ (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \
+ (_the_context)->pcsqfront = 0; \
+ (_the_context)->pcsqback = 0; \
+ if ( (_new_level) ) \
+ (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
+ else \
+ (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
+ \
+ _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
+ _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
+ if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
+ _stack += CPU_FRAME_SIZE; \
+ \
+ (_the_context)->sp = (_stack); \
+ (_the_context)->gr27 = _CPU_Default_gr27; \
+ } while (0)
+
+#define _CPU_Context_Restart_self( _the_context ) \
+ do { \
+ _CPU_Context_restore( (_the_context) ); \
+ } while (0)
+
+#define _CPU_Context_Fp_start( _base, _offset ) \
+ ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+
+#define _CPU_Context_Initialize_fp( _destination ) \
+ do { \
+ *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
+ } while(0)
+
+#define _CPU_Context_save_fp( _fp_context ) \
+ _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
+
+#define _CPU_Context_restore_fp( _fp_context ) \
+ _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
+
+/* end of Context handler macros */
+
+/*
+ * Fatal Error manager macros
+ *
+ * These macros perform the following functions:
+ * + disable interrupts and halt the CPU
+ */
+
+void hppa_cpu_halt(unsigned32 the_error);
+#define _CPU_Fatal_halt( _error ) \
+ hppa_cpu_halt(_error)
+
+/* end of Fatal Error manager macros */
+
+/*
+ * Bitfield handler macros
+ *
+ * These macros perform the following functions:
+ * + scan for the highest numbered (MSB) set in a 16 bit bitfield
+ *
+ * NOTE:
+ *
+ * The HPPA does not have a scan instruction. This functionality
+ * is implemented in software.
+ */
+
+#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
+#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
+
+int hppa_rtems_ffs(unsigned int value);
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+ _output = hppa_rtems_ffs(_value)
+
+/* end of Bitfield handler macros */
+
+/*
+ * Priority handler macros
+ *
+ * These macros perform the following functions:
+ * + return a mask with the bit for this major/minor portion of
+ * of thread priority set.
+ * + translate the bit number returned by "Bitfield_find_first_bit"
+ * into an index into the thread ready chain bit maps
+ *
+ * Note: 255 is the lowest priority
+ */
+
+#define _CPU_Priority_Mask( _bit_number ) \
+ ( 1 << (_bit_number) )
+
+#define _CPU_Priority_bits_index( _priority ) \
+ (_priority)
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/*
+ * _CPU_Initialize
+ *
+ * This routine performs CPU dependent initialization.
+ */
+
+void _CPU_Initialize(
+ rtems_cpu_table *cpu_table,
+ void (*thread_dispatch)
+);
+
+/*
+ * _CPU_ISR_install_raw_handler
+ *
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
+ */
+
+void _CPU_ISR_install_raw_handler(
+ unsigned32 vector,
+ proc_ptr new_handler,
+ proc_ptr *old_handler
+);
+
+/*
+ * _CPU_ISR_install_vector
+ *
+ * This routine installs an interrupt vector.
+ */
+
+void _CPU_ISR_install_vector(
+ unsigned32 vector,
+ proc_ptr new_handler,
+ proc_ptr *old_handler
+);
+
+/*
+ * _CPU_Context_switch
+ *
+ * This routine switches from the run context to the heir context.
+ */
+
+void _CPU_Context_switch(
+ Context_Control *run,
+ Context_Control *heir
+);
+
+/*
+ * _CPU_Context_restore
+ *
+ * This routine is generally used only to restart self in an
+ * efficient manner and avoid stack conflicts.
+ */
+
+void _CPU_Context_restore(
+ Context_Control *new_context
+);
+
+/*
+ * _CPU_Save_float_context
+ *
+ * This routine saves the floating point context passed to it.
+ *
+ * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
+ * which dereferences the pointer before calling this.
+ */
+
+void _CPU_Save_float_context(
+ Context_Control_fp *fp_context
+);
+
+/*
+ * _CPU_Restore_float_context
+ *
+ * This routine restores the floating point context passed to it.
+ *
+ * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
+ * which dereferences the pointer before calling this.
+ */
+
+void _CPU_Restore_float_context(
+ Context_Control_fp *fp_context
+);
+
+
+/*
+ * The raw interrupt handler for external interrupts
+ */
+
+extern void _Generic_ISR_Handler(
+ void
+);
+
+
+/* The following routine swaps the endian format of an unsigned int.
+ * It must be static so it can be referenced indirectly.
+ */
+
+static inline unsigned int
+CPU_swap_u32(unsigned32 value)
+{
+ unsigned32 swapped;
+
+ HPPA_ASM_SWAPBYTES(value, swapped);
+
+ return( swapped );
+}
+
+#define CPU_swap_u16( value ) \
+ (((value&0xff) << 8) | ((value >> 8)&0xff))
+
+#endif /* ! ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! __CPU_h */
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h b/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h
new file mode 100644
index 0000000000..951f80dcf0
--- /dev/null
+++ b/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 1990,1991 The University of Utah and
+ * the Center for Software Science (CSS). All rights reserved.
+ *
+ * Permission to use, copy, modify and distribute this software is hereby
+ * granted provided that (1) source code retains these copyright, permission,
+ * and disclaimer notices, and (2) redistributions including binaries
+ * reproduce the notices in supporting documentation, and (3) all advertising
+ * materials mentioning features or use of this software display the following
+ * acknowledgement: ``This product includes software developed by the Center
+ * for Software Science at the University of Utah.''
+ *
+ * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
+ * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF
+ * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * CSS requests users of this software to return to css-dist@cs.utah.edu any
+ * improvements that they make and grant CSS redistribution rights.
+ *
+ * Utah $Hdr: asm.h 1.6 91/12/03$
+ *
+ * $Id$
+ */
+
+/*
+ * Hardware Space Registers
+ */
+sr0 .reg %sr0
+sr1 .reg %sr1
+sr2 .reg %sr2
+sr3 .reg %sr3
+sr4 .reg %sr4
+sr5 .reg %sr5
+sr6 .reg %sr6
+sr7 .reg %sr7
+
+/*
+ * Control register aliases
+ */
+
+rctr .reg %cr0
+pidr1 .reg %cr8
+pidr2 .reg %cr9
+ccr .reg %cr10
+sar .reg %cr11
+pidr3 .reg %cr12
+pidr4 .reg %cr13
+iva .reg %cr14
+eiem .reg %cr15
+itmr .reg %cr16
+pcsq .reg %cr17
+pcoq .reg %cr18
+iir .reg %cr19
+isr .reg %cr20
+ior .reg %cr21
+ipsw .reg %cr22
+eirr .reg %cr23
+
+/*
+ * Calling Convention
+ */
+rp .reg %r2
+arg3 .reg %r23
+arg2 .reg %r24
+arg1 .reg %r25
+arg0 .reg %r26
+dp .reg %r27
+ret0 .reg %r28
+ret1 .reg %r29
+sl .reg %r29
+sp .reg %r30
+
+
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h b/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h
new file mode 100644
index 0000000000..049981ea84
--- /dev/null
+++ b/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h
@@ -0,0 +1,716 @@
+/*
+ * Description:
+ *
+ * Definitions for HP PA Risc
+ * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
+ *
+ * COPYRIGHT (c) 1994 by Division Incorporated
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * Note:
+ * This file is included by both C and assembler code ( -DASM )
+ *
+ * $Id$
+ */
+
+#ifndef _INCLUDE_HPPA_H
+#define _INCLUDE_HPPA_H
+
+#ifdef ASM
+#include <rtems/score/targopts.h>
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*
+ * This section contains the information required to build
+ * RTEMS for a particular member of the Hewlett Packard
+ * PA-RISC family. It does this by setting variables to
+ * indicate which implementation dependent features are
+ * present in a particular member of the family.
+ */
+
+#if defined(hppa7100)
+
+#define CPU_MODEL_NAME "hppa 7100"
+
+#elif defined(hppa7200)
+
+#define CPU_MODEL_NAME "hppa 7200"
+
+#else
+
+#error "Unsupported CPU Model"
+
+#endif
+
+/*
+ * Define the name of the CPU family.
+ */
+
+#if !defined(CPU_NAME)
+#define CPU_NAME "HP PA-RISC 1.1"
+#endif
+
+/*
+ * Processor Status Word (PSW) Masks
+ */
+
+
+#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
+#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
+#define HPPA_PSW_r2 0x20000000 /* reserved */
+#define HPPA_PSW_r3 0x10000000 /* reserved */
+#define HPPA_PSW_r4 0x08000000 /* reserved */
+#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
+#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
+#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
+#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
+#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
+#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
+#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
+#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
+#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
+#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
+#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
+#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
+#define HPPA_PSW_r24 0x00000080 /* reserved */
+#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
+#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
+#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
+#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
+#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
+#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
+#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
+ /* Low-Priority Machine Check */
+ /* Interruption Enable */
+
+/*
+ * HPPA traps and interrupts
+ * basic layout. Note numbers do not denote priority
+ *
+ * 0-31 basic traps and interrupts defined by HPPA architecture
+ * 0-31 32 external interrupts
+ * 32-... bsp defined
+ */
+
+#define HPPA_TRAP_NON_EXISTENT 0
+/* group 1 */
+#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
+/* group 2 */
+#define HPPA_TRAP_POWER_FAIL 2
+#define HPPA_TRAP_RECOVERY_COUNTER 3
+#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
+#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
+#define HPPA_TRAP_PERFORMANCE_MONITOR 29
+/* group 3 */
+#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
+#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
+#define HPPA_TRAP_INSTRUCTION_DEBUG 30
+#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
+#define HPPA_TRAP_BREAK_INSTRUCTION 9
+#define HPPA_TRAP_PRIVILEGED_OPERATION 10
+#define HPPA_TRAP_PRIVILEGED_REGISTER 11
+#define HPPA_TRAP_OVERFLOW 12
+#define HPPA_TRAP_CONDITIONAL 13
+#define HPPA_TRAP_ASSIST_EXCEPTION 14
+#define HPPA_TRAP_DATA_TLB_MISS 15
+#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
+#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
+#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
+#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
+#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
+#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
+#define HPPA_TRAP_DATA_MEMORY_BREAK 19
+#define HPPA_TRAP_TLB_DIRTY_BIT 20
+#define HPPA_TRAP_PAGE_REFERENCE 21
+#define HPPA_TRAP_DATA_DEBUG 31
+#define HPPA_TRAP_ASSIST_EMULATION 22
+/* group 4 */
+#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
+#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
+#define HPPA_TRAP_TAKEN_BRANCH 25
+
+#define HPPA_INTERNAL_TRAPS 32
+
+/* External Interrupts via interrupt 4 */
+
+#define HPPA_INTERRUPT_EXTERNAL_0 0
+#define HPPA_INTERRUPT_EXTERNAL_1 1
+#define HPPA_INTERRUPT_EXTERNAL_2 2
+#define HPPA_INTERRUPT_EXTERNAL_3 3
+#define HPPA_INTERRUPT_EXTERNAL_4 4
+#define HPPA_INTERRUPT_EXTERNAL_5 5
+#define HPPA_INTERRUPT_EXTERNAL_6 6
+#define HPPA_INTERRUPT_EXTERNAL_7 7
+#define HPPA_INTERRUPT_EXTERNAL_8 8
+#define HPPA_INTERRUPT_EXTERNAL_9 9
+#define HPPA_INTERRUPT_EXTERNAL_10 10
+#define HPPA_INTERRUPT_EXTERNAL_11 11
+#define HPPA_INTERRUPT_EXTERNAL_12 12
+#define HPPA_INTERRUPT_EXTERNAL_13 13
+#define HPPA_INTERRUPT_EXTERNAL_14 14
+#define HPPA_INTERRUPT_EXTERNAL_15 15
+#define HPPA_INTERRUPT_EXTERNAL_16 16
+#define HPPA_INTERRUPT_EXTERNAL_17 17
+#define HPPA_INTERRUPT_EXTERNAL_18 18
+#define HPPA_INTERRUPT_EXTERNAL_19 19
+#define HPPA_INTERRUPT_EXTERNAL_20 20
+#define HPPA_INTERRUPT_EXTERNAL_21 21
+#define HPPA_INTERRUPT_EXTERNAL_22 22
+#define HPPA_INTERRUPT_EXTERNAL_23 23
+#define HPPA_INTERRUPT_EXTERNAL_24 24
+#define HPPA_INTERRUPT_EXTERNAL_25 25
+#define HPPA_INTERRUPT_EXTERNAL_26 26
+#define HPPA_INTERRUPT_EXTERNAL_27 27
+#define HPPA_INTERRUPT_EXTERNAL_28 28
+#define HPPA_INTERRUPT_EXTERNAL_29 29
+#define HPPA_INTERRUPT_EXTERNAL_30 30
+#define HPPA_INTERRUPT_EXTERNAL_31 31
+
+#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
+#define HPPA_EXTERNAL_INTERRUPTS 32
+
+/* BSP defined interrupts begin here */
+
+#define HPPA_INTERRUPT_MAX 32
+
+/*
+ * Cache characteristics
+ */
+
+#define HPPA_CACHELINE_SIZE 32
+#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
+
+/*
+ * page size characteristics
+ */
+
+#define HPPA_PAGE_SIZE 4096
+#define HPPA_PAGE_MASK (0xfffff000)
+
+
+/*
+ * TLB characteristics
+ *
+ * Flags and Access Control layout for using TLB protection insertion
+ *
+ * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
+ * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |?|?|T|D|B|type |PL1|Pl2|U| access id |?|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ */
+
+/*
+ * Access rights (type + PL1 + PL2)
+ */
+#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
+#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
+#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
+#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
+#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
+#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
+#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
+#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
+
+/*
+ * Floating point status register definitions
+ */
+
+#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
+#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
+#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
+#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
+#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
+#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
+#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
+#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
+#define HPPA_FPSTATUS_RM_SHIFT 9
+#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
+#define HPPA_FPSTATUS_CQ_SHIFT 13
+#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
+#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
+#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
+#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
+#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
+#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
+
+
+/*
+ * Inline macros for misc. interesting opcodes
+ */
+
+/* generate a global label */
+#define HPPA_ASM_LABEL(label) \
+ asm(".export " label ", ! .label " label);
+
+/* Return From Interrupt RFI */
+#define HPPA_ASM_RFI() asm volatile ("rfi")
+
+/* Set System Mask SSM i,t */
+#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
+ : "=r" (gr) \
+ : "i" (i))
+/* Reset System Mask RSM i,t */
+#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
+ : "=r" (gr) \
+ : "i" (i))
+/* Move To System Mask MTSM r */
+#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
+ : : "r" (gr))
+
+/* Load Space Identifier LDSID (s,b),t */
+#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (grb))
+
+/*
+ * Gcc extended asm doesn't really allow for treatment of space registers
+ * as "registers", so we have to use "i" format.
+ * Unfortunately this means that the "=" constraint is not available.
+ */
+
+/* Move To Space Register MTSP r,sr */
+#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
+ : : "i" (sr), \
+ "r" (gr))
+
+/* Move From Space Register MFSP sr,t */
+#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
+ : "=r" (gr) \
+ : "i" (sr))
+
+/* Move To Control register MTCTL r,t */
+#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
+ : : "i" (cr), \
+ "r" (gr))
+
+/* Move From Control register MFCTL r,t */
+#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
+ : "=r" (gr) \
+ : "i" (cr))
+
+/* Synchronize caches SYNC */
+#define HPPA_ASM_SYNC() asm volatile ("sync")
+
+/* Probe Read Access PROBER (s,b),r,t */
+#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
+ asm volatile ("prober (%1,%2),%3,%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (groff), \
+ "r" (gracc))
+
+/* Probe Read Access Immediate PROBERI (s,b),i,t*/
+#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
+ asm volatile ("proberi (%1,%2),%3,%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (groff), \
+ "i" (iacc))
+
+/* Probe Write Access PROBEW (s,b),r,t */
+#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
+ asm volatile ("probew (%1,%2),%3,%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (groff), \
+ "r" (gracc))
+
+/* Probe Write Access Immediate PROBEWI (s,b),i,t */
+#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
+ asm volatile ("probewi (%1,%2),%3,%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (groff), \
+ "i" (iacc))
+
+/* Load Physical Address LPA x(s,b),t */
+#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
+ : "=r" (grt) \
+ : "i" (sr), \
+ "r" (grb))
+
+/* Load Coherence Index LCI x(s,b),t */
+/* AKA: Load Hash Address LHA x(s,b),t */
+#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
+ : "=r" (grt) \
+ : "r" (grx),\
+ "i" (sr), \
+ "r" (grb))
+#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
+
+/* Purge Data Tlb PDTLB x(s,b) */
+#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Purge Instruction Tlb PITLB x(s,b) */
+#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Purge Data Tlb Entry PDTLBE x(s,b) */
+#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Purge Instruction Tlb Entry PITLBE x(s,b) */
+#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+
+/* Insert Data TLB Address IDTLBA r,(s,b) */
+#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
+ : : "r" (gr), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Insert Instruction TLB Address IITLBA r,(s,b) */
+#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
+ : : "r" (gr), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Insert Data TLB Protection IDTLBP r,(s,b) */
+#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
+ : : "r" (gr), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Insert Instruction TLB Protection IITLBP r,(s,b) */
+#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
+ : : "r" (gr), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Purge Data Cache PDC x(s,b) */
+#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Flush Data Cache FDC x(s,b) */
+#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Flush Instruction Cache FDC x(s,b) */
+#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Flush Data Cache Entry FDCE x(s,b) */
+#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Flush Instruction Cache Entry FICE x(s,b) */
+#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
+ : : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Break BREAK i5,i13 */
+#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
+ : : "i" (i5), \
+ "i" (i13))
+
+/* Load and Clear Word Short LDCWS d(s,b),t */
+#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
+ : "=r" (grt) \
+ : "i" (i), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Load and Clear Word Indexed LDCWX x(s,b),t */
+#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
+ : "=r" (grt) \
+ : "r" (grx), \
+ "i" (sr), \
+ "r" (grb))
+
+/* Load Word Absolute Short LDWAS d(b),t */
+/* NOTE: "short" here means "short displacement" */
+#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
+ : "=r" (gr) \
+ : "i" (disp), \
+ "r" (grbase))
+
+/* Store Word Absolute Short STWAS r,d(b) */
+/* NOTE: "short" here means "short displacement" */
+#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
+ : : "r" (gr), \
+ "i" (disp), \
+ "r" (grbase))
+
+/*
+ * Swap bytes
+ * REFERENCE: PA72000 TRM -- Appendix C
+ */
+#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
+ " shd %1,%1,16,%0 \n\
+ dep %0,15,8,%0 \n\
+ shd %1,%0,8,%0" \
+ : "=r" (swapped) \
+ : "r" (value) \
+ )
+
+
+/* 72000 Diagnose instructions follow
+ * These macros assume gas knows about these instructions.
+ * gas2.2.u1 did not.
+ * I added them to my copy and installed it locally.
+ *
+ * There are *very* special requirements for these guys
+ * ref: TRM 6.1.3 Programming Constraints
+ *
+ * The macros below handle the following rules
+ *
+ * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
+ * Must never be nullified (hence the leading nop)
+ * NOP must preced every RDD,RDT,WDD,WDT,RDTLB
+ * Instruction preceeding GR_SHDW must not set any of the GR's saved
+ *
+ * The macros do *NOT* deal with the following problems
+ * doubled DIAGNOSE instructions must not straddle a page boundary
+ * if code translation enabled. (since 2nd could trap on ITLB)
+ * If you care about DHIT and DPE bits of DR0, then
+ * No store instruction in the 2 insn window before RDD
+ */
+
+
+/* Move To CPU/DIAG register MTCPU r,t */
+#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
+ " mtcpu %1,%0 \n" \
+ " mtcpu %1,%0" \
+ : : "i" (dr), \
+ "r" (gr))
+
+/* Move From CPU/DIAG register MFCPU r,t */
+#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
+ " mfcpu %1,%0\n" \
+ " mfcpu %1,%0" \
+ : "=r" (gr) \
+ : "i" (dr))
+
+/* Transfer of Control Enable TOC_EN */
+#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
+ " tocen")
+
+/* Transfer of Control Disable TOC_DIS */
+#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
+ " tocdis")
+
+/* Shadow Registers to General Register SHDW_GR */
+#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
+ " shdwgr" \
+ ::: "r1" "r8" "r9" "r16" \
+ "r17" "r24" "r25")
+
+/* General Registers to Shadow Register GR_SHDW */
+#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
+ " grshdw \n" \
+ " grshdw")
+
+/*
+ * Definitions of special registers for use by the above macros.
+ */
+
+/* Hardware Space Registers */
+#define HPPA_SR0 0
+#define HPPA_SR1 1
+#define HPPA_SR2 2
+#define HPPA_SR3 3
+#define HPPA_SR4 4
+#define HPPA_SR5 5
+#define HPPA_SR6 6
+#define HPPA_SR7 7
+
+/* Hardware Control Registers */
+#define HPPA_CR0 0
+#define HPPA_RCTR 0 /* Recovery Counter Register */
+
+#define HPPA_CR8 8 /* Protection ID 1 */
+#define HPPA_PIDR1 8
+
+#define HPPA_CR9 9 /* Protection ID 2 */
+#define HPPA_PIDR2 9
+
+#define HPPA_CR10 10
+#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
+
+#define HPPA_CR11 11
+#define HPPA_SAR 11 /* Shift Amount Register */
+
+#define HPPA_CR12 12
+#define HPPA_PIDR3 12 /* Protection ID 3 */
+
+#define HPPA_CR13 13
+#define HPPA_PIDR4 13 /* Protection ID 4 */
+
+#define HPPA_CR14 14
+#define HPPA_IVA 14 /* Interrupt Vector Address */
+
+#define HPPA_CR15 15
+#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
+
+#define HPPA_CR16 16
+#define HPPA_ITMR 16 /* Interval Timer */
+
+#define HPPA_CR17 17
+#define HPPA_PCSQ 17 /* Program Counter Space queue */
+
+#define HPPA_CR18 18
+#define HPPA_PCOQ 18 /* Program Counter Offset queue */
+
+#define HPPA_CR19 19
+#define HPPA_IIR 19 /* Interruption Instruction Register */
+
+#define HPPA_CR20 20
+#define HPPA_ISR 20 /* Interruption Space Register */
+
+#define HPPA_CR21 21
+#define HPPA_IOR 21 /* Interruption Offset Register */
+
+#define HPPA_CR22 22
+#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
+
+#define HPPA_CR23 23
+#define HPPA_EIRR 23 /* External Interrupt Request */
+
+#define HPPA_CR24 24
+#define HPPA_PPDA 24 /* Physcial Page Directory Address */
+#define HPPA_TR0 24 /* Temporary register 0 */
+
+#define HPPA_CR25 25
+#define HPPA_HTA 25 /* Hash Table Address */
+#define HPPA_TR1 25 /* Temporary register 1 */
+
+#define HPPA_CR26 26
+#define HPPA_TR2 26 /* Temporary register 2 */
+
+#define HPPA_CR27 27
+#define HPPA_TR3 27 /* Temporary register 3 */
+
+#define HPPA_CR28 28
+#define HPPA_TR4 28 /* Temporary register 4 */
+
+#define HPPA_CR29 29
+#define HPPA_TR5 29 /* Temporary register 5 */
+
+#define HPPA_CR30 30
+#define HPPA_TR6 30 /* Temporary register 6 */
+
+#define HPPA_CR31 31
+#define HPPA_CPUID 31 /* MP identifier */
+
+/*
+ * Diagnose registers
+ */
+
+#define HPPA_DR0 0
+#define HPPA_DR1 1
+#define HPPA_DR8 8
+#define HPPA_DR24 24
+#define HPPA_DR25 25
+
+/*
+ * Tear apart a break instruction to find its type.
+ */
+#define HPPA_BREAK5(x) ((x) & 0x1F)
+#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
+
+/* assemble a break instruction */
+#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13))
+
+
+/*
+ * this won't work in ASM or non-GNU compilers
+ */
+
+#if !defined(ASM) && defined(__GNUC__)
+
+/*
+ * static inline utility functions to get at control registers
+ */
+
+#define EMIT_GET_CONTROL(name, reg) \
+static __inline__ unsigned int \
+get_ ## name (void) \
+{ \
+ unsigned int value; \
+ HPPA_ASM_MFCTL(reg, value); \
+ return value; \
+}
+
+#define EMIT_SET_CONTROL(name, reg) \
+static __inline__ void \
+set_ ## name (unsigned int new_value) \
+{ \
+ HPPA_ASM_MTCTL(new_value, reg); \
+}
+
+#define EMIT_CONTROLS(name, reg) \
+ EMIT_GET_CONTROL(name, reg) \
+ EMIT_SET_CONTROL(name, reg)
+
+EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
+EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
+EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
+EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
+EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
+EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
+EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
+EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
+EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
+EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
+EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
+EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
+EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
+EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
+EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
+EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
+EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
+EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
+EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
+EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
+EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
+EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
+EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
+EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
+EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
+EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
+
+#endif /* ASM and GNU */
+
+/*
+ * If and How to invoke the debugger (a ROM debugger generally)
+ */
+#define CPU_INVOKE_DEBUGGER \
+ do { \
+ HPPA_ASM_BREAK(1,1); \
+ } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! _INCLUDE_HPPA_H */
+
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/types.h b/cpukit/score/cpu/hppa1.1/rtems/score/types.h
new file mode 100644
index 0000000000..512323819b
--- /dev/null
+++ b/cpukit/score/cpu/hppa1.1/rtems/score/types.h
@@ -0,0 +1,46 @@
+/* hppatypes.h
+ *
+ * This include file contains type definitions pertaining to the Hewlett
+ * Packard PA-RISC processor family.
+ *
+ * $Id$
+ */
+
+#ifndef _INCLUDE_HPPATYPES_H
+#define _INCLUDE_HPPATYPES_H
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This section defines the basic types for this processor.
+ */
+
+typedef unsigned char unsigned8; /* 8-bit unsigned integer */
+typedef unsigned short unsigned16; /* 16-bit unsigned integer */
+typedef unsigned int unsigned32; /* 32-bit unsigned integer */
+typedef unsigned long long unsigned64; /* 64-bit unsigned integer */
+
+typedef unsigned16 Priority_Bit_map_control;
+
+typedef signed char signed8; /* 8-bit signed integer */
+typedef signed short signed16; /* 16-bit signed integer */
+typedef signed int signed32; /* 32-bit signed integer */
+typedef signed long long signed64; /* 64 bit signed integer */
+
+typedef unsigned32 boolean; /* Boolean value */
+
+typedef float single_precision; /* single precision float */
+typedef double double_precision; /* double precision float */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !ASM */
+
+#endif /* _INCLUDE_HPPATYPES_H */
+/* end of include file */