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authorJoel Sherrill <joel.sherrill@OARcorp.com>2006-01-16 15:12:44 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2006-01-16 15:12:44 +0000
commitece004d72a6ef2968c56fb32295606642fd0b4c5 (patch)
tree21b2d31bf21181c46a5f2db745742e6fff070e73 /cpukit/score/cpu/h8300/rtems/score
parent2006-01-16 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-ece004d72a6ef2968c56fb32295606642fd0b4c5.tar.bz2
2006-01-16 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Part of a large patch to improve Doxygen output. As a side-effect, grammar and spelling errors were corrected, spacing errors were address, and some variable names were improved.
Diffstat (limited to 'cpukit/score/cpu/h8300/rtems/score')
-rw-r--r--cpukit/score/cpu/h8300/rtems/score/cpu.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h
index 735ff448b9..c7f3b3c77b 100644
--- a/cpukit/score/cpu/h8300/rtems/score/cpu.h
+++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h
@@ -6,7 +6,7 @@
* This include file contains information pertaining to the H8300
* processor.
*
- * COPYRIGHT (c) 1989-1999.
+ * COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -136,8 +136,7 @@ extern "C" {
* If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization.
*
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
*
* H8300 Specific Information:
*
@@ -531,7 +530,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
/*
- * Should be large enough to run all RTEMS tests. This insures
+ * Should be large enough to run all RTEMS tests. This ensures
* that a "reasonable" small application should not have any problems.
*
* H8300 Specific Information:
@@ -1147,7 +1146,7 @@ void _CPU_Context_restore_fp(
* Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to insure that
+ * that interrupts would probably have to be disabled to ensure that
* an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code