This is the initial addition of the port of RTEMS to the

Hitachi H8 family.  This port was done by Philip Quaife
<philip@qs.co.nz> of Q Solutions and sponsored by
Comnet Technologies Ltd.  The port was done based on RTEMS 3.5.1
to a Hitach H8300H.  The port was updated to RTEMS 4.5 style
Makefiles/configure by Joel Sherrill <joel@OARcorp.com>.
While doing this Joel added support for the h8300-rtems to
binutils, gcc, newlib, and gdb.

NOTE:  Philip submitted a BSP for a Hitachi evaluation board
which is being merged as a separate entity.

1 files changed, 174 insertions, 0 deletions

diff --git a/cpukit/score/cpu/h8300/cpu.c b/cpukit/score/cpu/h8300/cpu.c
new file mode 100644
index 0000000000..f01c39d969
--- /dev/null
+++ b/cpukit/score/cpu/h8300/cpu.c
@@ -0,0 +1,174 @@
+/*
+ *  Hitachi H8300 CPU Dependent Source
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ */
+
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+  /*
+   *  The thread_dispatch argument is the address of the entry point
+   *  for the routine called at the end of an ISR once it has been
+   *  decided a context switch is necessary.  On some compilation
+   *  systems it is difficult to call a high-level language routine
+   *  from assembly.  This allows us to trick these systems.
+   *
+   *  If you encounter this problem save the entry point in a CPU
+   *  dependent variable.
+   */
+
+  _CPU_Thread_dispatch_pointer = thread_dispatch;
+
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+
+  _CPU_Table = *cpu_table;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ *
+ *  This routine returns the current interrupt level.
+ */
+ 
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  unsigned int _ccr;
+
+#if defined(__H8300__)
+#warning "How do we get ccr on base CPU models"
+#else
+  asm volatile ( "stc ccr, %0" : "=m" (_ccr) : );
+#endif
+
+  if ( _ccr & 0x80 )
+    return 1;
+  return 0;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   *  Use Debug level IRQ Handlers
+   */
+  H8BD_Install_IRQ(vector,new_handler,old_handler);
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ */
+
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+/*PAGE
+ *
+ *  _CPU_Thread_Idle_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ */
+
+#if 0
+void _CPU_Thread_Idle_body( void )
+{
+
+  for( ; ; )
+    IDLE_Monitor();
+	/*asm("	sleep	\n"); */
+    /* insert your "halt" instruction here */ ;
+}
+#endif