diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-10 15:41:37 +0000 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2008-09-10 15:41:37 +0000 |
commit | 7a28ac8880b580689a225ed3776b70a15f96bcec (patch) | |
tree | 3697b9062e3c68ab9261f1629c614b6bfb73e483 /cpukit/score/cpu/c4x/irq.c | |
parent | 2008-09-10 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
download | rtems-7a28ac8880b580689a225ed3776b70a15f96bcec.tar.bz2 |
2008-09-10 Joel Sherrill <joel.sherrill@OARcorp.com>
* configure.ac, aclocal/canonical-target-name.m4: Readd NIOS2 and TI
C4x. Accidentally not done on 4.9 branch. :(
* score/cpu/c4x/.cvsignore, score/cpu/c4x/ChangeLog,
score/cpu/c4x/Makefile.am, score/cpu/c4x/cpu.c,
score/cpu/c4x/cpu_asm.S, score/cpu/c4x/irq.c,
score/cpu/c4x/preinstall.am, score/cpu/c4x/rtems/asm.h,
score/cpu/c4x/rtems/score/c4x.h, score/cpu/c4x/rtems/score/cpu.h,
score/cpu/c4x/rtems/score/cpu_asm.h,
score/cpu/c4x/rtems/score/types.h, score/cpu/c4x/rtems/tic4x/c4xio.h,
score/cpu/nios2/.cvsignore, score/cpu/nios2/ChangeLog,
score/cpu/nios2/Makefile.am, score/cpu/nios2/cpu.c,
score/cpu/nios2/cpu_asm.S, score/cpu/nios2/irq.c,
score/cpu/nios2/preinstall.am, score/cpu/nios2/rtems/asm.h,
score/cpu/nios2/rtems/score/cpu.h,
score/cpu/nios2/rtems/score/cpu_asm.h,
score/cpu/nios2/rtems/score/nios2.h,
score/cpu/nios2/rtems/score/types.h: New files.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/c4x/irq.c | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/cpukit/score/cpu/c4x/irq.c b/cpukit/score/cpu/c4x/irq.c new file mode 100644 index 0000000000..104b3afdc4 --- /dev/null +++ b/cpukit/score/cpu/c4x/irq.c @@ -0,0 +1,89 @@ +/* + * C4x CPU Dependent Source + * + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems/system.h> +#include <rtems/score/cpu.h> +#include <rtems/score/isr.h> +#include <rtems/score/thread.h> + +/* + * This routine provides the RTEMS interrupt management. + */ + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr asm("sp"); + +void __ISR_Handler(uint32_t vector, void *isr_sp) +{ + register uint32_t level; + + /* already disabled when we get here */ + /* _CPU_ISR_Disable( level ); */ + + _Thread_Dispatch_disable_level++; + +#if 0 + if ( stack_ptr > (_Thread_Executing->Start.stack + + _Thread_Executing->Start.Initial_stack.size) ) { + printk( "Blown interrupt stack at 0x%x\n", stack_ptr ); + } +#endif + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if ( _ISR_Nest_level == 0 ) { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_low; + } +#endif + + _ISR_Nest_level++; + + /* leave it to the ISR to decide if they get reenabled */ + /* _CPU_ISR_Enable( level ); */ + + /* call isp */ + if ( _ISR_Vector_table[ vector] ) + (*_ISR_Vector_table[ vector ])( + vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 ); + + _CPU_ISR_Disable( level ); + + _ISR_Nest_level--; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */ + stack_ptr = _old_stack_ptr; +#endif + + _Thread_Dispatch_disable_level--; + + _CPU_ISR_Enable( level ); + + if ( _ISR_Nest_level ) + return; + + if ( _Thread_Dispatch_disable_level ) { + _ISR_Signals_to_thread_executing = FALSE; + return; + } + + if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) { + _ISR_Signals_to_thread_executing = FALSE; + _Thread_Dispatch(); + } +} |