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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-10-23 17:17:50 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-10-23 17:17:50 +0000 |
commit | d9a6ab3fed9e77a6343ee56571e4d9d767c8e979 (patch) | |
tree | 5cbb0283798520905ed50d799d1f19de959e7a55 /cpukit/score/cpu/bfin/cpu.c | |
parent | 2006-10-22 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
download | rtems-d9a6ab3fed9e77a6343ee56571e4d9d767c8e979.tar.bz2 |
2006-10-23 Joel Sherrill <joel@OARcorp.com>
* .cvsignore, ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c,
preinstall.am, rtems/asm.h, rtems/score/bfin.h, rtems/score/cpu.h,
rtems/score/cpu_asm.h, rtems/score/types.h: New files.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/bfin/cpu.c | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/cpukit/score/cpu/bfin/cpu.c b/cpukit/score/cpu/bfin/cpu.c new file mode 100644 index 0000000000..aa52e0e10b --- /dev/null +++ b/cpukit/score/cpu/bfin/cpu.c @@ -0,0 +1,225 @@ +/* Blackfin CPU Dependent Source + * + * Copyright (c) 2006 by Atos Automacao Industrial Ltda. + * written by Alain Schaefer <alain.schaefer@easc.ch> + * and Antonio Giovanini <antonio@atos.com.br> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> +#include <rtems/score/bfin.h> + +/* _CPU_Initialize + * + * This routine performs processor dependent initialization. + * + * INPUT PARAMETERS: + * cpu_table - CPU table to initialize + * thread_dispatch - address of disptaching routine + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch) /* ignored on this CPU */ +) +{ + /* + * The thread_dispatch argument is the address of the entry point + * for the routine called at the end of an ISR once it has been + * decided a context switch is necessary. On some compilation + * systems it is difficult to call a high-level language routine + * from assembly. This allows us to trick these systems. + * + * If you encounter this problem save the entry point in a CPU + * dependent variable. + */ + + _CPU_Thread_dispatch_pointer = thread_dispatch; + + /* + * If there is not an easy way to initialize the FP context + * during Context_Initialize, then it is usually easier to + * save an "uninitialized" FP context here and copy it to + * the task's during Context_Initialize. + */ + + /* FP context initialization support goes here */ + + _CPU_Table = *cpu_table; +} + +/*PAGE + * + * _CPU_ISR_Get_level + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +uint32_t _CPU_ISR_Get_level( void ) +{ + /* + * This routine returns the current interrupt level. + */ + + register uint32_t _tmpimask; + + /*read from the IMASK registers*/ + + _tmpimask = *((uint32_t*)IMASK); + + return _tmpimask; +} + +/*PAGE + * + * _CPU_ISR_install_raw_handler + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr *interrupt_table = NULL; + /* + * This is where we install the interrupt handler into the "raw" interrupt + * table used by the CPU to dispatch interrupt handlers. + */ + + /* base of vector table on blackfin architecture */ + interrupt_table = (void*)0xFFE02000; + + *old_handler = interrupt_table[ vector ]; + interrupt_table[ vector ] = new_handler; + +} + +/*PAGE + * + * _CPU_ISR_install_vector + * + * This kernel routine installs the RTEMS handler for the + * specified vector. + * + * Input parameters: + * vector - interrupt vector number + * old_handler - former ISR for this vector number + * new_handler - replacement ISR for this vector number + * + * Output parameters: NONE + * + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + + /* + * If the interrupt vector table is a table of pointer to isr entry + * points, then we need to install the appropriate RTEMS interrupt + * handler for this vector number. + */ + + _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); + + /* + * We put the actual user ISR address in '_ISR_vector_table'. This will + * be used by the _ISR_Handler so the user gets control. + */ + + _ISR_Vector_table[ vector ] = new_handler; +} + +/* + * Copied from the arm port. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + uint32_t *stack_base, + uint32_t size, + uint32_t new_level, + void *entry_point, + boolean is_fp +) +{ + uint32_t stack_high; /* highest "stack aligned" address */ + stack_high = ((uint32_t )(stack_base) + size); + + the_context->register_sp = stack_high; + // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp + // is this correct ????? + the_context->register_fp = stack_high; + the_context->register_rets = (uint32_t) entry_point; + + //mask the interrupt level +} + + + +/*PAGE + * + * _CPU_Install_interrupt_stack + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_Install_interrupt_stack( void ) +{ +} + +/*PAGE + * + * _CPU_Thread_Idle_body + * + * NOTES: + * + * 1. This is the same as the regular CPU independent algorithm. + * + * 2. If you implement this using a "halt", "idle", or "shutdown" + * instruction, then don't forget to put it in an infinite loop. + * + * 3. Be warned. Some processors with onboard DMA have been known + * to stop the DMA if the CPU were put in IDLE mode. This might + * also be a problem with other on-chip peripherals. So use this + * hook with caution. + * + * NO_CPU Specific Information: + * + * XXX document implementation including references if appropriate + */ + +void _CPU_Thread_Idle_body( void ) +{ + + for( ; ; ) + /* insert your "halt" instruction here */ ; +} |