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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-01-13 14:51:55 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-01-17 08:14:12 +0100 |
commit | 12a2a8e4426c05161aa76a9c86de1e36e43e8a61 (patch) | |
tree | 2fc95f72415a243cc05aa7aae73586ea18f0cd3d /cpukit/score/cpu/arm/include/rtems | |
parent | arm: Fix stack alignment during interrupt handling (diff) | |
download | rtems-12a2a8e4426c05161aa76a9c86de1e36e43e8a61.tar.bz2 |
arm: Optimize interrupt handling
Use the SRS (Store Return State) instruction if available. This
considerably simplifies the context save and restore.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/arm/include/rtems/score/arm.h | 1 | ||||
-rw-r--r-- | cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h | 13 |
2 files changed, 14 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/include/rtems/score/arm.h b/cpukit/score/cpu/arm/include/rtems/score/arm.h index b1e4b07a37..7eaa69d889 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/include/rtems/score/arm.h @@ -47,6 +47,7 @@ extern "C" { #define ARM_MULTILIB_HAS_WFI #define ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE #define ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS + #define ARM_MULTILIB_HAS_STORE_RETURN_STATE #endif #ifndef ARM_DISABLE_THREAD_ID_REGISTER_USE diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h index 0f86710966..a6fe74e9ad 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h @@ -79,6 +79,18 @@ typedef struct { double d6; double d7; #endif /* ARM_MULTILIB_VFP */ +#ifdef ARM_MULTILIB_HAS_STORE_RETURN_STATE + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r7; + uint32_t r9; + uint32_t r12; + uint32_t lr; + uint32_t return_pc; + uint32_t return_cpsr; +#else /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ uint32_t r9; uint32_t lr; uint32_t r0; @@ -89,6 +101,7 @@ typedef struct { uint32_t return_cpsr; uint32_t r7; uint32_t r12; +#endif /* ARM_MULTILIB_HAS_STORE_RETURN_STATE */ } CPU_Interrupt_frame; #ifdef RTEMS_SMP |