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authorSebastian Huber <sebastian.huber@embedded-brains.de>2017-06-09 07:25:02 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2017-06-09 07:30:41 +0200
commit32b4a0c42704f0076da8e2d5411290f55d1b2965 (patch)
treeb8b10e79ed076140e3b0a9f88833ef3582d8b23c /cpukit/score/cpu/arm/cpu_asm.S
parenta66accc5532ee661df19d7334bbf8da7fa0248d7 (diff)
downloadrtems-32b4a0c42704f0076da8e2d5411290f55d1b2965.tar.bz2
Simplify TLS support in context switch
There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize().
Diffstat (limited to 'cpukit/score/cpu/arm/cpu_asm.S')
-rw-r--r--cpukit/score/cpu/arm/cpu_asm.S13
1 files changed, 2 insertions, 11 deletions
diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index 52ea77aae1..f58b99dc6c 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -56,24 +56,15 @@
DEFINE_FUNCTION_ARM(_CPU_Context_switch)
/* Start saving context */
GET_SELF_CPU_CONTROL r2
+ ldr r3, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
stm r0, {r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- mrc p15, 0, r3, c13, c0, 3
-#endif
-
- ldr r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE]
-
#ifdef ARM_MULTILIB_VFP
add r5, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET
vstm r5, {d8-d15}
#endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
- str r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
-#endif
-
- str r4, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
+ str r3, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE]
#ifdef RTEMS_SMP
/*