2011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* rtems/score/armv7m.h, armv7m-context-initialize.c,
	armv7m-context-restore.c, armv7m-context-switch.c,
	armv7m-exception-handler-get.c, armv7m-exception-handler-set.c,
	armv7m-exception-priority-get.c, armv7m-exception-priority-set.c,
	armv7m-initialize.c, armv7m-isr-dispatch.c, armv7m-isr-enter-leave.c,
	armv7m-isr-level-get.c, armv7m-isr-level-set.c,
	armv7m-isr-vector-install.c, armv7m-multitasking-start-stop.c: New
	files.
	* Makefile.am, preinstall.am: Reflect changes above.
	* rtems/score/arm.h: Define ARM_MULTILIB_ARCH_V4 and
	ARM_MULTILIB_ARCH_V7M.
	* rtems/score/cpu.h, cpu_asm.S, cpu.c, arm_exc_abort.S,
	arm_exc_handler_high.c, arm_exc_handler_low.S, arm_exc_interrupt.S:
	Define CPU_HAS_HARDWARE_INTERRUPT_STACK to FALSE.  Use
	ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M.

1 files changed, 65 insertions, 0 deletions

diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
new file mode 100644
index 0000000000..42ea404f0f
--- /dev/null
+++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/score/percpu.h>
+
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+#include <rtems/score/armv7m.h>
+
+static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
+{
+  __asm__ volatile (
+    "bl _Thread_Dispatch\n"
+    /* FIXME: SVC, binutils bug */
+    ".short 0xdf00\n"
+    "nop\n"
+  );
+}
+
+void _ARMV7M_Pendable_service_call( void )
+{
+  _ISR_Nest_level = 1;
+  _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
+  ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
+  --ef;
+  _ARMV7M_Set_PSP((uint32_t) ef);
+
+  /*
+   * According to "ARMv7-M Architecture Reference Manual" section B1.5.6
+   * "Exception entry behavior" the return address is half-word aligned.
+   */
+  ef->register_pc = (void *)
+    ((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
+
+  ef->register_xpsr = 0x01000000U;
+}
+
+void _ARMV7M_Supervisor_call( void )
+{
+  ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
+  ++ef;
+  _ARMV7M_Set_PSP((uint32_t) ef);
+  _ISR_Nest_level = 0;
+  RTEMS_COMPILER_MEMORY_BARRIER();
+  if ( _Thread_Dispatch_necessary ) {
+    _ARMV7M_Pendable_service_call();
+  }
+}
+
+#endif /* ARM_MULTILIB_ARCH_V7M */