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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-03-09 14:32:04 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-08-10 08:21:04 +0200 |
| commit | 5cc276e7c1a7fb5808749da6f504a18db34c941f (patch) | |
| tree | eba4adb07bd043fbf71131e9f8e46b2ada794f55 /cpukit/score/cpu/arm/arm-context-volatile-clobber.S | |
| parent | arm: Fix ARMv7-M interrupt processing (diff) | |
| download | rtems-5cc276e7c1a7fb5808749da6f504a18db34c941f.tar.bz2 | |
arm: Fix CPU context validation for Cortex-R4
Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
Close #3092.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/arm/arm-context-volatile-clobber.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index 7970b8e690..23facdb88f 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -29,8 +29,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) #ifdef ARM_MULTILIB_VFP vmrs r1, FPSCR - movs r2, #0x001f - movt r2, #0xf800 + ldr r2, =0xf000001f bic r1, r1, r2 and r2, r2, r0 orr r1, r1, r2 |