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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-08-11 16:27:32 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-10-01 14:03:26 -0500 |
| commit | 9c2cb68481635fa72b7c08644df70b3df037f430 (patch) | |
| tree | df06735b9939b6f80ca0d903f941eb927a05c89d /cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | |
| parent | cpukit/aarch64: Use correct context register sets (diff) | |
| download | rtems-9c2cb68481635fa72b7c08644df70b3df037f430.tar.bz2 | |
cpukit/aarch64: Use correct interrupt level types
All other architectures use uint32_t for interrupt levels and there is
no reason not to do so on AArch64.
Diffstat (limited to 'cpukit/score/cpu/aarch64/include/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h index 82f74193a2..ae7e2bdcba 100644 --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h @@ -204,9 +204,9 @@ static inline void _AARCH64_Instruction_synchronization_barrier( void ) __asm__ volatile ( "isb" : : : "memory" ); } -void _CPU_ISR_Set_level( uint64_t level ); +void _CPU_ISR_Set_level( uint32_t level ); -uint64_t _CPU_ISR_Get_level( void ); +uint32_t _CPU_ISR_Get_level( void ); #if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE) uint64_t AArch64_interrupt_disable( void ); |