LIBPCI: converted to BSD header

14 files changed, 1833 insertions, 1158 deletions

diff --git a/cpukit/libpci/Makefile.am b/cpukit/libpci/Makefile.am
index d7ca5ccba9..b9e5fd2add 100644
--- a/cpukit/libpci/Makefile.am
+++ b/cpukit/libpci/Makefile.am
@@ -15,7 +15,8 @@ include_pcidir = $(includedir)/pci
 include_pci_HEADERS =	pci/access.h pci/cfg.h \
 			pci/cfg_auto.h pci/cfg_static.h \
 			pci/cfg_peripheral.h pci/cfg_read.h \
-			pci/ids.h pci/ids_extra.h pci/irq.h
+			pci/ids.h pci/ids_extra.h pci/irq.h \
+			pci/pcireg.h
 
 noinst_LIBRARIES = libpci.a
 
diff --git a/cpukit/libpci/pci.h b/cpukit/libpci/pci.h
index e9955bc6a2..fc33bbb18a 100644
--- a/cpukit/libpci/pci.h
+++ b/cpukit/libpci/pci.h
@@ -1,285 +1,24 @@
 /*
+ * PCI library. Defines in this file was taken from FreeBSD and auto-generated
+ * pci_ids.h reused from RTEMS.
  *
- *	PCI defines and function prototypes
- *	Copyright 1994, Drew Eckhardt
- *	Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- * 
- *      New PCI library written from scratch. Defines in this file was reused.
- *      auto-generated pci_ids.h also reused.
- *      Copyright 2009, Cobham Gaisler AB
+ * COPYRIGHT (c) 2009 Cobham Gaisler AB.
  *
- *	For more information, please consult the following manuals (look at
- *	http://www.pcisig.com/ for how to get them):
- *
- *	PCI BIOS Specification
- *	PCI Local Bus Specification
- *	PCI to PCI Bridge Specification
- *	PCI System Design Guide
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
  */
 
 #ifndef __PCI_H__
 #define __PCI_H__
 
+#include <pci/pcireg.h>
 #include <pci/ids.h>
 
-/*
- * Under PCI, each device has 256 bytes of configuration address space,
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID		0x00	/* 16 bits */
-#define PCI_DEVICE_ID		0x02	/* 16 bits */
-#define PCI_COMMAND		0x04	/* 16 bits */
-#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
-#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
-#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
-#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
-#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
-#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
-#define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
-#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
-#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
-
-#define PCI_STATUS		0x06	/* 16 bits */
-#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features */
-
-#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
-#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
-#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST	0x000
-#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
-#define  PCI_STATUS_DEVSEL_SLOW 0x400
-#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
-#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
-#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
-#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
-#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
-
-#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
-					   revision */
-#define PCI_REVISION_ID         0x08    /* Revision ID */
-#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE        0x0a    /* Device class */
-
-#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
-#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
-#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
-#define  PCI_HEADER_TYPE_NORMAL	0
-#define  PCI_HEADER_TYPE_BRIDGE 1
-#define  PCI_HEADER_TYPE_CARDBUS 2
-
-#define PCI_BIST		0x0f	/* 8 bits */
-#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
-#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
-#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
-
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of
- * 0xffffffff to the register, and reading it back. Only
- * 1 bits are decoded.
- */
-#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
-#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
-#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
-#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
-#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
-#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
-#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
-#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
-#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
-#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
-/* bit 1 is reserved if address_space = 1 */
-
-/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS		0x28
-#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
-#define PCI_SUBSYSTEM_ID	0x2e
-#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
-#define  PCI_ROM_ADDRESS_ENABLE	0x01
-#define  PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
-
-/* 0x34 Capabilities Pointer (PCI 2.3) */
-#define PCI_CAP_PTR		0x34	/* 8 bits */
-
-/* 0x35-0x3b are reserved */
-#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
-#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
-#define PCI_MIN_GNT		0x3e	/* 8 bits */
-#define PCI_MAX_LAT		0x3f	/* 8 bits */
-
-/* Header type 1 (PCI-to-PCI bridges) */
-#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
-#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
-#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
-#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
-#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
-#define PCI_IO_LIMIT		0x1d
-#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */
-#define  PCI_IO_RANGE_TYPE_16	0x00
-#define  PCI_IO_RANGE_TYPE_32	0x01
-#define  PCI_IO_RANGE_MASK	(~0x0f)
-#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
-#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
-#define PCI_MEMORY_LIMIT	0x22
-#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
-#define  PCI_MEMORY_RANGE_MASK	(~0x0f)
-#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
-#define PCI_PREF_MEMORY_LIMIT	0x26
-#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
-#define  PCI_PREF_RANGE_TYPE_32	0x00
-#define  PCI_PREF_RANGE_TYPE_64	0x01
-#define  PCI_PREF_RANGE_MASK	(~0x0f)
-#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
-#define PCI_PREF_LIMIT_UPPER32	0x2c
-#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
-#define PCI_IO_LIMIT_UPPER16	0x32
-/* 0x34-0x3b is reserved */
-#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_BRIDGE_CONTROL	0x3e
-#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
-#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
-#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
-#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
-#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
-#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
-#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
-
-/* Header type 2 (CardBus bridges) */
-/* 0x14-0x15 reserved */
-#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
-#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
-#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
-#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
-#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
-#define PCI_CB_MEMORY_BASE_0	0x1c
-#define PCI_CB_MEMORY_LIMIT_0	0x20
-#define PCI_CB_MEMORY_BASE_1	0x24
-#define PCI_CB_MEMORY_LIMIT_1	0x28
-#define PCI_CB_IO_BASE_0	0x2c
-#define PCI_CB_IO_BASE_0_HI	0x2e
-#define PCI_CB_IO_LIMIT_0	0x30
-#define PCI_CB_IO_LIMIT_0_HI	0x32
-#define PCI_CB_IO_BASE_1	0x34
-#define PCI_CB_IO_BASE_1_HI	0x36
-#define PCI_CB_IO_LIMIT_1	0x38
-#define PCI_CB_IO_LIMIT_1_HI	0x3a
-#define  PCI_CB_IO_RANGE_MASK	(~0x03)
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_CB_BRIDGE_CONTROL	0x3e
-#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
-#define  PCI_CB_BRIDGE_CTL_SERR		0x02
-#define  PCI_CB_BRIDGE_CTL_ISA		0x04
-#define  PCI_CB_BRIDGE_CTL_VGA		0x08
-#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
-#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
-#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
-#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
-#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
-#define PCI_CB_SUBSYSTEM_ID	0x42
-#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
-/* 0x48-0x7f reserved */
-
-/* Device classes and subclasses */
-
-#define PCI_CLASS_NOT_DEFINED		0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
-
-#define PCI_BASE_CLASS_STORAGE		0x01
-#define PCI_CLASS_STORAGE_SCSI		0x0100
-#define PCI_CLASS_STORAGE_IDE		0x0101
-#define PCI_CLASS_STORAGE_FLOPPY	0x0102
-#define PCI_CLASS_STORAGE_IPI		0x0103
-#define PCI_CLASS_STORAGE_RAID		0x0104
-#define PCI_CLASS_STORAGE_OTHER		0x0180
-
-#define PCI_BASE_CLASS_NETWORK		0x02
-#define PCI_CLASS_NETWORK_ETHERNET	0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
-#define PCI_CLASS_NETWORK_FDDI		0x0202
-#define PCI_CLASS_NETWORK_ATM		0x0203
-#define PCI_CLASS_NETWORK_OTHER		0x0280
-
-#define PCI_BASE_CLASS_DISPLAY		0x03
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_CLASS_DISPLAY_XGA		0x0301
-#define PCI_CLASS_DISPLAY_OTHER		0x0380
-
-#define PCI_BASE_CLASS_MULTIMEDIA	0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
-#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
-
-#define PCI_BASE_CLASS_MEMORY		0x05
-#define  PCI_CLASS_MEMORY_RAM		0x0500
-#define  PCI_CLASS_MEMORY_FLASH		0x0501
-#define  PCI_CLASS_MEMORY_OTHER		0x0580
-
-#define PCI_BASE_CLASS_BRIDGE		0x06
-#define  PCI_CLASS_BRIDGE_HOST		0x0600
-#define  PCI_CLASS_BRIDGE_ISA		0x0601
-#define  PCI_CLASS_BRIDGE_EISA		0x0602
-#define  PCI_CLASS_BRIDGE_MC		0x0603
-#define  PCI_CLASS_BRIDGE_PCI		0x0604
-#define  PCI_CLASS_BRIDGE_PCMCIA	0x0605
-#define  PCI_CLASS_BRIDGE_NUBUS		0x0606
-#define  PCI_CLASS_BRIDGE_CARDBUS	0x0607
-#define  PCI_CLASS_BRIDGE_OTHER		0x0680
-
-#define PCI_BASE_CLASS_COMMUNICATION	0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
-
-#define PCI_BASE_CLASS_SYSTEM		0x08
-#define PCI_CLASS_SYSTEM_PIC		0x0800
-#define PCI_CLASS_SYSTEM_DMA		0x0801
-#define PCI_CLASS_SYSTEM_TIMER		0x0802
-#define PCI_CLASS_SYSTEM_RTC		0x0803
-#define PCI_CLASS_SYSTEM_OTHER		0x0880
-
-#define PCI_BASE_CLASS_INPUT		0x09
-#define PCI_CLASS_INPUT_KEYBOARD	0x0900
-#define PCI_CLASS_INPUT_PEN		0x0901
-#define PCI_CLASS_INPUT_MOUSE		0x0902
-#define PCI_CLASS_INPUT_OTHER		0x0980
-
-#define PCI_BASE_CLASS_DOCKING		0x0a
-#define PCI_CLASS_DOCKING_GENERIC	0x0a00
-#define PCI_CLASS_DOCKING_OTHER		0x0a01
-
-#define PCI_BASE_CLASS_PROCESSOR	0x0b
-#define PCI_CLASS_PROCESSOR_386		0x0b00
-#define PCI_CLASS_PROCESSOR_486		0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
-#define PCI_CLASS_PROCESSOR_CO		0x0b40
-
-#define PCI_BASE_CLASS_SERIAL		0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
-#define PCI_CLASS_SERIAL_ACCESS		0x0c01
-#define PCI_CLASS_SERIAL_SSA		0x0c02
-#define PCI_CLASS_SERIAL_USB		0x0c03
-#define PCI_CLASS_SERIAL_FIBER		0x0c04
-
-#define PCI_CLASS_OTHERS		0xff
-
 #define PCI_INVALID_VENDORDEVICEID    0xffffffff
-#define PCI_MULTI_FUNCTION            0x80
 
-#define PCI_MAX_DEVICES			32
-#define PCI_MAX_FUNCTIONS		8
+#define PCID_CLASS(class, dev) ((class << 8) | dev)
+#define PCID_PCI2PCI_BRIDGE PCID_CLASS(PCIC_BRIDGE, PCIS_BRIDGE_PCI)
 
 #include <pci/access.h>
 
diff --git a/cpukit/libpci/pci/access.h b/cpukit/libpci/pci/access.h
index 990aaaefdf..7755b7a475 100644
--- a/cpukit/libpci/pci/access.h
+++ b/cpukit/libpci/pci/access.h
@@ -131,32 +131,32 @@ extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val);
 /* Enable Memory in command register */
 static inline void pci_mem_enable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, PCI_COMMAND_MEMORY);
+	pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, PCIM_CMD_MEMEN);
 }
 
 static inline void pci_mem_disable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, 0);
+	pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, 0);
 }
 
 static inline void pci_io_enable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_IO, PCI_COMMAND_IO);
+	pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, PCIM_CMD_PORTEN);
 }
 
 static inline void pci_io_disable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_IO, 0);
+	pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, 0);
 }
 
 static inline void pci_master_enable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, PCI_COMMAND_MASTER);
+	pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, PCIM_CMD_BUSMASTEREN);
 }
 
 static inline void pci_master_disable(pci_dev_t dev)
 {
-	pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, 0);
+	pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, 0);
 }
 
 /* Configuration Space Access Read Routines */
diff --git a/cpukit/libpci/pci/ids.h b/cpukit/libpci/pci/ids.h
index 2d2592bc03..d4ce5f57ef 100644
--- a/cpukit/libpci/pci/ids.h
+++ b/cpukit/libpci/pci/ids.h
@@ -13,790 +13,790 @@
  * (and according to card ID within vendor). Send all updates to
  * <linux-pcisupport@cck.uni-kl.de>.
  */
-#define PCI_VENDOR_ID_COMPAQ		0x0e11
-#define PCI_DEVICE_ID_COMPAQ_1280	0x3033
-#define PCI_DEVICE_ID_COMPAQ_TRIFLEX	0x4000
-#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
-#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
-#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
-#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
-#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
-#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
-#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
-
-#define PCI_VENDOR_ID_NCR		0x1000
-#define PCI_DEVICE_ID_NCR_53C810	0x0001
-#define PCI_DEVICE_ID_NCR_53C820	0x0002
-#define PCI_DEVICE_ID_NCR_53C825	0x0003
-#define PCI_DEVICE_ID_NCR_53C815	0x0004
-#define PCI_DEVICE_ID_NCR_53C860	0x0006
-#define PCI_DEVICE_ID_NCR_53C896	0x000b
-#define PCI_DEVICE_ID_NCR_53C895	0x000c
-#define PCI_DEVICE_ID_NCR_53C885	0x000d
-#define PCI_DEVICE_ID_NCR_53C875	0x000f
-#define PCI_DEVICE_ID_NCR_53C875J	0x008f
-
-#define PCI_VENDOR_ID_ATI		0x1002
-#define PCI_DEVICE_ID_ATI_68800		0x4158
-#define PCI_DEVICE_ID_ATI_215CT222	0x4354
-#define PCI_DEVICE_ID_ATI_210888CX	0x4358
-#define PCI_DEVICE_ID_ATI_215GB		0x4742
-#define PCI_DEVICE_ID_ATI_215GD		0x4744
-#define PCI_DEVICE_ID_ATI_215GI		0x4749
-#define PCI_DEVICE_ID_ATI_215GP		0x4750
-#define PCI_DEVICE_ID_ATI_215GQ		0x4751
-#define PCI_DEVICE_ID_ATI_215GT		0x4754
-#define PCI_DEVICE_ID_ATI_215GTB	0x4755
-#define PCI_DEVICE_ID_ATI_210888GX	0x4758
-#define PCI_DEVICE_ID_ATI_215LG		0x4c47
-#define PCI_DEVICE_ID_ATI_264LT		0x4c54
-#define PCI_DEVICE_ID_ATI_264VT		0x5654
-
-#define PCI_VENDOR_ID_VLSI		0x1004
-#define PCI_DEVICE_ID_VLSI_82C592	0x0005
-#define PCI_DEVICE_ID_VLSI_82C593	0x0006
-#define PCI_DEVICE_ID_VLSI_82C594	0x0007
-#define PCI_DEVICE_ID_VLSI_82C597	0x0009
-#define PCI_DEVICE_ID_VLSI_82C541	0x000c
-#define PCI_DEVICE_ID_VLSI_82C543	0x000d
-#define PCI_DEVICE_ID_VLSI_82C532	0x0101
-#define PCI_DEVICE_ID_VLSI_82C534	0x0102
-#define PCI_DEVICE_ID_VLSI_82C535	0x0104
-#define PCI_DEVICE_ID_VLSI_82C147	0x0105
-#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
-
-#define PCI_VENDOR_ID_ADL		0x1005
-#define PCI_DEVICE_ID_ADL_2301		0x2301
-
-#define PCI_VENDOR_ID_NS		0x100b
-#define PCI_DEVICE_ID_NS_87415		0x0002
-#define PCI_DEVICE_ID_NS_87410		0xd001
-
-#define PCI_VENDOR_ID_TSENG		0x100c
-#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
-#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
-#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
-#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
-#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
-
-#define PCI_VENDOR_ID_WEITEK		0x100e
-#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
-#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
-
-#define PCI_VENDOR_ID_DEC		0x1011
-#define PCI_DEVICE_ID_DEC_BRD		0x0001
-#define PCI_DEVICE_ID_DEC_TULIP		0x0002
-#define PCI_DEVICE_ID_DEC_TGA		0x0004
-#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
-#define PCI_DEVICE_ID_DEC_TGA2		0x000D
-#define PCI_DEVICE_ID_DEC_FDDI		0x000F
-#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
-#define PCI_DEVICE_ID_DEC_21142		0x0019
-#define PCI_DEVICE_ID_DEC_21052		0x0021
-#define PCI_DEVICE_ID_DEC_21150		0x0022
-#define PCI_DEVICE_ID_DEC_21152		0x0024
-
-#define PCI_VENDOR_ID_CIRRUS		0x1013
-#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
-#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
-#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
-#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
-#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
-#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
-#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
-#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
-#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
-#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
-#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
-#define PCI_DEVICE_ID_CIRRUS_7542	0x1200
-#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
-#define PCI_DEVICE_ID_CIRRUS_7541	0x1204
-
-#define PCI_VENDOR_ID_IBM		0x1014
-#define PCI_DEVICE_ID_IBM_FIRE_CORAL	0x000a
-#define PCI_DEVICE_ID_IBM_TR		0x0018
-#define PCI_DEVICE_ID_IBM_82G2675	0x001d
-#define PCI_DEVICE_ID_IBM_MCA		0x0020
-#define PCI_DEVICE_ID_IBM_82351		0x0022
-#define PCI_DEVICE_ID_IBM_SERVERAID	0x002e
-#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
-#define PCI_DEVICE_ID_IBM_MPIC		0x0046
-#define PCI_DEVICE_ID_IBM_3780IDSP	0x007d
-#define PCI_DEVICE_ID_IBM_MPIC_2	0xffff
-
-#define PCI_VENDOR_ID_WD		0x101c
-#define PCI_DEVICE_ID_WD_7197		0x3296
-
-#define PCI_VENDOR_ID_AMD		0x1022
-#define PCI_DEVICE_ID_AMD_LANCE		0x2000
-#define PCI_DEVICE_ID_AMD_SCSI		0x2020
-
-#define PCI_VENDOR_ID_TRIDENT		0x1023
-#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
-#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
-#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
-#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
-#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
-
-#define PCI_VENDOR_ID_AI		0x1025
-#define PCI_DEVICE_ID_AI_M1435		0x1435
-
-#define PCI_VENDOR_ID_MATROX		0x102B
-#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
-#define PCI_DEVICE_ID_MATROX_MIL	0x0519
-#define PCI_DEVICE_ID_MATROX_MYS	0x051A
-#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
-#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
-#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
-
-#define PCI_VENDOR_ID_CT		0x102c
-#define PCI_DEVICE_ID_CT_65545		0x00d8
-#define PCI_DEVICE_ID_CT_65548		0x00dc
-#define PCI_DEVICE_ID_CT_65550		0x00e0
-#define PCI_DEVICE_ID_CT_65554		0x00e4
-#define PCI_DEVICE_ID_CT_65555		0x00e5
-
-#define PCI_VENDOR_ID_MIRO		0x1031
-#define PCI_DEVICE_ID_MIRO_36050	0x5601
-
-#define PCI_VENDOR_ID_NEC		0x1033
-#define PCI_DEVICE_ID_NEC_PCX2		0x0046
-
-#define PCI_VENDOR_ID_FD		0x1036
-#define PCI_DEVICE_ID_FD_36C70		0x0000
-
-#define PCI_VENDOR_ID_SI		0x1039
-#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
-#define PCI_DEVICE_ID_SI_6202		0x0002
-#define PCI_DEVICE_ID_SI_503		0x0008
-#define PCI_DEVICE_ID_SI_ACPI		0x0009
-#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
-#define PCI_DEVICE_ID_SI_6205		0x0205
-#define PCI_DEVICE_ID_SI_501		0x0406
-#define PCI_DEVICE_ID_SI_496		0x0496
-#define PCI_DEVICE_ID_SI_601		0x0601
-#define PCI_DEVICE_ID_SI_5107		0x5107
-#define PCI_DEVICE_ID_SI_5511		0x5511
-#define PCI_DEVICE_ID_SI_5513		0x5513
-#define PCI_DEVICE_ID_SI_5571		0x5571
-#define PCI_DEVICE_ID_SI_5591		0x5591
-#define PCI_DEVICE_ID_SI_5597		0x5597
-#define PCI_DEVICE_ID_SI_7001		0x7001
-
-#define PCI_VENDOR_ID_HP		0x103c
-#define PCI_DEVICE_ID_HP_J2585A		0x1030
-#define PCI_DEVICE_ID_HP_J2585B		0x1031
-
-#define PCI_VENDOR_ID_PCTECH		0x1042
-#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
-#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_0	0x3000
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_1	0x3010
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
-
-#define PCI_VENDOR_ID_DPT               0x1044
-#define PCI_DEVICE_ID_DPT               0xa400
-
-#define PCI_VENDOR_ID_OPTI		0x1045
-#define PCI_DEVICE_ID_OPTI_92C178	0xc178
-#define PCI_DEVICE_ID_OPTI_82C557	0xc557
-#define PCI_DEVICE_ID_OPTI_82C558	0xc558
-#define PCI_DEVICE_ID_OPTI_82C621	0xc621
-#define PCI_DEVICE_ID_OPTI_82C700	0xc700
-#define PCI_DEVICE_ID_OPTI_82C701	0xc701
-#define PCI_DEVICE_ID_OPTI_82C814	0xc814
-#define PCI_DEVICE_ID_OPTI_82C822	0xc822
-#define PCI_DEVICE_ID_OPTI_82C825	0xd568
-
-#define PCI_VENDOR_ID_SGS		0x104a
-#define PCI_DEVICE_ID_SGS_2000		0x0008
-#define PCI_DEVICE_ID_SGS_1764		0x0009
-
-#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
-#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
-
-#define PCI_VENDOR_ID_TI		0x104c
-#define PCI_DEVICE_ID_TI_TVP4010	0x3d04
-#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
-#define PCI_DEVICE_ID_TI_PCI1130	0xac12
-#define PCI_DEVICE_ID_TI_PCI1031	0xac13
-#define PCI_DEVICE_ID_TI_PCI1131	0xac15
-#define PCI_DEVICE_ID_TI_PCI1250	0xac16
-#define PCI_DEVICE_ID_TI_PCI1220	0xac17
-
-#define PCI_VENDOR_ID_OAK		0x104e
-#define PCI_DEVICE_ID_OAK_OTI107	0x0107
+#define PCIR_VENDOR_COMPAQ		0x0e11
+#define PCIR_DEVICE_COMPAQ_1280	0x3033
+#define PCIR_DEVICE_COMPAQ_TRIFLEX	0x4000
+#define PCIR_DEVICE_COMPAQ_SMART2P	0xae10
+#define PCIR_DEVICE_COMPAQ_NETEL100	0xae32
+#define PCIR_DEVICE_COMPAQ_NETEL10	0xae34
+#define PCIR_DEVICE_COMPAQ_NETFLEX3I	0xae35
+#define PCIR_DEVICE_COMPAQ_NETEL100D	0xae40
+#define PCIR_DEVICE_COMPAQ_NETEL100PI	0xae43
+#define PCIR_DEVICE_COMPAQ_NETEL100I	0xb011
+#define PCIR_DEVICE_COMPAQ_THUNDER	0xf130
+#define PCIR_DEVICE_COMPAQ_NETFLEX3B	0xf150
+
+#define PCIR_VENDOR_NCR		0x1000
+#define PCIR_DEVICE_NCR_53C810	0x0001
+#define PCIR_DEVICE_NCR_53C820	0x0002
+#define PCIR_DEVICE_NCR_53C825	0x0003
+#define PCIR_DEVICE_NCR_53C815	0x0004
+#define PCIR_DEVICE_NCR_53C860	0x0006
+#define PCIR_DEVICE_NCR_53C896	0x000b
+#define PCIR_DEVICE_NCR_53C895	0x000c
+#define PCIR_DEVICE_NCR_53C885	0x000d
+#define PCIR_DEVICE_NCR_53C875	0x000f
+#define PCIR_DEVICE_NCR_53C875J	0x008f
+
+#define PCIR_VENDOR_ATI		0x1002
+#define PCIR_DEVICE_ATI_68800		0x4158
+#define PCIR_DEVICE_ATI_215CT222	0x4354
+#define PCIR_DEVICE_ATI_210888CX	0x4358
+#define PCIR_DEVICE_ATI_215GB		0x4742
+#define PCIR_DEVICE_ATI_215GD		0x4744
+#define PCIR_DEVICE_ATI_215GI		0x4749
+#define PCIR_DEVICE_ATI_215GP		0x4750
+#define PCIR_DEVICE_ATI_215GQ		0x4751
+#define PCIR_DEVICE_ATI_215GT		0x4754
+#define PCIR_DEVICE_ATI_215GTB	0x4755
+#define PCIR_DEVICE_ATI_210888GX	0x4758
+#define PCIR_DEVICE_ATI_215LG		0x4c47
+#define PCIR_DEVICE_ATI_264LT		0x4c54
+#define PCIR_DEVICE_ATI_264VT		0x5654
+
+#define PCIR_VENDOR_VLSI		0x1004
+#define PCIR_DEVICE_VLSI_82C592	0x0005
+#define PCIR_DEVICE_VLSI_82C593	0x0006
+#define PCIR_DEVICE_VLSI_82C594	0x0007
+#define PCIR_DEVICE_VLSI_82C597	0x0009
+#define PCIR_DEVICE_VLSI_82C541	0x000c
+#define PCIR_DEVICE_VLSI_82C543	0x000d
+#define PCIR_DEVICE_VLSI_82C532	0x0101
+#define PCIR_DEVICE_VLSI_82C534	0x0102
+#define PCIR_DEVICE_VLSI_82C535	0x0104
+#define PCIR_DEVICE_VLSI_82C147	0x0105
+#define PCIR_DEVICE_VLSI_VAS96011	0x0702
+
+#define PCIR_VENDOR_ADL		0x1005
+#define PCIR_DEVICE_ADL_2301		0x2301
+
+#define PCIR_VENDOR_NS		0x100b
+#define PCIR_DEVICE_NS_87415		0x0002
+#define PCIR_DEVICE_NS_87410		0xd001
+
+#define PCIR_VENDOR_TSENG		0x100c
+#define PCIR_DEVICE_TSENG_W32P_2	0x3202
+#define PCIR_DEVICE_TSENG_W32P_b	0x3205
+#define PCIR_DEVICE_TSENG_W32P_c	0x3206
+#define PCIR_DEVICE_TSENG_W32P_d	0x3207
+#define PCIR_DEVICE_TSENG_ET6000	0x3208
+
+#define PCIR_VENDOR_WEITEK		0x100e
+#define PCIR_DEVICE_WEITEK_P9000	0x9001
+#define PCIR_DEVICE_WEITEK_P9100	0x9100
+
+#define PCIR_VENDOR_DEC		0x1011
+#define PCIR_DEVICE_DEC_BRD		0x0001
+#define PCIR_DEVICE_DEC_TULIP		0x0002
+#define PCIR_DEVICE_DEC_TGA		0x0004
+#define PCIR_DEVICE_DEC_TULIP_FAST	0x0009
+#define PCIR_DEVICE_DEC_TGA2		0x000D
+#define PCIR_DEVICE_DEC_FDDI		0x000F
+#define PCIR_DEVICE_DEC_TULIP_PLUS	0x0014
+#define PCIR_DEVICE_DEC_21142		0x0019
+#define PCIR_DEVICE_DEC_21052		0x0021
+#define PCIR_DEVICE_DEC_21150		0x0022
+#define PCIR_DEVICE_DEC_21152		0x0024
+
+#define PCIR_VENDOR_CIRRUS		0x1013
+#define PCIR_DEVICE_CIRRUS_7548	0x0038
+#define PCIR_DEVICE_CIRRUS_5430	0x00a0
+#define PCIR_DEVICE_CIRRUS_5434_4	0x00a4
+#define PCIR_DEVICE_CIRRUS_5434_8	0x00a8
+#define PCIR_DEVICE_CIRRUS_5436	0x00ac
+#define PCIR_DEVICE_CIRRUS_5446	0x00b8
+#define PCIR_DEVICE_CIRRUS_5480	0x00bc
+#define PCIR_DEVICE_CIRRUS_5464	0x00d4
+#define PCIR_DEVICE_CIRRUS_5465	0x00d6
+#define PCIR_DEVICE_CIRRUS_6729	0x1100
+#define PCIR_DEVICE_CIRRUS_6832	0x1110
+#define PCIR_DEVICE_CIRRUS_7542	0x1200
+#define PCIR_DEVICE_CIRRUS_7543	0x1202
+#define PCIR_DEVICE_CIRRUS_7541	0x1204
+
+#define PCIR_VENDOR_IBM		0x1014
+#define PCIR_DEVICE_IBM_FIRE_CORAL	0x000a
+#define PCIR_DEVICE_IBM_TR		0x0018
+#define PCIR_DEVICE_IBM_82G2675	0x001d
+#define PCIR_DEVICE_IBM_MCA		0x0020
+#define PCIR_DEVICE_IBM_82351		0x0022
+#define PCIR_DEVICE_IBM_SERVERAID	0x002e
+#define PCIR_DEVICE_IBM_TR_WAKE	0x003e
+#define PCIR_DEVICE_IBM_MPIC		0x0046
+#define PCIR_DEVICE_IBM_3780IDSP	0x007d
+#define PCIR_DEVICE_IBM_MPIC_2	0xffff
+
+#define PCIR_VENDOR_WD		0x101c
+#define PCIR_DEVICE_WD_7197		0x3296
+
+#define PCIR_VENDOR_AMD		0x1022
+#define PCIR_DEVICE_AMD_LANCE		0x2000
+#define PCIR_DEVICE_AMD_SCSI		0x2020
+
+#define PCIR_VENDOR_TRIDENT		0x1023
+#define PCIR_DEVICE_TRIDENT_9397	0x9397
+#define PCIR_DEVICE_TRIDENT_9420	0x9420
+#define PCIR_DEVICE_TRIDENT_9440	0x9440
+#define PCIR_DEVICE_TRIDENT_9660	0x9660
+#define PCIR_DEVICE_TRIDENT_9750	0x9750
+
+#define PCIR_VENDOR_AI		0x1025
+#define PCIR_DEVICE_AI_M1435		0x1435
+
+#define PCIR_VENDOR_MATROX		0x102B
+#define PCIR_DEVICE_MATROX_MGA_2	0x0518
+#define PCIR_DEVICE_MATROX_MIL	0x0519
+#define PCIR_DEVICE_MATROX_MYS	0x051A
+#define PCIR_DEVICE_MATROX_MIL_2	0x051b
+#define PCIR_DEVICE_MATROX_MIL_2_AGP	0x051f
+#define PCIR_DEVICE_MATROX_MGA_IMP	0x0d10
+
+#define PCIR_VENDOR_CT		0x102c
+#define PCIR_DEVICE_CT_65545		0x00d8
+#define PCIR_DEVICE_CT_65548		0x00dc
+#define PCIR_DEVICE_CT_65550		0x00e0
+#define PCIR_DEVICE_CT_65554		0x00e4
+#define PCIR_DEVICE_CT_65555		0x00e5
+
+#define PCIR_VENDOR_MIRO		0x1031
+#define PCIR_DEVICE_MIRO_36050	0x5601
+
+#define PCIR_VENDOR_NEC		0x1033
+#define PCIR_DEVICE_NEC_PCX2		0x0046
+
+#define PCIR_VENDOR_FD		0x1036
+#define PCIR_DEVICE_FD_36C70		0x0000
+
+#define PCIR_VENDOR_SI		0x1039
+#define PCIR_DEVICE_SI_5591_AGP	0x0001
+#define PCIR_DEVICE_SI_6202		0x0002
+#define PCIR_DEVICE_SI_503		0x0008
+#define PCIR_DEVICE_SI_ACPI		0x0009
+#define PCIR_DEVICE_SI_5597_VGA	0x0200
+#define PCIR_DEVICE_SI_6205		0x0205
+#define PCIR_DEVICE_SI_501		0x0406
+#define PCIR_DEVICE_SI_496		0x0496
+#define PCIR_DEVICE_SI_601		0x0601
+#define PCIR_DEVICE_SI_5107		0x5107
+#define PCIR_DEVICE_SI_5511		0x5511
+#define PCIR_DEVICE_SI_5513		0x5513
+#define PCIR_DEVICE_SI_5571		0x5571
+#define PCIR_DEVICE_SI_5591		0x5591
+#define PCIR_DEVICE_SI_5597		0x5597
+#define PCIR_DEVICE_SI_7001		0x7001
+
+#define PCIR_VENDOR_HP		0x103c
+#define PCIR_DEVICE_HP_J2585A		0x1030
+#define PCIR_DEVICE_HP_J2585B		0x1031
+
+#define PCIR_VENDOR_PCTECH		0x1042
+#define PCIR_DEVICE_PCTECH_RZ1000	0x1000
+#define PCIR_DEVICE_PCTECH_RZ1001	0x1001
+#define PCIR_DEVICE_PCTECH_SAMURAI_0	0x3000
+#define PCIR_DEVICE_PCTECH_SAMURAI_1	0x3010
+#define PCIR_DEVICE_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCIR_VENDOR_DPT               0x1044
+#define PCIR_DEVICE_DPT               0xa400
+
+#define PCIR_VENDOR_OPTI		0x1045
+#define PCIR_DEVICE_OPTI_92C178	0xc178
+#define PCIR_DEVICE_OPTI_82C557	0xc557
+#define PCIR_DEVICE_OPTI_82C558	0xc558
+#define PCIR_DEVICE_OPTI_82C621	0xc621
+#define PCIR_DEVICE_OPTI_82C700	0xc700
+#define PCIR_DEVICE_OPTI_82C701	0xc701
+#define PCIR_DEVICE_OPTI_82C814	0xc814
+#define PCIR_DEVICE_OPTI_82C822	0xc822
+#define PCIR_DEVICE_OPTI_82C825	0xd568
+
+#define PCIR_VENDOR_SGS		0x104a
+#define PCIR_DEVICE_SGS_2000		0x0008
+#define PCIR_DEVICE_SGS_1764		0x0009
+
+#define PCIR_VENDOR_BUSLOGIC		      0x104B
+#define PCIR_DEVICE_BUSLOGIC_MULTIMASTER_NC 0x0140
+#define PCIR_DEVICE_BUSLOGIC_MULTIMASTER    0x1040
+#define PCIR_DEVICE_BUSLOGIC_FLASHPOINT     0x8130
+
+#define PCIR_VENDOR_TI		0x104c
+#define PCIR_DEVICE_TI_TVP4010	0x3d04
+#define PCIR_DEVICE_TI_TVP4020	0x3d07
+#define PCIR_DEVICE_TI_PCI1130	0xac12
+#define PCIR_DEVICE_TI_PCI1031	0xac13
+#define PCIR_DEVICE_TI_PCI1131	0xac15
+#define PCIR_DEVICE_TI_PCI1250	0xac16
+#define PCIR_DEVICE_TI_PCI1220	0xac17
+
+#define PCIR_VENDOR_OAK		0x104e
+#define PCIR_DEVICE_OAK_OTI107	0x0107
 
 /* Winbond have two vendor IDs! See 0x10ad as well */
-#define PCI_VENDOR_ID_WINBOND2		0x1050
-#define PCI_DEVICE_ID_WINBOND2_89C940	0x0940
-
-#define PCI_VENDOR_ID_MOTOROLA		0x1057
-#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
-#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
-#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
-
-#define PCI_VENDOR_ID_PROMISE		0x105a
-#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
-#define PCI_DEVICE_ID_PROMISE_5300	0x5300
-
-#define PCI_VENDOR_ID_N9		0x105d
-#define PCI_DEVICE_ID_N9_I128		0x2309
-#define PCI_DEVICE_ID_N9_I128_2		0x2339
-#define PCI_DEVICE_ID_N9_I128_T2R	0x493d
-
-#define PCI_VENDOR_ID_UMC		0x1060
-#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
-#define PCI_DEVICE_ID_UMC_UM8891A	0x0891
-#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
-#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
-#define PCI_DEVICE_ID_UMC_UM8881F	0x8881
-#define PCI_DEVICE_ID_UMC_UM8886F	0x8886
-#define PCI_DEVICE_ID_UMC_UM9017F	0x9017
-#define PCI_DEVICE_ID_UMC_UM8886N	0xe886
-#define PCI_DEVICE_ID_UMC_UM8891N	0xe891
-
-#define PCI_VENDOR_ID_X			0x1061
-#define PCI_DEVICE_ID_X_AGX016		0x0001
-
-#define PCI_VENDOR_ID_PICOP		0x1066
-#define PCI_DEVICE_ID_PICOP_PT86C52X	0x0001
-#define PCI_DEVICE_ID_PICOP_PT80C524	0x8002
-
-#define PCI_VENDOR_ID_APPLE		0x106b
-#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
-#define PCI_DEVICE_ID_APPLE_GC		0x0002
-#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
-
-#define PCI_VENDOR_ID_NEXGEN		0x1074
-#define PCI_DEVICE_ID_NEXGEN_82C501	0x4e78
-
-#define PCI_VENDOR_ID_QLOGIC		0x1077
-#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
-#define PCI_DEVICE_ID_QLOGIC_ISP1022	0x1022
-
-#define PCI_VENDOR_ID_CYRIX		0x1078
-#define PCI_DEVICE_ID_CYRIX_5510	0x0000
-#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
-#define PCI_DEVICE_ID_CYRIX_5520	0x0002
-#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
-#define PCI_DEVICE_ID_CYRIX_5530_SMI	0x0101
-#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
-#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
-#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
-
-#define PCI_VENDOR_ID_LEADTEK		0x107d
-#define PCI_DEVICE_ID_LEADTEK_805	0x0000
-
-#define PCI_VENDOR_ID_CONTAQ		0x1080
-#define PCI_DEVICE_ID_CONTAQ_82C599	0x0600
-#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
-
-#define PCI_VENDOR_ID_FOREX		0x1083
-
-#define PCI_VENDOR_ID_OLICOM		0x108d
-#define PCI_DEVICE_ID_OLICOM_OC3136	0x0001
-#define PCI_DEVICE_ID_OLICOM_OC2315	0x0011
-#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
-#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
-#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
-#define PCI_DEVICE_ID_OLICOM_OC6151	0x0021
-
-#define PCI_VENDOR_ID_SUN		0x108e
-#define PCI_DEVICE_ID_SUN_EBUS		0x1000
-#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
-#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
-#define PCI_DEVICE_ID_SUN_PBM		0x8000
-#define PCI_DEVICE_ID_SUN_SABRE		0xa000
-
-#define PCI_VENDOR_ID_CMD		0x1095
-#define PCI_DEVICE_ID_CMD_640		0x0640
-#define PCI_DEVICE_ID_CMD_643		0x0643
-#define PCI_DEVICE_ID_CMD_646		0x0646
-#define PCI_DEVICE_ID_CMD_647		0x0647
-#define PCI_DEVICE_ID_CMD_670		0x0670
-
-#define PCI_VENDOR_ID_VISION		0x1098
-#define PCI_DEVICE_ID_VISION_QD8500	0x0001
-#define PCI_DEVICE_ID_VISION_QD8580	0x0002
-
-#define PCI_VENDOR_ID_BROOKTREE		0x109e
-#define PCI_DEVICE_ID_BROOKTREE_848	0x0350
-#define PCI_DEVICE_ID_BROOKTREE_849A	0x0351
-#define PCI_DEVICE_ID_BROOKTREE_8474	0x8474
-
-#define PCI_VENDOR_ID_SIERRA		0x10a8
-#define PCI_DEVICE_ID_SIERRA_STB	0x0000
-
-#define PCI_VENDOR_ID_ACC		0x10aa
-#define PCI_DEVICE_ID_ACC_2056		0x0000
-
-#define PCI_VENDOR_ID_WINBOND		0x10ad
-#define PCI_DEVICE_ID_WINBOND_83769	0x0001
-#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
-#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
-
-#define PCI_VENDOR_ID_DATABOOK		0x10b3
-#define PCI_DEVICE_ID_DATABOOK_87144	0xb106
-
-#define PCI_VENDOR_ID_PLX		0x10b5
-#define PCI_DEVICE_ID_PLX_9050		0x9050
-#define PCI_DEVICE_ID_PLX_9060		0x9060
-#define PCI_DEVICE_ID_PLX_9060ES	0x906E
-#define PCI_DEVICE_ID_PLX_9060SD	0x906D
-#define PCI_DEVICE_ID_PLX_9080		0x9080
-
-#define PCI_VENDOR_ID_MADGE		0x10b6
-#define PCI_DEVICE_ID_MADGE_MK2		0x0002
-#define PCI_DEVICE_ID_MADGE_C155S	0x1001
-
-#define PCI_VENDOR_ID_3COM		0x10b7
-#define PCI_DEVICE_ID_3COM_3C339	0x3390
-#define PCI_DEVICE_ID_3COM_3C590	0x5900
-#define PCI_DEVICE_ID_3COM_3C595TX	0x5950
-#define PCI_DEVICE_ID_3COM_3C595T4	0x5951
-#define PCI_DEVICE_ID_3COM_3C595MII	0x5952
-#define PCI_DEVICE_ID_3COM_3C900TPO	0x9000
-#define PCI_DEVICE_ID_3COM_3C900COMBO	0x9001
-#define PCI_DEVICE_ID_3COM_3C905TX	0x9050
-#define PCI_DEVICE_ID_3COM_3C905T4	0x9051
-#define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
-
-#define PCI_VENDOR_ID_SMC		0x10b8
-#define PCI_DEVICE_ID_SMC_EPIC100	0x0005
-
-#define PCI_VENDOR_ID_AL		0x10b9
-#define PCI_DEVICE_ID_AL_M1445		0x1445
-#define PCI_DEVICE_ID_AL_M1449		0x1449
-#define PCI_DEVICE_ID_AL_M1451		0x1451
-#define PCI_DEVICE_ID_AL_M1461		0x1461
-#define PCI_DEVICE_ID_AL_M1489		0x1489
-#define PCI_DEVICE_ID_AL_M1511		0x1511
-#define PCI_DEVICE_ID_AL_M1513		0x1513
-#define PCI_DEVICE_ID_AL_M1521		0x1521
-#define PCI_DEVICE_ID_AL_M1523		0x1523
-#define PCI_DEVICE_ID_AL_M1531		0x1531
-#define PCI_DEVICE_ID_AL_M1533		0x1533
-#define PCI_DEVICE_ID_AL_M3307		0x3307
-#define PCI_DEVICE_ID_AL_M4803		0x5215
-#define PCI_DEVICE_ID_AL_M5219		0x5219
-#define PCI_DEVICE_ID_AL_M5229		0x5229
-#define PCI_DEVICE_ID_AL_M5237		0x5237
-#define PCI_DEVICE_ID_AL_M7101		0x7101
-
-#define PCI_VENDOR_ID_MITSUBISHI	0x10ba
-
-#define PCI_VENDOR_ID_SURECOM		0x10bd
-#define PCI_DEVICE_ID_SURECOM_NE34	0x0e34
-
-#define PCI_VENDOR_ID_NEOMAGIC          0x10c8
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
-
-#define PCI_VENDOR_ID_ASP		0x10cd
-#define PCI_DEVICE_ID_ASP_ABP940	0x1200
-#define PCI_DEVICE_ID_ASP_ABP940U	0x1300
-#define PCI_DEVICE_ID_ASP_ABP940UW	0x2300
-
-#define PCI_VENDOR_ID_MACRONIX		0x10d9
-#define PCI_DEVICE_ID_MACRONIX_MX98713	0x0512
-#define PCI_DEVICE_ID_MACRONIX_MX987x5	0x0531
-
-#define PCI_VENDOR_ID_CERN		0x10dc
-#define PCI_DEVICE_ID_CERN_SPSB_PMC	0x0001
-#define PCI_DEVICE_ID_CERN_SPSB_PCI	0x0002
-#define PCI_DEVICE_ID_CERN_HIPPI_DST	0x0021
-#define PCI_DEVICE_ID_CERN_HIPPI_SRC	0x0022
-
-#define PCI_VENDOR_ID_NVIDIA		0x10de
-
-#define PCI_VENDOR_ID_IMS		0x10e0
-#define PCI_DEVICE_ID_IMS_8849		0x8849
-
-#define PCI_VENDOR_ID_TEKRAM2		0x10e1
-#define PCI_DEVICE_ID_TEKRAM2_690c	0x690c
-
-#define PCI_VENDOR_ID_TUNDRA		0x10e3
-#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
-
-#define PCI_VENDOR_ID_AMCC		0x10e8
-#define PCI_DEVICE_ID_AMCC_MYRINET	0x8043
-#define PCI_DEVICE_ID_AMCC_PARASTATION	0x8062
-#define PCI_DEVICE_ID_AMCC_S5933	0x807d
-#define PCI_DEVICE_ID_AMCC_S5933_HEPC3	0x809c
-
-#define PCI_VENDOR_ID_INTERG		0x10ea
-#define PCI_DEVICE_ID_INTERG_1680	0x1680
-#define PCI_DEVICE_ID_INTERG_1682	0x1682
-
-#define PCI_VENDOR_ID_REALTEK		0x10ec
-#define PCI_DEVICE_ID_REALTEK_8029	0x8029
-#define PCI_DEVICE_ID_REALTEK_8129	0x8129
-#define PCI_DEVICE_ID_REALTEK_8139	0x8139
-
-#define PCI_VENDOR_ID_TRUEVISION	0x10fa
-#define PCI_DEVICE_ID_TRUEVISION_T1000	0x000c
-
-#define PCI_VENDOR_ID_INIT		0x1101
-#define PCI_DEVICE_ID_INIT_320P		0x9100
-#define PCI_DEVICE_ID_INIT_360P		0x9500
-
-#define PCI_VENDOR_ID_TTI		0x1103
-#define PCI_DEVICE_ID_TTI_HPT343	0x0003
-
-#define PCI_VENDOR_ID_VIA		0x1106
-#define PCI_DEVICE_ID_VIA_82C505	0x0505
-#define PCI_DEVICE_ID_VIA_82C561	0x0561
-#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
-#define PCI_DEVICE_ID_VIA_82C576	0x0576
-#define PCI_DEVICE_ID_VIA_82C585	0x0585
-#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
-#define PCI_DEVICE_ID_VIA_82C595	0x0595
-#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
-#define PCI_DEVICE_ID_VIA_82C926	0x0926
-#define PCI_DEVICE_ID_VIA_82C416	0x1571
-#define PCI_DEVICE_ID_VIA_82C595_97	0x1595
-#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
-#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
-#define PCI_DEVICE_ID_VIA_86C100A	0x6100
-#define PCI_DEVICE_ID_VIA_82C597_1	0x8597
-
-#define PCI_VENDOR_ID_VORTEX		0x1119
-#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
-#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
-#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
-#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
-#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
-#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
-#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
-#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
-#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
-#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
-#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
-#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
-#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
-#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1	0x0110
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1	0x0111
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP1	0x0112
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP1	0x0113
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1	0x0114
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1	0x0115
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2	0x0120
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2	0x0121
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP2	0x0122
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP2	0x0123
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2	0x0124
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2	0x0125
-
-#define PCI_VENDOR_ID_EF		0x111a
-#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
-#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
-
-#define PCI_VENDOR_ID_FORE		0x1127
-#define PCI_DEVICE_ID_FORE_PCA200PC	0x0210
-#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
-
-#define PCI_VENDOR_ID_IMAGINGTECH	0x112f
-#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI	0x0000
-
-#define PCI_VENDOR_ID_PHILIPS		0x1131
-#define PCI_DEVICE_ID_PHILIPS_SAA7145	0x7145
-#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
-
-#define PCI_VENDOR_ID_CYCLONE		0x113c
-#define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
-
-#define PCI_VENDOR_ID_ALLIANCE		0x1142
-#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO	0x3210
-#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO	0x6422
-#define PCI_DEVICE_ID_ALLIANCE_AT24	0x6424
-#define PCI_DEVICE_ID_ALLIANCE_AT3D	0x643d
-
-#define PCI_VENDOR_ID_SK		0x1148
-#define PCI_DEVICE_ID_SK_FP		0x4000
-#define PCI_DEVICE_ID_SK_TR		0x4200
-#define PCI_DEVICE_ID_SK_GE		0x4300
-
-#define PCI_VENDOR_ID_VMIC		0x114a
-#define PCI_DEVICE_ID_VMIC_VME		0x7587
-
-#define PCI_VENDOR_ID_DIGI		0x114f
-#define PCI_DEVICE_ID_DIGI_EPC		0x0002
-#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH	0x0003
-#define PCI_DEVICE_ID_DIGI_XEM		0x0004
-#define PCI_DEVICE_ID_DIGI_XR		0x0005
-#define PCI_DEVICE_ID_DIGI_CX		0x0006
-#define PCI_DEVICE_ID_DIGI_XRJ		0x0009
-#define PCI_DEVICE_ID_DIGI_EPCJ		0x000a
-#define PCI_DEVICE_ID_DIGI_XR_920	0x0027
-
-#define PCI_VENDOR_ID_MUTECH		0x1159
-#define PCI_DEVICE_ID_MUTECH_MV1000	0x0001
-
-#define PCI_VENDOR_ID_RENDITION		0x1163
-#define PCI_DEVICE_ID_RENDITION_VERITE	0x0001
-#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
-
-#define PCI_VENDOR_ID_TOSHIBA		0x1179
-#define PCI_DEVICE_ID_TOSHIBA_601	0x0601
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
-
-#define PCI_VENDOR_ID_RICOH		0x1180
-#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
-#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
-#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
-#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
-
-#define PCI_VENDOR_ID_ARTOP		0x1191
-#define PCI_DEVICE_ID_ARTOP_ATP8400	0x0004
-#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
-
-#define PCI_VENDOR_ID_ZEITNET		0x1193
-#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
-#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
-
-#define PCI_VENDOR_ID_OMEGA		0x119b
-#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
-
-#define PCI_VENDOR_ID_LITEON		0x11ad
-#define PCI_DEVICE_ID_LITEON_LNE100TX	0x0002
-
-#define PCI_VENDOR_ID_NP		0x11bc
-#define PCI_DEVICE_ID_NP_PCI_FDDI	0x0001
-
-#define PCI_VENDOR_ID_ATT		0x11c1
-#define PCI_DEVICE_ID_ATT_L56XMF	0x0440
-
-#define PCI_VENDOR_ID_SPECIALIX		0x11cb
-#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
-#define PCI_DEVICE_ID_SPECIALIX_XIO	0x4000
-#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
-
-#define PCI_VENDOR_ID_AURAVISION	0x11d1
-#define PCI_DEVICE_ID_AURAVISION_VXP524	0x01f7
-
-#define PCI_VENDOR_ID_IKON		0x11d5
-#define PCI_DEVICE_ID_IKON_10115	0x0115
-#define PCI_DEVICE_ID_IKON_10117	0x0117
-
-#define PCI_VENDOR_ID_ZORAN		0x11de
-#define PCI_DEVICE_ID_ZORAN_36057	0x6057
-#define PCI_DEVICE_ID_ZORAN_36120	0x6120
-
-#define PCI_VENDOR_ID_KINETIC		0x11f4
-#define PCI_DEVICE_ID_KINETIC_2915	0x2915
-
-#define PCI_VENDOR_ID_COMPEX		0x11f6
-#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
-#define PCI_DEVICE_ID_COMPEX_RL2000	0x1401
-
-#define PCI_VENDOR_ID_RP               0x11fe
-#define PCI_DEVICE_ID_RP32INTF         0x0001
-#define PCI_DEVICE_ID_RP8INTF          0x0002
-#define PCI_DEVICE_ID_RP16INTF         0x0003
-#define PCI_DEVICE_ID_RP4QUAD	       0x0004
-#define PCI_DEVICE_ID_RP8OCTA          0x0005
-#define PCI_DEVICE_ID_RP8J	       0x0006
-#define PCI_DEVICE_ID_RPP4	       0x000A
-#define PCI_DEVICE_ID_RPP8	       0x000B
-#define PCI_DEVICE_ID_RP8M	       0x000C
-
-#define PCI_VENDOR_ID_CYCLADES		0x120e
-#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
-#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
-#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
-#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
-
-#define PCI_VENDOR_ID_ESSENTIAL		0x120f
-#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
-
-#define PCI_VENDOR_ID_O2		0x1217
-#define PCI_DEVICE_ID_O2_6729		0x6729
-#define PCI_DEVICE_ID_O2_6730		0x673a
-#define PCI_DEVICE_ID_O2_6832		0x6832
-#define PCI_DEVICE_ID_O2_6836		0x6836
-
-#define PCI_VENDOR_ID_3DFX		0x121a
-#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
-#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
-
-#define PCI_VENDOR_ID_SIGMADES		0x1236
-#define PCI_DEVICE_ID_SIGMADES_6425	0x6401
-
-#define PCI_VENDOR_ID_CCUBE		0x123f
-
-#define PCI_VENDOR_ID_DIPIX		0x1246
-
-#define PCI_VENDOR_ID_STALLION		0x124d
-#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
-#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
-#define PCI_DEVICE_ID_STALLION_EIOPCI	0x0003
-
-#define PCI_VENDOR_ID_OPTIBASE		0x1255
-#define PCI_DEVICE_ID_OPTIBASE_FORGE	0x1110
-#define PCI_DEVICE_ID_OPTIBASE_FUSION	0x1210
-#define PCI_DEVICE_ID_OPTIBASE_VPLEX	0x2110
-#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC	0x2120
-#define PCI_DEVICE_ID_OPTIBASE_VQUEST	0x2130
-
-#define PCI_VENDOR_ID_SATSAGEM		0x1267
-#define PCI_DEVICE_ID_SATSAGEM_PCR2101	0x5352
-#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
-
-#define PCI_VENDOR_ID_HUGHES		0x1273
-#define PCI_DEVICE_ID_HUGHES_DIRECPC	0x0002
-
-#define PCI_VENDOR_ID_ENSONIQ		0x1274
-#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI	0x5000
-
-#define PCI_VENDOR_ID_ALTEON		0x12ae
-#define PCI_DEVICE_ID_ALTEON_ACENIC	0x0001
-
-#define PCI_VENDOR_ID_PICTUREL		0x12c5
-#define PCI_DEVICE_ID_PICTUREL_PCIVST	0x0081
-
-#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
-#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
-
-#define PCI_VENDOR_ID_CBOARDS		0x1307
-#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
-
-#define PCI_VENDOR_ID_SYMPHONY		0x1c1c
-#define PCI_DEVICE_ID_SYMPHONY_101	0x0001
-
-#define PCI_VENDOR_ID_TEKRAM		0x1de1
-#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
-
-#define PCI_VENDOR_ID_3DLABS		0x3d3d
-#define PCI_DEVICE_ID_3DLABS_300SX	0x0001
-#define PCI_DEVICE_ID_3DLABS_500TX	0x0002
-#define PCI_DEVICE_ID_3DLABS_DELTA	0x0003
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA	0x0004
-#define PCI_DEVICE_ID_3DLABS_MX		0x0006
-
-#define PCI_VENDOR_ID_AVANCE		0x4005
-#define PCI_DEVICE_ID_AVANCE_ALG2064	0x2064
-#define PCI_DEVICE_ID_AVANCE_2302	0x2302
-
-#define PCI_VENDOR_ID_NETVIN		0x4a14
-#define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
-
-#define PCI_VENDOR_ID_S3		0x5333
-#define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551
-#define PCI_DEVICE_ID_S3_ViRGE		0x5631
-#define PCI_DEVICE_ID_S3_TRIO		0x8811
-#define PCI_DEVICE_ID_S3_AURORA64VP	0x8812
-#define PCI_DEVICE_ID_S3_TRIO64UVP	0x8814
-#define PCI_DEVICE_ID_S3_ViRGE_VX	0x883d
-#define PCI_DEVICE_ID_S3_868		0x8880
-#define PCI_DEVICE_ID_S3_928		0x88b0
-#define PCI_DEVICE_ID_S3_864_1		0x88c0
-#define PCI_DEVICE_ID_S3_864_2		0x88c1
-#define PCI_DEVICE_ID_S3_964_1		0x88d0
-#define PCI_DEVICE_ID_S3_964_2		0x88d1
-#define PCI_DEVICE_ID_S3_968		0x88f0
-#define PCI_DEVICE_ID_S3_TRIO64V2	0x8901
-#define PCI_DEVICE_ID_S3_PLATO_PXG	0x8902
-#define PCI_DEVICE_ID_S3_ViRGE_DXGX	0x8a01
-#define PCI_DEVICE_ID_S3_ViRGE_GX2	0x8a10
-#define PCI_DEVICE_ID_S3_ViRGE_MX	0x8c01
-#define PCI_DEVICE_ID_S3_ViRGE_MXP	0x8c02
-#define PCI_DEVICE_ID_S3_ViRGE_MXPMV	0x8c03
-#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
-
-#define PCI_VENDOR_ID_INTEL		0x8086
-#define PCI_DEVICE_ID_INTEL_82375	0x0482
-#define PCI_DEVICE_ID_INTEL_82424	0x0483
-#define PCI_DEVICE_ID_INTEL_82378	0x0484
-#define PCI_DEVICE_ID_INTEL_82430	0x0486
-#define PCI_DEVICE_ID_INTEL_82434	0x04a3
-#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
-#define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
-#define PCI_DEVICE_ID_INTEL_7116	0x1223
-#define PCI_DEVICE_ID_INTEL_82596	0x1226
-#define PCI_DEVICE_ID_INTEL_82865	0x1227
-#define PCI_DEVICE_ID_INTEL_82557	0x1229
-#define PCI_DEVICE_ID_INTEL_82437	0x122d
-#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
-#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
-#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
-#define PCI_DEVICE_ID_INTEL_82437MX	0x1235
-#define PCI_DEVICE_ID_INTEL_82441	0x1237
-#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
-#define PCI_DEVICE_ID_INTEL_82439	0x1250
-#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
-#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
-#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
-#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
-#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
-#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
-#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
-#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
-#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
-#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
-#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
-#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
-#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
-#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
-#define PCI_DEVICE_ID_INTEL_P6		0x84c4
-#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
-
-#define PCI_VENDOR_ID_KTI		0x8e2e
-#define PCI_DEVICE_ID_KTI_ET32P2	0x3000
-
-#define PCI_VENDOR_ID_ADAPTEC		0x9004
-#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
-#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
-#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
-#define PCI_DEVICE_ID_ADAPTEC_5800	0x5800
-#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
-#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
-#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
-#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
-#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
-#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
-#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
-#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
-#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
-#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
-#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
-#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
-#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
-#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
-#define PCI_DEVICE_ID_ADAPTEC_1030	0x8b78
-
-#define PCI_VENDOR_ID_ADAPTEC2		0x9005
-#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
-#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
-#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
-#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
-
-#define PCI_VENDOR_ID_ATRONICS		0x907f
-#define PCI_DEVICE_ID_ATRONICS_2015	0x2015
-
-#define PCI_VENDOR_ID_HOLTEK		0x9412
-#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
-
-#define PCI_VENDOR_ID_TIGERJET		0xe159
-#define PCI_DEVICE_ID_TIGERJET_300	0x0001
-
-#define PCI_VENDOR_ID_ARK		0xedd8
-#define PCI_DEVICE_ID_ARK_STING		0xa091
-#define PCI_DEVICE_ID_ARK_STINGARK	0xa099
-#define PCI_DEVICE_ID_ARK_2000MT	0xa0a1
+#define PCIR_VENDOR_WINBOND2		0x1050
+#define PCIR_DEVICE_WINBOND2_89C940	0x0940
+
+#define PCIR_VENDOR_MOTOROLA		0x1057
+#define PCIR_DEVICE_MOTOROLA_MPC105	0x0001
+#define PCIR_DEVICE_MOTOROLA_MPC106	0x0002
+#define PCIR_DEVICE_MOTOROLA_RAVEN	0x4801
+
+#define PCIR_VENDOR_PROMISE		0x105a
+#define PCIR_DEVICE_PROMISE_20246	0x4d33
+#define PCIR_DEVICE_PROMISE_5300	0x5300
+
+#define PCIR_VENDOR_N9		0x105d
+#define PCIR_DEVICE_N9_I128		0x2309
+#define PCIR_DEVICE_N9_I128_2		0x2339
+#define PCIR_DEVICE_N9_I128_T2R	0x493d
+
+#define PCIR_VENDOR_UMC		0x1060
+#define PCIR_DEVICE_UMC_UM8673F	0x0101
+#define PCIR_DEVICE_UMC_UM8891A	0x0891
+#define PCIR_DEVICE_UMC_UM8886BF	0x673a
+#define PCIR_DEVICE_UMC_UM8886A	0x886a
+#define PCIR_DEVICE_UMC_UM8881F	0x8881
+#define PCIR_DEVICE_UMC_UM8886F	0x8886
+#define PCIR_DEVICE_UMC_UM9017F	0x9017
+#define PCIR_DEVICE_UMC_UM8886N	0xe886
+#define PCIR_DEVICE_UMC_UM8891N	0xe891
+
+#define PCIR_VENDOR_X			0x1061
+#define PCIR_DEVICE_X_AGX016		0x0001
+
+#define PCIR_VENDOR_PICOP		0x1066
+#define PCIR_DEVICE_PICOP_PT86C52X	0x0001
+#define PCIR_DEVICE_PICOP_PT80C524	0x8002
+
+#define PCIR_VENDOR_APPLE		0x106b
+#define PCIR_DEVICE_APPLE_BANDIT	0x0001
+#define PCIR_DEVICE_APPLE_GC		0x0002
+#define PCIR_DEVICE_APPLE_HYDRA	0x000e
+
+#define PCIR_VENDOR_NEXGEN		0x1074
+#define PCIR_DEVICE_NEXGEN_82C501	0x4e78
+
+#define PCIR_VENDOR_QLOGIC		0x1077
+#define PCIR_DEVICE_QLOGIC_ISP1020	0x1020
+#define PCIR_DEVICE_QLOGIC_ISP1022	0x1022
+
+#define PCIR_VENDOR_CYRIX		0x1078
+#define PCIR_DEVICE_CYRIX_5510	0x0000
+#define PCIR_DEVICE_CYRIX_PCI_MASTER	0x0001
+#define PCIR_DEVICE_CYRIX_5520	0x0002
+#define PCIR_DEVICE_CYRIX_5530_LEGACY	0x0100
+#define PCIR_DEVICE_CYRIX_5530_SMI	0x0101
+#define PCIR_DEVICE_CYRIX_5530_IDE	0x0102
+#define PCIR_DEVICE_CYRIX_5530_AUDIO	0x0103
+#define PCIR_DEVICE_CYRIX_5530_VIDEO	0x0104
+
+#define PCIR_VENDOR_LEADTEK		0x107d
+#define PCIR_DEVICE_LEADTEK_805	0x0000
+
+#define PCIR_VENDOR_CONTAQ		0x1080
+#define PCIR_DEVICE_CONTAQ_82C599	0x0600
+#define PCIR_DEVICE_CONTAQ_82C693	0xc693
+
+#define PCIR_VENDOR_FOREX		0x1083
+
+#define PCIR_VENDOR_OLICOM		0x108d
+#define PCIR_DEVICE_OLICOM_OC3136	0x0001
+#define PCIR_DEVICE_OLICOM_OC2315	0x0011
+#define PCIR_DEVICE_OLICOM_OC2325	0x0012
+#define PCIR_DEVICE_OLICOM_OC2183	0x0013
+#define PCIR_DEVICE_OLICOM_OC2326	0x0014
+#define PCIR_DEVICE_OLICOM_OC6151	0x0021
+
+#define PCIR_VENDOR_SUN		0x108e
+#define PCIR_DEVICE_SUN_EBUS		0x1000
+#define PCIR_DEVICE_SUN_HAPPYMEAL	0x1001
+#define PCIR_DEVICE_SUN_SIMBA		0x5000
+#define PCIR_DEVICE_SUN_PBM		0x8000
+#define PCIR_DEVICE_SUN_SABRE		0xa000
+
+#define PCIR_VENDOR_CMD		0x1095
+#define PCIR_DEVICE_CMD_640		0x0640
+#define PCIR_DEVICE_CMD_643		0x0643
+#define PCIR_DEVICE_CMD_646		0x0646
+#define PCIR_DEVICE_CMD_647		0x0647
+#define PCIR_DEVICE_CMD_670		0x0670
+
+#define PCIR_VENDOR_VISION		0x1098
+#define PCIR_DEVICE_VISION_QD8500	0x0001
+#define PCIR_DEVICE_VISION_QD8580	0x0002
+
+#define PCIR_VENDOR_BROOKTREE		0x109e
+#define PCIR_DEVICE_BROOKTREE_848	0x0350
+#define PCIR_DEVICE_BROOKTREE_849A	0x0351
+#define PCIR_DEVICE_BROOKTREE_8474	0x8474
+
+#define PCIR_VENDOR_SIERRA		0x10a8
+#define PCIR_DEVICE_SIERRA_STB	0x0000
+
+#define PCIR_VENDOR_ACC		0x10aa
+#define PCIR_DEVICE_ACC_2056		0x0000
+
+#define PCIR_VENDOR_WINBOND		0x10ad
+#define PCIR_DEVICE_WINBOND_83769	0x0001
+#define PCIR_DEVICE_WINBOND_82C105	0x0105
+#define PCIR_DEVICE_WINBOND_83C553	0x0565
+
+#define PCIR_VENDOR_DATABOOK		0x10b3
+#define PCIR_DEVICE_DATABOOK_87144	0xb106
+
+#define PCIR_VENDOR_PLX		0x10b5
+#define PCIR_DEVICE_PLX_9050		0x9050
+#define PCIR_DEVICE_PLX_9060		0x9060
+#define PCIR_DEVICE_PLX_9060ES	0x906E
+#define PCIR_DEVICE_PLX_9060SD	0x906D
+#define PCIR_DEVICE_PLX_9080		0x9080
+
+#define PCIR_VENDOR_MADGE		0x10b6
+#define PCIR_DEVICE_MADGE_MK2		0x0002
+#define PCIR_DEVICE_MADGE_C155S	0x1001
+
+#define PCIR_VENDOR_3COM		0x10b7
+#define PCIR_DEVICE_3COM_3C339	0x3390
+#define PCIR_DEVICE_3COM_3C590	0x5900
+#define PCIR_DEVICE_3COM_3C595TX	0x5950
+#define PCIR_DEVICE_3COM_3C595T4	0x5951
+#define PCIR_DEVICE_3COM_3C595MII	0x5952
+#define PCIR_DEVICE_3COM_3C900TPO	0x9000
+#define PCIR_DEVICE_3COM_3C900COMBO	0x9001
+#define PCIR_DEVICE_3COM_3C905TX	0x9050
+#define PCIR_DEVICE_3COM_3C905T4	0x9051
+#define PCIR_DEVICE_3COM_3C905B_TX	0x9055
+
+#define PCIR_VENDOR_SMC		0x10b8
+#define PCIR_DEVICE_SMC_EPIC100	0x0005
+
+#define PCIR_VENDOR_AL		0x10b9
+#define PCIR_DEVICE_AL_M1445		0x1445
+#define PCIR_DEVICE_AL_M1449		0x1449
+#define PCIR_DEVICE_AL_M1451		0x1451
+#define PCIR_DEVICE_AL_M1461		0x1461
+#define PCIR_DEVICE_AL_M1489		0x1489
+#define PCIR_DEVICE_AL_M1511		0x1511
+#define PCIR_DEVICE_AL_M1513		0x1513
+#define PCIR_DEVICE_AL_M1521		0x1521
+#define PCIR_DEVICE_AL_M1523		0x1523
+#define PCIR_DEVICE_AL_M1531		0x1531
+#define PCIR_DEVICE_AL_M1533		0x1533
+#define PCIR_DEVICE_AL_M3307		0x3307
+#define PCIR_DEVICE_AL_M4803		0x5215
+#define PCIR_DEVICE_AL_M5219		0x5219
+#define PCIR_DEVICE_AL_M5229		0x5229
+#define PCIR_DEVICE_AL_M5237		0x5237
+#define PCIR_DEVICE_AL_M7101		0x7101
+
+#define PCIR_VENDOR_MITSUBISHI	0x10ba
+
+#define PCIR_VENDOR_SURECOM		0x10bd
+#define PCIR_DEVICE_SURECOM_NE34	0x0e34
+
+#define PCIR_VENDOR_NEOMAGIC          0x10c8
+#define PCIR_DEVICE_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
+#define PCIR_DEVICE_NEOMAGIC_MAGICGRAPH_128V 0x0002
+#define PCIR_DEVICE_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
+#define PCIR_DEVICE_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
+
+#define PCIR_VENDOR_ASP		0x10cd
+#define PCIR_DEVICE_ASP_ABP940	0x1200
+#define PCIR_DEVICE_ASP_ABP940U	0x1300
+#define PCIR_DEVICE_ASP_ABP940UW	0x2300
+
+#define PCIR_VENDOR_MACRONIX		0x10d9
+#define PCIR_DEVICE_MACRONIX_MX98713	0x0512
+#define PCIR_DEVICE_MACRONIX_MX987x5	0x0531
+
+#define PCIR_VENDOR_CERN		0x10dc
+#define PCIR_DEVICE_CERN_SPSB_PMC	0x0001
+#define PCIR_DEVICE_CERN_SPSB_PCI	0x0002
+#define PCIR_DEVICE_CERN_HIPPI_DST	0x0021
+#define PCIR_DEVICE_CERN_HIPPI_SRC	0x0022
+
+#define PCIR_VENDOR_NVIDIA		0x10de
+
+#define PCIR_VENDOR_IMS		0x10e0
+#define PCIR_DEVICE_IMS_8849		0x8849
+
+#define PCIR_VENDOR_TEKRAM2		0x10e1
+#define PCIR_DEVICE_TEKRAM2_690c	0x690c
+
+#define PCIR_VENDOR_TUNDRA		0x10e3
+#define PCIR_DEVICE_TUNDRA_CA91C042	0x0000
+
+#define PCIR_VENDOR_AMCC		0x10e8
+#define PCIR_DEVICE_AMCC_MYRINET	0x8043
+#define PCIR_DEVICE_AMCC_PARASTATION	0x8062
+#define PCIR_DEVICE_AMCC_S5933	0x807d
+#define PCIR_DEVICE_AMCC_S5933_HEPC3	0x809c
+
+#define PCIR_VENDOR_INTERG		0x10ea
+#define PCIR_DEVICE_INTERG_1680	0x1680
+#define PCIR_DEVICE_INTERG_1682	0x1682
+
+#define PCIR_VENDOR_REALTEK		0x10ec
+#define PCIR_DEVICE_REALTEK_8029	0x8029
+#define PCIR_DEVICE_REALTEK_8129	0x8129
+#define PCIR_DEVICE_REALTEK_8139	0x8139
+
+#define PCIR_VENDOR_TRUEVISION	0x10fa
+#define PCIR_DEVICE_TRUEVISION_T1000	0x000c
+
+#define PCIR_VENDOR_INIT		0x1101
+#define PCIR_DEVICE_INIT_320P		0x9100
+#define PCIR_DEVICE_INIT_360P		0x9500
+
+#define PCIR_VENDOR_TTI		0x1103
+#define PCIR_DEVICE_TTI_HPT343	0x0003
+
+#define PCIR_VENDOR_VIA		0x1106
+#define PCIR_DEVICE_VIA_82C505	0x0505
+#define PCIR_DEVICE_VIA_82C561	0x0561
+#define PCIR_DEVICE_VIA_82C586_1	0x0571
+#define PCIR_DEVICE_VIA_82C576	0x0576
+#define PCIR_DEVICE_VIA_82C585	0x0585
+#define PCIR_DEVICE_VIA_82C586_0	0x0586
+#define PCIR_DEVICE_VIA_82C595	0x0595
+#define PCIR_DEVICE_VIA_82C597_0	0x0597
+#define PCIR_DEVICE_VIA_82C926	0x0926
+#define PCIR_DEVICE_VIA_82C416	0x1571
+#define PCIR_DEVICE_VIA_82C595_97	0x1595
+#define PCIR_DEVICE_VIA_82C586_2	0x3038
+#define PCIR_DEVICE_VIA_82C586_3	0x3040
+#define PCIR_DEVICE_VIA_86C100A	0x6100
+#define PCIR_DEVICE_VIA_82C597_1	0x8597
+
+#define PCIR_VENDOR_VORTEX		0x1119
+#define PCIR_DEVICE_VORTEX_GDT60x0	0x0000
+#define PCIR_DEVICE_VORTEX_GDT6000B	0x0001
+#define PCIR_DEVICE_VORTEX_GDT6x10	0x0002
+#define PCIR_DEVICE_VORTEX_GDT6x20	0x0003
+#define PCIR_DEVICE_VORTEX_GDT6530	0x0004
+#define PCIR_DEVICE_VORTEX_GDT6550	0x0005
+#define PCIR_DEVICE_VORTEX_GDT6x17	0x0006
+#define PCIR_DEVICE_VORTEX_GDT6x27	0x0007
+#define PCIR_DEVICE_VORTEX_GDT6537	0x0008
+#define PCIR_DEVICE_VORTEX_GDT6557	0x0009
+#define PCIR_DEVICE_VORTEX_GDT6x15	0x000a
+#define PCIR_DEVICE_VORTEX_GDT6x25	0x000b
+#define PCIR_DEVICE_VORTEX_GDT6535	0x000c
+#define PCIR_DEVICE_VORTEX_GDT6555	0x000d
+#define PCIR_DEVICE_VORTEX_GDT6x17RP	0x0100
+#define PCIR_DEVICE_VORTEX_GDT6x27RP	0x0101
+#define PCIR_DEVICE_VORTEX_GDT6537RP	0x0102
+#define PCIR_DEVICE_VORTEX_GDT6557RP	0x0103
+#define PCIR_DEVICE_VORTEX_GDT6x11RP	0x0104
+#define PCIR_DEVICE_VORTEX_GDT6x21RP	0x0105
+#define PCIR_DEVICE_VORTEX_GDT6x17RP1	0x0110
+#define PCIR_DEVICE_VORTEX_GDT6x27RP1	0x0111
+#define PCIR_DEVICE_VORTEX_GDT6537RP1	0x0112
+#define PCIR_DEVICE_VORTEX_GDT6557RP1	0x0113
+#define PCIR_DEVICE_VORTEX_GDT6x11RP1	0x0114
+#define PCIR_DEVICE_VORTEX_GDT6x21RP1	0x0115
+#define PCIR_DEVICE_VORTEX_GDT6x17RP2	0x0120
+#define PCIR_DEVICE_VORTEX_GDT6x27RP2	0x0121
+#define PCIR_DEVICE_VORTEX_GDT6537RP2	0x0122
+#define PCIR_DEVICE_VORTEX_GDT6557RP2	0x0123
+#define PCIR_DEVICE_VORTEX_GDT6x11RP2	0x0124
+#define PCIR_DEVICE_VORTEX_GDT6x21RP2	0x0125
+
+#define PCIR_VENDOR_EF		0x111a
+#define PCIR_DEVICE_EF_ATM_FPGA	0x0000
+#define PCIR_DEVICE_EF_ATM_ASIC	0x0002
+
+#define PCIR_VENDOR_FORE		0x1127
+#define PCIR_DEVICE_FORE_PCA200PC	0x0210
+#define PCIR_DEVICE_FORE_PCA200E	0x0300
+
+#define PCIR_VENDOR_IMAGINGTECH	0x112f
+#define PCIR_DEVICE_IMAGINGTECH_ICPCI	0x0000
+
+#define PCIR_VENDOR_PHILIPS		0x1131
+#define PCIR_DEVICE_PHILIPS_SAA7145	0x7145
+#define PCIR_DEVICE_PHILIPS_SAA7146	0x7146
+
+#define PCIR_VENDOR_CYCLONE		0x113c
+#define PCIR_DEVICE_CYCLONE_SDK	0x0001
+
+#define PCIR_VENDOR_ALLIANCE		0x1142
+#define PCIR_DEVICE_ALLIANCE_PROMOTIO	0x3210
+#define PCIR_DEVICE_ALLIANCE_PROVIDEO	0x6422
+#define PCIR_DEVICE_ALLIANCE_AT24	0x6424
+#define PCIR_DEVICE_ALLIANCE_AT3D	0x643d
+
+#define PCIR_VENDOR_SK		0x1148
+#define PCIR_DEVICE_SK_FP		0x4000
+#define PCIR_DEVICE_SK_TR		0x4200
+#define PCIR_DEVICE_SK_GE		0x4300
+
+#define PCIR_VENDOR_VMIC		0x114a
+#define PCIR_DEVICE_VMIC_VME		0x7587
+
+#define PCIR_VENDOR_DIGI		0x114f
+#define PCIR_DEVICE_DIGI_EPC		0x0002
+#define PCIR_DEVICE_DIGI_RIGHTSWITCH	0x0003
+#define PCIR_DEVICE_DIGI_XEM		0x0004
+#define PCIR_DEVICE_DIGI_XR		0x0005
+#define PCIR_DEVICE_DIGI_CX		0x0006
+#define PCIR_DEVICE_DIGI_XRJ		0x0009
+#define PCIR_DEVICE_DIGI_EPCJ		0x000a
+#define PCIR_DEVICE_DIGI_XR_920	0x0027
+
+#define PCIR_VENDOR_MUTECH		0x1159
+#define PCIR_DEVICE_MUTECH_MV1000	0x0001
+
+#define PCIR_VENDOR_RENDITION		0x1163
+#define PCIR_DEVICE_RENDITION_VERITE	0x0001
+#define PCIR_DEVICE_RENDITION_VERITE2100 0x2000
+
+#define PCIR_VENDOR_TOSHIBA		0x1179
+#define PCIR_DEVICE_TOSHIBA_601	0x0601
+#define PCIR_DEVICE_TOSHIBA_TOPIC95	0x060a
+#define PCIR_DEVICE_TOSHIBA_TOPIC97	0x060f
+
+#define PCIR_VENDOR_RICOH		0x1180
+#define PCIR_DEVICE_RICOH_RL5C465	0x0465
+#define PCIR_DEVICE_RICOH_RL5C466	0x0466
+#define PCIR_DEVICE_RICOH_RL5C475	0x0475
+#define PCIR_DEVICE_RICOH_RL5C478	0x0478
+
+#define PCIR_VENDOR_ARTOP		0x1191
+#define PCIR_DEVICE_ARTOP_ATP8400	0x0004
+#define PCIR_DEVICE_ARTOP_ATP850UF	0x0005
+
+#define PCIR_VENDOR_ZEITNET		0x1193
+#define PCIR_DEVICE_ZEITNET_1221	0x0001
+#define PCIR_DEVICE_ZEITNET_1225	0x0002
+
+#define PCIR_VENDOR_OMEGA		0x119b
+#define PCIR_DEVICE_OMEGA_82C092G	0x1221
+
+#define PCIR_VENDOR_LITEON		0x11ad
+#define PCIR_DEVICE_LITEON_LNE100TX	0x0002
+
+#define PCIR_VENDOR_NP		0x11bc
+#define PCIR_DEVICE_NP_PCI_FDDI	0x0001
+
+#define PCIR_VENDOR_ATT		0x11c1
+#define PCIR_DEVICE_ATT_L56XMF	0x0440
+
+#define PCIR_VENDOR_SPECIALIX		0x11cb
+#define PCIR_DEVICE_SPECIALIX_IO8	0x2000
+#define PCIR_DEVICE_SPECIALIX_XIO	0x4000
+#define PCIR_DEVICE_SPECIALIX_RIO	0x8000
+
+#define PCIR_VENDOR_AURAVISION	0x11d1
+#define PCIR_DEVICE_AURAVISION_VXP524	0x01f7
+
+#define PCIR_VENDOR_IKON		0x11d5
+#define PCIR_DEVICE_IKON_10115	0x0115
+#define PCIR_DEVICE_IKON_10117	0x0117
+
+#define PCIR_VENDOR_ZORAN		0x11de
+#define PCIR_DEVICE_ZORAN_36057	0x6057
+#define PCIR_DEVICE_ZORAN_36120	0x6120
+
+#define PCIR_VENDOR_KINETIC		0x11f4
+#define PCIR_DEVICE_KINETIC_2915	0x2915
+
+#define PCIR_VENDOR_COMPEX		0x11f6
+#define PCIR_DEVICE_COMPEX_ENET100VG4	0x0112
+#define PCIR_DEVICE_COMPEX_RL2000	0x1401
+
+#define PCIR_VENDOR_RP               0x11fe
+#define PCIR_DEVICE_RP32INTF         0x0001
+#define PCIR_DEVICE_RP8INTF          0x0002
+#define PCIR_DEVICE_RP16INTF         0x0003
+#define PCIR_DEVICE_RP4QUAD	       0x0004
+#define PCIR_DEVICE_RP8OCTA          0x0005
+#define PCIR_DEVICE_RP8J	       0x0006
+#define PCIR_DEVICE_RPP4	       0x000A
+#define PCIR_DEVICE_RPP8	       0x000B
+#define PCIR_DEVICE_RP8M	       0x000C
+
+#define PCIR_VENDOR_CYCLADES		0x120e
+#define PCIR_DEVICE_CYCLOM_Y_Lo	0x0100
+#define PCIR_DEVICE_CYCLOM_Y_Hi	0x0101
+#define PCIR_DEVICE_CYCLOM_Z_Lo	0x0200
+#define PCIR_DEVICE_CYCLOM_Z_Hi	0x0201
+
+#define PCIR_VENDOR_ESSENTIAL		0x120f
+#define PCIR_DEVICE_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCIR_VENDOR_O2		0x1217
+#define PCIR_DEVICE_O2_6729		0x6729
+#define PCIR_DEVICE_O2_6730		0x673a
+#define PCIR_DEVICE_O2_6832		0x6832
+#define PCIR_DEVICE_O2_6836		0x6836
+
+#define PCIR_VENDOR_3DFX		0x121a
+#define PCIR_DEVICE_3DFX_VOODOO	0x0001
+#define PCIR_DEVICE_3DFX_VOODOO2	0x0002
+
+#define PCIR_VENDOR_SIGMADES		0x1236
+#define PCIR_DEVICE_SIGMADES_6425	0x6401
+
+#define PCIR_VENDOR_CCUBE		0x123f
+
+#define PCIR_VENDOR_DIPIX		0x1246
+
+#define PCIR_VENDOR_STALLION		0x124d
+#define PCIR_DEVICE_STALLION_ECHPCI832 0x0000
+#define PCIR_DEVICE_STALLION_ECHPCI864 0x0002
+#define PCIR_DEVICE_STALLION_EIOPCI	0x0003
+
+#define PCIR_VENDOR_OPTIBASE		0x1255
+#define PCIR_DEVICE_OPTIBASE_FORGE	0x1110
+#define PCIR_DEVICE_OPTIBASE_FUSION	0x1210
+#define PCIR_DEVICE_OPTIBASE_VPLEX	0x2110
+#define PCIR_DEVICE_OPTIBASE_VPLEXCC	0x2120
+#define PCIR_DEVICE_OPTIBASE_VQUEST	0x2130
+
+#define PCIR_VENDOR_SATSAGEM		0x1267
+#define PCIR_DEVICE_SATSAGEM_PCR2101	0x5352
+#define PCIR_DEVICE_SATSAGEM_TELSATTURBO 0x5a4b
+
+#define PCIR_VENDOR_HUGHES		0x1273
+#define PCIR_DEVICE_HUGHES_DIRECPC	0x0002
+
+#define PCIR_VENDOR_ENSONIQ		0x1274
+#define PCIR_DEVICE_ENSONIQ_AUDIOPCI	0x5000
+
+#define PCIR_VENDOR_ALTEON		0x12ae
+#define PCIR_DEVICE_ALTEON_ACENIC	0x0001
+
+#define PCIR_VENDOR_PICTUREL		0x12c5
+#define PCIR_DEVICE_PICTUREL_PCIVST	0x0081
+
+#define PCIR_VENDOR_NVIDIA_SGS	0x12d2
+#define PCIR_DEVICE_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCIR_VENDOR_CBOARDS		0x1307
+#define PCIR_DEVICE_CBOARDS_DAS1602_16 0x0001
+
+#define PCIR_VENDOR_SYMPHONY		0x1c1c
+#define PCIR_DEVICE_SYMPHONY_101	0x0001
+
+#define PCIR_VENDOR_TEKRAM		0x1de1
+#define PCIR_DEVICE_TEKRAM_DC290	0xdc29
+
+#define PCIR_VENDOR_3DLABS		0x3d3d
+#define PCIR_DEVICE_3DLABS_300SX	0x0001
+#define PCIR_DEVICE_3DLABS_500TX	0x0002
+#define PCIR_DEVICE_3DLABS_DELTA	0x0003
+#define PCIR_DEVICE_3DLABS_PERMEDIA	0x0004
+#define PCIR_DEVICE_3DLABS_MX		0x0006
+
+#define PCIR_VENDOR_AVANCE		0x4005
+#define PCIR_DEVICE_AVANCE_ALG2064	0x2064
+#define PCIR_DEVICE_AVANCE_2302	0x2302
+
+#define PCIR_VENDOR_NETVIN		0x4a14
+#define PCIR_DEVICE_NETVIN_NV5000SC	0x5000
+
+#define PCIR_VENDOR_S3		0x5333
+#define PCIR_DEVICE_S3_PLATO_PXS	0x0551
+#define PCIR_DEVICE_S3_ViRGE		0x5631
+#define PCIR_DEVICE_S3_TRIO		0x8811
+#define PCIR_DEVICE_S3_AURORA64VP	0x8812
+#define PCIR_DEVICE_S3_TRIO64UVP	0x8814
+#define PCIR_DEVICE_S3_ViRGE_VX	0x883d
+#define PCIR_DEVICE_S3_868		0x8880
+#define PCIR_DEVICE_S3_928		0x88b0
+#define PCIR_DEVICE_S3_864_1		0x88c0
+#define PCIR_DEVICE_S3_864_2		0x88c1
+#define PCIR_DEVICE_S3_964_1		0x88d0
+#define PCIR_DEVICE_S3_964_2		0x88d1
+#define PCIR_DEVICE_S3_968		0x88f0
+#define PCIR_DEVICE_S3_TRIO64V2	0x8901
+#define PCIR_DEVICE_S3_PLATO_PXG	0x8902
+#define PCIR_DEVICE_S3_ViRGE_DXGX	0x8a01
+#define PCIR_DEVICE_S3_ViRGE_GX2	0x8a10
+#define PCIR_DEVICE_S3_ViRGE_MX	0x8c01
+#define PCIR_DEVICE_S3_ViRGE_MXP	0x8c02
+#define PCIR_DEVICE_S3_ViRGE_MXPMV	0x8c03
+#define PCIR_DEVICE_S3_SONICVIBES	0xca00
+
+#define PCIR_VENDOR_INTEL		0x8086
+#define PCIR_DEVICE_INTEL_82375	0x0482
+#define PCIR_DEVICE_INTEL_82424	0x0483
+#define PCIR_DEVICE_INTEL_82378	0x0484
+#define PCIR_DEVICE_INTEL_82430	0x0486
+#define PCIR_DEVICE_INTEL_82434	0x04a3
+#define PCIR_DEVICE_INTEL_82092AA_0	0x1221
+#define PCIR_DEVICE_INTEL_82092AA_1	0x1222
+#define PCIR_DEVICE_INTEL_7116	0x1223
+#define PCIR_DEVICE_INTEL_82596	0x1226
+#define PCIR_DEVICE_INTEL_82865	0x1227
+#define PCIR_DEVICE_INTEL_82557	0x1229
+#define PCIR_DEVICE_INTEL_82437	0x122d
+#define PCIR_DEVICE_INTEL_82371FB_0	0x122e
+#define PCIR_DEVICE_INTEL_82371FB_1	0x1230
+#define PCIR_DEVICE_INTEL_82371MX	0x1234
+#define PCIR_DEVICE_INTEL_82437MX	0x1235
+#define PCIR_DEVICE_INTEL_82441	0x1237
+#define PCIR_DEVICE_INTEL_82380FB	0x124b
+#define PCIR_DEVICE_INTEL_82439	0x1250
+#define PCIR_DEVICE_INTEL_82371SB_0	0x7000
+#define PCIR_DEVICE_INTEL_82371SB_1	0x7010
+#define PCIR_DEVICE_INTEL_82371SB_2	0x7020
+#define PCIR_DEVICE_INTEL_82437VX	0x7030
+#define PCIR_DEVICE_INTEL_82439TX	0x7100
+#define PCIR_DEVICE_INTEL_82371AB_0	0x7110
+#define PCIR_DEVICE_INTEL_82371AB	0x7111
+#define PCIR_DEVICE_INTEL_82371AB_2	0x7112
+#define PCIR_DEVICE_INTEL_82371AB_3	0x7113
+#define PCIR_DEVICE_INTEL_82443LX_0	0x7180
+#define PCIR_DEVICE_INTEL_82443LX_1	0x7181
+#define PCIR_DEVICE_INTEL_82443BX_0	0x7190
+#define PCIR_DEVICE_INTEL_82443BX_1	0x7191
+#define PCIR_DEVICE_INTEL_82443BX_2	0x7192
+#define PCIR_DEVICE_INTEL_P6		0x84c4
+#define PCIR_DEVICE_INTEL_82450GX	0x84c5
+
+#define PCIR_VENDOR_KTI		0x8e2e
+#define PCIR_DEVICE_KTI_ET32P2	0x3000
+
+#define PCIR_VENDOR_ADAPTEC		0x9004
+#define PCIR_DEVICE_ADAPTEC_7810	0x1078
+#define PCIR_DEVICE_ADAPTEC_7850	0x5078
+#define PCIR_DEVICE_ADAPTEC_7855	0x5578
+#define PCIR_DEVICE_ADAPTEC_5800	0x5800
+#define PCIR_DEVICE_ADAPTEC_1480A	0x6075
+#define PCIR_DEVICE_ADAPTEC_7860	0x6078
+#define PCIR_DEVICE_ADAPTEC_7861	0x6178
+#define PCIR_DEVICE_ADAPTEC_7870	0x7078
+#define PCIR_DEVICE_ADAPTEC_7871	0x7178
+#define PCIR_DEVICE_ADAPTEC_7872	0x7278
+#define PCIR_DEVICE_ADAPTEC_7873	0x7378
+#define PCIR_DEVICE_ADAPTEC_7874	0x7478
+#define PCIR_DEVICE_ADAPTEC_7895	0x7895
+#define PCIR_DEVICE_ADAPTEC_7880	0x8078
+#define PCIR_DEVICE_ADAPTEC_7881	0x8178
+#define PCIR_DEVICE_ADAPTEC_7882	0x8278
+#define PCIR_DEVICE_ADAPTEC_7883	0x8378
+#define PCIR_DEVICE_ADAPTEC_7884	0x8478
+#define PCIR_DEVICE_ADAPTEC_1030	0x8b78
+
+#define PCIR_VENDOR_ADAPTEC2		0x9005
+#define PCIR_DEVICE_ADAPTEC2_2940U2	0x0010
+#define PCIR_DEVICE_ADAPTEC2_7890	0x001f
+#define PCIR_DEVICE_ADAPTEC2_3940U2	0x0050
+#define PCIR_DEVICE_ADAPTEC2_7896	0x005f
+
+#define PCIR_VENDOR_ATRONICS		0x907f
+#define PCIR_DEVICE_ATRONICS_2015	0x2015
+
+#define PCIR_VENDOR_HOLTEK		0x9412
+#define PCIR_DEVICE_HOLTEK_6565	0x6565
+
+#define PCIR_VENDOR_TIGERJET		0xe159
+#define PCIR_DEVICE_TIGERJET_300	0x0001
+
+#define PCIR_VENDOR_ARK		0xedd8
+#define PCIR_DEVICE_ARK_STING		0xa091
+#define PCIR_DEVICE_ARK_STINGARK	0xa099
+#define PCIR_DEVICE_ARK_2000MT	0xa0a1
 
 #endif /* !__PCI_IDS_H__ */
diff --git a/cpukit/libpci/pci/pcireg.h b/cpukit/libpci/pci/pcireg.h
new file mode 100644
index 0000000000..f2b2b74cf0
--- /dev/null
+++ b/cpukit/libpci/pci/pcireg.h
@@ -0,0 +1,931 @@
+/*-
+ * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
+ * All rights reserved.
+ *
+ * New PCI library written from scratch. Defines in this file was taken from
+ * FreeBSD commit f1d6f4778d2044502209708bc167c05f9aa48615.
+ * auto-generated pci_ids.h also reused from RTEMS.
+ * Copyright 2009, Cobham Gaisler AB
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef __PCI_REG_H__
+#define __PCI_REG_H__
+
+/*
+ * PCIM_xxx: mask to locate subfield in register
+ * PCIR_xxx: config register offset
+ * PCIC_xxx: device class
+ * PCIS_xxx: device subclass
+ * PCIP_xxx: device programming interface
+ * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
+ * PCID_xxx: device ID
+ * PCIY_xxx: capability identification number
+ * PCIZ_xxx: extended capability identification number
+ */
+
+/* some PCI bus constants */
+#define	PCI_DOMAINMAX	65535	/* highest supported domain number */
+#define	PCI_BUSMAX	255	/* highest supported bus number */
+#define	PCI_SLOTMAX	31	/* highest supported slot number */
+#define	PCI_FUNCMAX	7	/* highest supported function number */
+#define	PCI_REGMAX	255	/* highest supported config register addr. */
+#define	PCIE_REGMAX	4095	/* highest supported config register addr. */
+#define	PCI_MAXHDRTYPE	2
+
+#define	PCIE_ARI_SLOTMAX 0
+#define	PCIE_ARI_FUNCMAX 255
+
+#define	PCI_RID_BUS_SHIFT	8
+#define	PCI_RID_SLOT_SHIFT	3
+#define	PCI_RID_FUNC_SHIFT	0
+
+#define PCI_RID(bus, slot, func) \
+    ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
+    (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \
+    (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
+
+#define PCI_ARI_RID(bus, func) \
+    ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
+    (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
+
+#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)
+#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
+#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
+
+#define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
+#define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
+
+/* PCI config header registers for all devices */
+
+#define	PCIR_DEVVENDOR	0x00
+#define	PCIR_VENDOR	0x00
+#define	PCIR_DEVICE	0x02
+#define	PCIR_COMMAND	0x04
+#define	PCIM_CMD_PORTEN		0x0001
+#define	PCIM_CMD_MEMEN		0x0002
+#define	PCIM_CMD_BUSMASTEREN	0x0004
+#define	PCIM_CMD_SPECIALEN	0x0008
+#define	PCIM_CMD_MWRICEN	0x0010
+#define	PCIM_CMD_PERRESPEN	0x0040
+#define	PCIM_CMD_SERRESPEN	0x0100
+#define	PCIM_CMD_BACKTOBACK	0x0200
+#define	PCIM_CMD_INTxDIS	0x0400
+#define	PCIR_STATUS	0x06
+#define	PCIM_STATUS_INTxSTATE	0x0008
+#define	PCIM_STATUS_CAPPRESENT	0x0010
+#define	PCIM_STATUS_66CAPABLE	0x0020
+#define	PCIM_STATUS_BACKTOBACK	0x0080
+#define	PCIM_STATUS_MDPERR	0x0100
+#define	PCIM_STATUS_SEL_FAST	0x0000
+#define	PCIM_STATUS_SEL_MEDIMUM	0x0200
+#define	PCIM_STATUS_SEL_SLOW	0x0400
+#define	PCIM_STATUS_SEL_MASK	0x0600
+#define	PCIM_STATUS_STABORT	0x0800
+#define	PCIM_STATUS_RTABORT	0x1000
+#define	PCIM_STATUS_RMABORT	0x2000
+#define	PCIM_STATUS_SERR	0x4000
+#define	PCIM_STATUS_PERR	0x8000
+#define	PCIR_REVID	0x08
+#define	PCIR_PROGIF	0x09
+#define	PCIR_SUBCLASS	0x0a
+#define	PCIR_CLASS	0x0b
+#define	PCIR_CACHELNSZ	0x0c
+#define	PCIR_LATTIMER	0x0d
+#define	PCIR_HDRTYPE	0x0e
+#define	PCIM_HDRTYPE		0x7f
+#define	PCIM_HDRTYPE_NORMAL	0x00
+#define	PCIM_HDRTYPE_BRIDGE	0x01
+#define	PCIM_HDRTYPE_CARDBUS	0x02
+#define	PCIM_MFDEV		0x80
+#define	PCIR_BIST	0x0f
+
+/* Capability Register Offsets */
+
+#define	PCICAP_ID	0x0
+#define	PCICAP_NEXTPTR	0x1
+
+/* Capability Identification Numbers */
+
+#define	PCIY_PMG	0x01	/* PCI Power Management */
+#define	PCIY_AGP	0x02	/* AGP */
+#define	PCIY_VPD	0x03	/* Vital Product Data */
+#define	PCIY_SLOTID	0x04	/* Slot Identification */
+#define	PCIY_MSI	0x05	/* Message Signaled Interrupts */
+#define	PCIY_CHSWP	0x06	/* CompactPCI Hot Swap */
+#define	PCIY_PCIX	0x07	/* PCI-X */
+#define	PCIY_HT		0x08	/* HyperTransport */
+#define	PCIY_VENDOR	0x09	/* Vendor Unique */
+#define	PCIY_DEBUG	0x0a	/* Debug port */
+#define	PCIY_CRES	0x0b	/* CompactPCI central resource control */
+#define	PCIY_HOTPLUG	0x0c	/* PCI Hot-Plug */
+#define	PCIY_SUBVENDOR	0x0d	/* PCI-PCI bridge subvendor ID */
+#define	PCIY_AGP8X	0x0e	/* AGP 8x */
+#define	PCIY_SECDEV	0x0f	/* Secure Device */
+#define	PCIY_EXPRESS	0x10	/* PCI Express */
+#define	PCIY_MSIX	0x11	/* MSI-X */
+#define	PCIY_SATA	0x12	/* SATA */
+#define	PCIY_PCIAF	0x13	/* PCI Advanced Features */
+
+/* Extended Capability Register Fields */
+
+#define	PCIR_EXTCAP	0x100
+#define	PCIM_EXTCAP_ID		0x0000ffff
+#define	PCIM_EXTCAP_VER		0x000f0000
+#define	PCIM_EXTCAP_NEXTPTR	0xfff00000
+#define	PCI_EXTCAP_ID(ecap)	((ecap) & PCIM_EXTCAP_ID)
+#define	PCI_EXTCAP_VER(ecap)	(((ecap) & PCIM_EXTCAP_VER) >> 16)
+#define	PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
+
+/* Extended Capability Identification Numbers */
+
+#define	PCIZ_AER	0x0001	/* Advanced Error Reporting */
+#define	PCIZ_VC		0x0002	/* Virtual Channel if MFVC Ext Cap not set */
+#define	PCIZ_SERNUM	0x0003	/* Device Serial Number */
+#define	PCIZ_PWRBDGT	0x0004	/* Power Budgeting */
+#define	PCIZ_RCLINK_DCL	0x0005	/* Root Complex Link Declaration */
+#define	PCIZ_RCLINK_CTL	0x0006	/* Root Complex Internal Link Control */
+#define	PCIZ_RCEC_ASSOC	0x0007	/* Root Complex Event Collector Association */
+#define	PCIZ_MFVC	0x0008	/* Multi-Function Virtual Channel */
+#define	PCIZ_VC2	0x0009	/* Virtual Channel if MFVC Ext Cap set */
+#define	PCIZ_RCRB	0x000a	/* RCRB Header */
+#define	PCIZ_VENDOR	0x000b	/* Vendor Unique */
+#define	PCIZ_CAC	0x000c	/* Configuration Access Correction -- obsolete */
+#define	PCIZ_ACS	0x000d	/* Access Control Services */
+#define	PCIZ_ARI	0x000e	/* Alternative Routing-ID Interpretation */
+#define	PCIZ_ATS	0x000f	/* Address Translation Services */
+#define	PCIZ_SRIOV	0x0010	/* Single Root IO Virtualization */
+#define	PCIZ_MRIOV	0x0011	/* Multiple Root IO Virtualization */
+#define	PCIZ_MULTICAST	0x0012	/* Multicast */
+#define	PCIZ_PAGE_REQ	0x0013	/* Page Request */
+#define	PCIZ_AMD	0x0014	/* Reserved for AMD */
+#define	PCIZ_RESIZE_BAR	0x0015	/* Resizable BAR */
+#define	PCIZ_DPA	0x0016	/* Dynamic Power Allocation */
+#define	PCIZ_TPH_REQ	0x0017	/* TPH Requester */
+#define	PCIZ_LTR	0x0018	/* Latency Tolerance Reporting */
+#define	PCIZ_SEC_PCIE	0x0019	/* Secondary PCI Express */
+#define	PCIZ_PMUX	0x001a	/* Protocol Multiplexing */
+#define	PCIZ_PASID	0x001b	/* Process Address Space ID */
+#define	PCIZ_LN_REQ	0x001c	/* LN Requester */
+#define	PCIZ_DPC	0x001d	/* Downstream Porto Containment */
+#define	PCIZ_L1PM	0x001e	/* L1 PM Substates */
+
+/* config registers for header type 0 devices */
+
+#define	PCIR_BARS	0x10
+#define	PCIR_BAR(x)		(PCIR_BARS + (x) * 4)
+#define	PCIR_MAX_BAR_0		5
+#define	PCI_RID2BAR(rid)	(((rid) - PCIR_BARS) / 4)
+#define	PCI_BAR_IO(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
+#define	PCI_BAR_MEM(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
+#define	PCIM_BAR_SPACE		0x00000001
+#define	PCIM_BAR_MEM_SPACE	0
+#define	PCIM_BAR_IO_SPACE	1
+#define	PCIM_BAR_MEM_TYPE	0x00000006
+#define	PCIM_BAR_MEM_32		0
+#define	PCIM_BAR_MEM_1MB	2	/* Locate below 1MB in PCI <= 2.1 */
+#define	PCIM_BAR_MEM_64		4
+#define	PCIM_BAR_MEM_PREFETCH	0x00000008
+#define	PCIM_BAR_MEM_BASE	0xfffffffffffffff0ULL
+#define	PCIM_BAR_IO_RESERVED	0x00000002
+#define	PCIM_BAR_IO_BASE	0xfffffffc
+#define	PCIR_CIS	0x28
+#define	PCIM_CIS_ASI_MASK	0x00000007
+#define	PCIM_CIS_ASI_CONFIG	0
+#define	PCIM_CIS_ASI_BAR0	1
+#define	PCIM_CIS_ASI_BAR1	2
+#define	PCIM_CIS_ASI_BAR2	3
+#define	PCIM_CIS_ASI_BAR3	4
+#define	PCIM_CIS_ASI_BAR4	5
+#define	PCIM_CIS_ASI_BAR5	6
+#define	PCIM_CIS_ASI_ROM	7
+#define	PCIM_CIS_ADDR_MASK	0x0ffffff8
+#define	PCIM_CIS_ROM_MASK	0xf0000000
+#define	PCIM_CIS_CONFIG_MASK	0xff
+#define	PCIR_SUBVEND_0	0x2c
+#define	PCIR_SUBDEV_0	0x2e
+#define	PCIR_BIOS	0x30
+#define	PCIM_BIOS_ENABLE	0x01
+#define	PCIM_BIOS_ADDR_MASK	0xfffff800
+#define	PCIR_CAP_PTR	0x34
+#define	PCIR_INTLINE	0x3c
+#define	PCIR_INTPIN	0x3d
+#define	PCIR_MINGNT	0x3e
+#define	PCIR_MAXLAT	0x3f
+
+/* config registers for header type 1 (PCI-to-PCI bridge) devices */
+
+#define	PCIR_MAX_BAR_1	1
+#define	PCIR_SECSTAT_1	0x1e
+
+#define	PCIR_PRIBUS_1	0x18
+#define	PCIR_SECBUS_1	0x19
+#define	PCIR_SUBBUS_1	0x1a
+#define	PCIR_SECLAT_1	0x1b
+
+#define	PCIR_IOBASEL_1	0x1c
+#define	PCIR_IOLIMITL_1	0x1d
+#define	PCIR_IOBASEH_1	0x30
+#define	PCIR_IOLIMITH_1	0x32
+#define	PCIM_BRIO_16		0x0
+#define	PCIM_BRIO_32		0x1
+#define	PCIM_BRIO_MASK		0xf
+
+#define	PCIR_MEMBASE_1	0x20
+#define	PCIR_MEMLIMIT_1	0x22
+
+#define	PCIR_PMBASEL_1	0x24
+#define	PCIR_PMLIMITL_1	0x26
+#define	PCIR_PMBASEH_1	0x28
+#define	PCIR_PMLIMITH_1	0x2c
+#define	PCIM_BRPM_32		0x0
+#define	PCIM_BRPM_64		0x1
+#define	PCIM_BRPM_MASK		0xf
+
+#define	PCIR_BIOS_1	0x38
+#define	PCIR_BRIDGECTL_1 0x3e
+
+/* config registers for header type 2 (CardBus) devices */
+
+#define	PCIR_MAX_BAR_2	0
+#define	PCIR_CAP_PTR_2	0x14
+#define	PCIR_SECSTAT_2	0x16
+
+#define	PCIR_PRIBUS_2	0x18
+#define	PCIR_SECBUS_2	0x19
+#define	PCIR_SUBBUS_2	0x1a
+#define	PCIR_SECLAT_2	0x1b
+
+#define	PCIR_MEMBASE0_2	0x1c
+#define	PCIR_MEMLIMIT0_2 0x20
+#define	PCIR_MEMBASE1_2	0x24
+#define	PCIR_MEMLIMIT1_2 0x28
+#define	PCIR_IOBASE0_2	0x2c
+#define	PCIR_IOLIMIT0_2	0x30
+#define	PCIR_IOBASE1_2	0x34
+#define	PCIR_IOLIMIT1_2	0x38
+
+#define	PCIR_BRIDGECTL_2 0x3e
+
+#define	PCIR_SUBVEND_2	0x40
+#define	PCIR_SUBDEV_2	0x42
+
+#define	PCIR_PCCARDIF_2	0x44
+
+/* PCI device class, subclass and programming interface definitions */
+
+#define	PCIC_OLD	0x00
+#define	PCIS_OLD_NONVGA		0x00
+#define	PCIS_OLD_VGA		0x01
+
+#define	PCIC_STORAGE	0x01
+#define	PCIS_STORAGE_SCSI	0x00
+#define	PCIS_STORAGE_IDE	0x01
+#define	PCIP_STORAGE_IDE_MODEPRIM	0x01
+#define	PCIP_STORAGE_IDE_PROGINDPRIM	0x02
+#define	PCIP_STORAGE_IDE_MODESEC	0x04
+#define	PCIP_STORAGE_IDE_PROGINDSEC	0x08
+#define	PCIP_STORAGE_IDE_MASTERDEV	0x80
+#define	PCIS_STORAGE_FLOPPY	0x02
+#define	PCIS_STORAGE_IPI	0x03
+#define	PCIS_STORAGE_RAID	0x04
+#define	PCIS_STORAGE_ATA_ADMA	0x05
+#define	PCIS_STORAGE_SATA	0x06
+#define	PCIP_STORAGE_SATA_AHCI_1_0	0x01
+#define	PCIS_STORAGE_SAS	0x07
+#define	PCIS_STORAGE_NVM	0x08
+#define	PCIP_STORAGE_NVM_NVMHCI_1_0	0x01
+#define	PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0	0x02
+#define	PCIS_STORAGE_OTHER	0x80
+
+#define	PCIC_NETWORK	0x02
+#define	PCIS_NETWORK_ETHERNET	0x00
+#define	PCIS_NETWORK_TOKENRING	0x01
+#define	PCIS_NETWORK_FDDI	0x02
+#define	PCIS_NETWORK_ATM	0x03
+#define	PCIS_NETWORK_ISDN	0x04
+#define	PCIS_NETWORK_WORLDFIP	0x05
+#define	PCIS_NETWORK_PICMG	0x06
+#define	PCIS_NETWORK_OTHER	0x80
+
+#define	PCIC_DISPLAY	0x03
+#define	PCIS_DISPLAY_VGA	0x00
+#define	PCIS_DISPLAY_XGA	0x01
+#define	PCIS_DISPLAY_3D		0x02
+#define	PCIS_DISPLAY_OTHER	0x80
+
+#define	PCIC_MULTIMEDIA	0x04
+#define	PCIS_MULTIMEDIA_VIDEO	0x00
+#define	PCIS_MULTIMEDIA_AUDIO	0x01
+#define	PCIS_MULTIMEDIA_TELE	0x02
+#define	PCIS_MULTIMEDIA_HDA	0x03
+#define	PCIS_MULTIMEDIA_OTHER	0x80
+
+#define	PCIC_MEMORY	0x05
+#define	PCIS_MEMORY_RAM		0x00
+#define	PCIS_MEMORY_FLASH	0x01
+#define	PCIS_MEMORY_OTHER	0x80
+
+#define	PCIC_BRIDGE	0x06
+#define	PCIS_BRIDGE_HOST	0x00
+#define	PCIS_BRIDGE_ISA		0x01
+#define	PCIS_BRIDGE_EISA	0x02
+#define	PCIS_BRIDGE_MCA		0x03
+#define	PCIS_BRIDGE_PCI		0x04
+#define	PCIP_BRIDGE_PCI_SUBTRACTIVE	0x01
+#define	PCIS_BRIDGE_PCMCIA	0x05
+#define	PCIS_BRIDGE_NUBUS	0x06
+#define	PCIS_BRIDGE_CARDBUS	0x07
+#define	PCIS_BRIDGE_RACEWAY	0x08
+#define	PCIS_BRIDGE_PCI_TRANSPARENT 0x09
+#define	PCIS_BRIDGE_INFINIBAND	0x0a
+#define	PCIS_BRIDGE_OTHER	0x80
+
+#define	PCIC_SIMPLECOMM	0x07
+#define	PCIS_SIMPLECOMM_UART	0x00
+#define	PCIP_SIMPLECOMM_UART_8250	0x00
+#define	PCIP_SIMPLECOMM_UART_16450A	0x01
+#define	PCIP_SIMPLECOMM_UART_16550A	0x02
+#define	PCIP_SIMPLECOMM_UART_16650A	0x03
+#define	PCIP_SIMPLECOMM_UART_16750A	0x04
+#define	PCIP_SIMPLECOMM_UART_16850A	0x05
+#define	PCIP_SIMPLECOMM_UART_16950A	0x06
+#define	PCIS_SIMPLECOMM_PAR	0x01
+#define	PCIS_SIMPLECOMM_MULSER	0x02
+#define	PCIS_SIMPLECOMM_MODEM	0x03
+#define	PCIS_SIMPLECOMM_GPIB	0x04
+#define	PCIS_SIMPLECOMM_SMART_CARD 0x05
+#define	PCIS_SIMPLECOMM_OTHER	0x80
+
+#define	PCIC_BASEPERIPH	0x08
+#define	PCIS_BASEPERIPH_PIC	0x00
+#define	PCIP_BASEPERIPH_PIC_8259A	0x00
+#define	PCIP_BASEPERIPH_PIC_ISA		0x01
+#define	PCIP_BASEPERIPH_PIC_EISA	0x02
+#define	PCIP_BASEPERIPH_PIC_IO_APIC	0x10
+#define	PCIP_BASEPERIPH_PIC_IOX_APIC	0x20
+#define	PCIS_BASEPERIPH_DMA	0x01
+#define	PCIS_BASEPERIPH_TIMER	0x02
+#define	PCIS_BASEPERIPH_RTC	0x03
+#define	PCIS_BASEPERIPH_PCIHOT	0x04
+#define	PCIS_BASEPERIPH_SDHC	0x05
+#define	PCIS_BASEPERIPH_IOMMU	0x06
+#define	PCIS_BASEPERIPH_OTHER	0x80
+
+#define	PCIC_INPUTDEV	0x09
+#define	PCIS_INPUTDEV_KEYBOARD	0x00
+#define	PCIS_INPUTDEV_DIGITIZER	0x01
+#define	PCIS_INPUTDEV_MOUSE	0x02
+#define	PCIS_INPUTDEV_SCANNER	0x03
+#define	PCIS_INPUTDEV_GAMEPORT	0x04
+#define	PCIS_INPUTDEV_OTHER	0x80
+
+#define	PCIC_DOCKING	0x0a
+#define	PCIS_DOCKING_GENERIC	0x00
+#define	PCIS_DOCKING_OTHER	0x80
+
+#define	PCIC_PROCESSOR	0x0b
+#define	PCIS_PROCESSOR_386	0x00
+#define	PCIS_PROCESSOR_486	0x01
+#define	PCIS_PROCESSOR_PENTIUM	0x02
+#define	PCIS_PROCESSOR_ALPHA	0x10
+#define	PCIS_PROCESSOR_POWERPC	0x20
+#define	PCIS_PROCESSOR_MIPS	0x30
+#define	PCIS_PROCESSOR_COPROC	0x40
+
+#define	PCIC_SERIALBUS	0x0c
+#define	PCIS_SERIALBUS_FW	0x00
+#define	PCIS_SERIALBUS_ACCESS	0x01
+#define	PCIS_SERIALBUS_SSA	0x02
+#define	PCIS_SERIALBUS_USB	0x03
+#define	PCIP_SERIALBUS_USB_UHCI		0x00
+#define	PCIP_SERIALBUS_USB_OHCI		0x10
+#define	PCIP_SERIALBUS_USB_EHCI		0x20
+#define	PCIP_SERIALBUS_USB_XHCI		0x30
+#define	PCIP_SERIALBUS_USB_DEVICE	0xfe
+#define	PCIS_SERIALBUS_FC	0x04
+#define	PCIS_SERIALBUS_SMBUS	0x05
+#define	PCIS_SERIALBUS_INFINIBAND 0x06
+#define	PCIS_SERIALBUS_IPMI	0x07
+#define	PCIP_SERIALBUS_IPMI_SMIC	0x00
+#define	PCIP_SERIALBUS_IPMI_KCS		0x01
+#define	PCIP_SERIALBUS_IPMI_BT		0x02
+#define	PCIS_SERIALBUS_SERCOS	0x08
+#define	PCIS_SERIALBUS_CANBUS	0x09
+
+#define	PCIC_WIRELESS	0x0d
+#define	PCIS_WIRELESS_IRDA	0x00
+#define	PCIS_WIRELESS_IR	0x01
+#define	PCIS_WIRELESS_RF	0x10
+#define	PCIS_WIRELESS_BLUETOOTH	0x11
+#define	PCIS_WIRELESS_BROADBAND	0x12
+#define	PCIS_WIRELESS_80211A	0x20
+#define	PCIS_WIRELESS_80211B	0x21
+#define	PCIS_WIRELESS_OTHER	0x80
+
+#define	PCIC_INTELLIIO	0x0e
+#define	PCIS_INTELLIIO_I2O	0x00
+
+#define	PCIC_SATCOM	0x0f
+#define	PCIS_SATCOM_TV		0x01
+#define	PCIS_SATCOM_AUDIO	0x02
+#define	PCIS_SATCOM_VOICE	0x03
+#define	PCIS_SATCOM_DATA	0x04
+
+#define	PCIC_CRYPTO	0x10
+#define	PCIS_CRYPTO_NETCOMP	0x00
+#define	PCIS_CRYPTO_ENTERTAIN	0x10
+#define	PCIS_CRYPTO_OTHER	0x80
+
+#define	PCIC_DASP	0x11
+#define	PCIS_DASP_DPIO		0x00
+#define	PCIS_DASP_PERFCNTRS	0x01
+#define	PCIS_DASP_COMM_SYNC	0x10
+#define	PCIS_DASP_MGMT_CARD	0x20
+#define	PCIS_DASP_OTHER		0x80
+
+#define	PCIC_OTHER	0xff
+
+/* Bridge Control Values. */
+#define	PCIB_BCR_PERR_ENABLE		0x0001
+#define	PCIB_BCR_SERR_ENABLE		0x0002
+#define	PCIB_BCR_ISA_ENABLE		0x0004
+#define	PCIB_BCR_VGA_ENABLE		0x0008
+#define	PCIB_BCR_MASTER_ABORT_MODE	0x0020
+#define	PCIB_BCR_SECBUS_RESET		0x0040
+#define	PCIB_BCR_SECBUS_BACKTOBACK	0x0080
+#define	PCIB_BCR_PRI_DISCARD_TIMEOUT	0x0100
+#define	PCIB_BCR_SEC_DISCARD_TIMEOUT	0x0200
+#define	PCIB_BCR_DISCARD_TIMER_STATUS	0x0400
+#define	PCIB_BCR_DISCARD_TIMER_SERREN	0x0800
+
+/* PCI power manangement */
+#define	PCIR_POWER_CAP		0x2
+#define	PCIM_PCAP_SPEC			0x0007
+#define	PCIM_PCAP_PMEREQCLK		0x0008
+#define	PCIM_PCAP_DEVSPECINIT		0x0020
+#define	PCIM_PCAP_AUXPWR_0		0x0000
+#define	PCIM_PCAP_AUXPWR_55		0x0040
+#define	PCIM_PCAP_AUXPWR_100		0x0080
+#define	PCIM_PCAP_AUXPWR_160		0x00c0
+#define	PCIM_PCAP_AUXPWR_220		0x0100
+#define	PCIM_PCAP_AUXPWR_270		0x0140
+#define	PCIM_PCAP_AUXPWR_320		0x0180
+#define	PCIM_PCAP_AUXPWR_375		0x01c0
+#define	PCIM_PCAP_AUXPWRMASK		0x01c0
+#define	PCIM_PCAP_D1SUPP		0x0200
+#define	PCIM_PCAP_D2SUPP		0x0400
+#define	PCIM_PCAP_D0PME			0x0800
+#define	PCIM_PCAP_D1PME			0x1000
+#define	PCIM_PCAP_D2PME			0x2000
+#define	PCIM_PCAP_D3PME_HOT		0x4000
+#define	PCIM_PCAP_D3PME_COLD		0x8000
+
+#define	PCIR_POWER_STATUS	0x4
+#define	PCIM_PSTAT_D0			0x0000
+#define	PCIM_PSTAT_D1			0x0001
+#define	PCIM_PSTAT_D2			0x0002
+#define	PCIM_PSTAT_D3			0x0003
+#define	PCIM_PSTAT_DMASK		0x0003
+#define	PCIM_PSTAT_NOSOFTRESET		0x0008
+#define	PCIM_PSTAT_PMEENABLE		0x0100
+#define	PCIM_PSTAT_D0POWER		0x0000
+#define	PCIM_PSTAT_D1POWER		0x0200
+#define	PCIM_PSTAT_D2POWER		0x0400
+#define	PCIM_PSTAT_D3POWER		0x0600
+#define	PCIM_PSTAT_D0HEAT		0x0800
+#define	PCIM_PSTAT_D1HEAT		0x0a00
+#define	PCIM_PSTAT_D2HEAT		0x0c00
+#define	PCIM_PSTAT_D3HEAT		0x0e00
+#define	PCIM_PSTAT_DATASELMASK		0x1e00
+#define	PCIM_PSTAT_DATAUNKN		0x0000
+#define	PCIM_PSTAT_DATADIV10		0x2000
+#define	PCIM_PSTAT_DATADIV100		0x4000
+#define	PCIM_PSTAT_DATADIV1000		0x6000
+#define	PCIM_PSTAT_DATADIVMASK		0x6000
+#define	PCIM_PSTAT_PME			0x8000
+
+#define	PCIR_POWER_BSE		0x6
+#define	PCIM_PMCSR_BSE_D3B3		0x00
+#define	PCIM_PMCSR_BSE_D3B2		0x40
+#define	PCIM_PMCSR_BSE_BPCCE		0x80
+
+#define	PCIR_POWER_DATA		0x7
+
+/* VPD capability registers */
+#define	PCIR_VPD_ADDR		0x2
+#define	PCIR_VPD_DATA		0x4
+
+/* PCI Message Signalled Interrupts (MSI) */
+#define	PCIR_MSI_CTRL		0x2
+#define	PCIM_MSICTRL_VECTOR		0x0100
+#define	PCIM_MSICTRL_64BIT		0x0080
+#define	PCIM_MSICTRL_MME_MASK		0x0070
+#define	PCIM_MSICTRL_MME_1		0x0000
+#define	PCIM_MSICTRL_MME_2		0x0010
+#define	PCIM_MSICTRL_MME_4		0x0020
+#define	PCIM_MSICTRL_MME_8		0x0030
+#define	PCIM_MSICTRL_MME_16		0x0040
+#define	PCIM_MSICTRL_MME_32		0x0050
+#define	PCIM_MSICTRL_MMC_MASK		0x000E
+#define	PCIM_MSICTRL_MMC_1		0x0000
+#define	PCIM_MSICTRL_MMC_2		0x0002
+#define	PCIM_MSICTRL_MMC_4		0x0004
+#define	PCIM_MSICTRL_MMC_8		0x0006
+#define	PCIM_MSICTRL_MMC_16		0x0008
+#define	PCIM_MSICTRL_MMC_32		0x000A
+#define	PCIM_MSICTRL_MSI_ENABLE		0x0001
+#define	PCIR_MSI_ADDR		0x4
+#define	PCIR_MSI_ADDR_HIGH	0x8
+#define	PCIR_MSI_DATA		0x8
+#define	PCIR_MSI_DATA_64BIT	0xc
+#define	PCIR_MSI_MASK		0x10
+#define	PCIR_MSI_PENDING	0x14
+
+/* PCI-X definitions */
+
+/* For header type 0 devices */
+#define	PCIXR_COMMAND		0x2
+#define	PCIXM_COMMAND_DPERR_E		0x0001	/* Data Parity Error Recovery */
+#define	PCIXM_COMMAND_ERO		0x0002	/* Enable Relaxed Ordering */
+#define	PCIXM_COMMAND_MAX_READ		0x000c	/* Maximum Burst Read Count */
+#define	PCIXM_COMMAND_MAX_READ_512	0x0000
+#define	PCIXM_COMMAND_MAX_READ_1024	0x0004
+#define	PCIXM_COMMAND_MAX_READ_2048	0x0008
+#define	PCIXM_COMMAND_MAX_READ_4096	0x000c
+#define	PCIXM_COMMAND_MAX_SPLITS 	0x0070	/* Maximum Split Transactions */
+#define	PCIXM_COMMAND_MAX_SPLITS_1	0x0000
+#define	PCIXM_COMMAND_MAX_SPLITS_2	0x0010
+#define	PCIXM_COMMAND_MAX_SPLITS_3	0x0020
+#define	PCIXM_COMMAND_MAX_SPLITS_4	0x0030
+#define	PCIXM_COMMAND_MAX_SPLITS_8	0x0040
+#define	PCIXM_COMMAND_MAX_SPLITS_12	0x0050
+#define	PCIXM_COMMAND_MAX_SPLITS_16	0x0060
+#define	PCIXM_COMMAND_MAX_SPLITS_32	0x0070
+#define	PCIXM_COMMAND_VERSION		0x3000
+#define	PCIXR_STATUS		0x4
+#define	PCIXM_STATUS_DEVFN		0x000000FF
+#define	PCIXM_STATUS_BUS		0x0000FF00
+#define	PCIXM_STATUS_64BIT		0x00010000
+#define	PCIXM_STATUS_133CAP		0x00020000
+#define	PCIXM_STATUS_SC_DISCARDED	0x00040000
+#define	PCIXM_STATUS_UNEXP_SC		0x00080000
+#define	PCIXM_STATUS_COMPLEX_DEV	0x00100000
+#define	PCIXM_STATUS_MAX_READ		0x00600000
+#define	PCIXM_STATUS_MAX_READ_512	0x00000000
+#define	PCIXM_STATUS_MAX_READ_1024	0x00200000
+#define	PCIXM_STATUS_MAX_READ_2048	0x00400000
+#define	PCIXM_STATUS_MAX_READ_4096	0x00600000
+#define	PCIXM_STATUS_MAX_SPLITS		0x03800000
+#define	PCIXM_STATUS_MAX_SPLITS_1	0x00000000
+#define	PCIXM_STATUS_MAX_SPLITS_2	0x00800000
+#define	PCIXM_STATUS_MAX_SPLITS_3	0x01000000
+#define	PCIXM_STATUS_MAX_SPLITS_4	0x01800000
+#define	PCIXM_STATUS_MAX_SPLITS_8	0x02000000
+#define	PCIXM_STATUS_MAX_SPLITS_12	0x02800000
+#define	PCIXM_STATUS_MAX_SPLITS_16	0x03000000
+#define	PCIXM_STATUS_MAX_SPLITS_32	0x03800000
+#define	PCIXM_STATUS_MAX_CUM_READ	0x1C000000
+#define	PCIXM_STATUS_RCVD_SC_ERR	0x20000000
+#define	PCIXM_STATUS_266CAP		0x40000000
+#define	PCIXM_STATUS_533CAP		0x80000000
+
+/* For header type 1 devices (PCI-X bridges) */
+#define	PCIXR_SEC_STATUS	0x2
+#define	PCIXM_SEC_STATUS_64BIT		0x0001
+#define	PCIXM_SEC_STATUS_133CAP		0x0002
+#define	PCIXM_SEC_STATUS_SC_DISC	0x0004
+#define	PCIXM_SEC_STATUS_UNEXP_SC	0x0008
+#define	PCIXM_SEC_STATUS_SC_OVERRUN	0x0010
+#define	PCIXM_SEC_STATUS_SR_DELAYED	0x0020
+#define	PCIXM_SEC_STATUS_BUS_MODE	0x03c0
+#define	PCIXM_SEC_STATUS_VERSION	0x3000
+#define	PCIXM_SEC_STATUS_266CAP		0x4000
+#define	PCIXM_SEC_STATUS_533CAP		0x8000
+#define	PCIXR_BRIDGE_STATUS	0x4
+#define	PCIXM_BRIDGE_STATUS_DEVFN	0x000000FF
+#define	PCIXM_BRIDGE_STATUS_BUS		0x0000FF00
+#define	PCIXM_BRIDGE_STATUS_64BIT	0x00010000
+#define	PCIXM_BRIDGE_STATUS_133CAP	0x00020000
+#define	PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
+#define	PCIXM_BRIDGE_STATUS_UNEXP_SC	0x00080000
+#define	PCIXM_BRIDGE_STATUS_SC_OVERRUN	0x00100000
+#define	PCIXM_BRIDGE_STATUS_SR_DELAYED	0x00200000
+#define	PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
+#define	PCIXM_BRIDGE_STATUS_266CAP	0x40000000
+#define	PCIXM_BRIDGE_STATUS_533CAP	0x80000000
+
+/* HT (HyperTransport) Capability definitions */
+#define	PCIR_HT_COMMAND		0x2
+#define	PCIM_HTCMD_CAP_MASK		0xf800	/* Capability type. */
+#define	PCIM_HTCAP_SLAVE		0x0000	/* 000xx */
+#define	PCIM_HTCAP_HOST			0x2000	/* 001xx */
+#define	PCIM_HTCAP_SWITCH		0x4000	/* 01000 */
+#define	PCIM_HTCAP_INTERRUPT		0x8000	/* 10000 */
+#define	PCIM_HTCAP_REVISION_ID		0x8800	/* 10001 */
+#define	PCIM_HTCAP_UNITID_CLUMPING	0x9000	/* 10010 */
+#define	PCIM_HTCAP_EXT_CONFIG_SPACE	0x9800	/* 10011 */
+#define	PCIM_HTCAP_ADDRESS_MAPPING	0xa000	/* 10100 */
+#define	PCIM_HTCAP_MSI_MAPPING		0xa800	/* 10101 */
+#define	PCIM_HTCAP_DIRECT_ROUTE		0xb000	/* 10110 */
+#define	PCIM_HTCAP_VCSET		0xb800	/* 10111 */
+#define	PCIM_HTCAP_RETRY_MODE		0xc000	/* 11000 */
+#define	PCIM_HTCAP_X86_ENCODING		0xc800	/* 11001 */
+#define	PCIM_HTCAP_GEN3			0xd000	/* 11010 */
+#define	PCIM_HTCAP_FLE			0xd800	/* 11011 */
+#define	PCIM_HTCAP_PM			0xe000	/* 11100 */
+#define	PCIM_HTCAP_HIGH_NODE_COUNT	0xe800	/* 11101 */
+
+/* HT MSI Mapping Capability definitions. */
+#define	PCIM_HTCMD_MSI_ENABLE		0x0001
+#define	PCIM_HTCMD_MSI_FIXED		0x0002
+#define	PCIR_HTMSI_ADDRESS_LO	0x4
+#define	PCIR_HTMSI_ADDRESS_HI	0x8
+
+/* PCI Vendor capability definitions */
+#define	PCIR_VENDOR_LENGTH	0x2
+#define	PCIR_VENDOR_DATA	0x3
+
+/* PCI EHCI Debug Port definitions */
+#define	PCIR_DEBUG_PORT		0x2
+#define	PCIM_DEBUG_PORT_OFFSET		0x1FFF
+#define	PCIM_DEBUG_PORT_BAR		0xe000
+
+/* PCI-PCI Bridge Subvendor definitions */
+#define	PCIR_SUBVENDCAP_ID	0x4
+
+/* PCI Express definitions */
+#define	PCIER_FLAGS		0x2
+#define	PCIEM_FLAGS_VERSION		0x000F
+#define	PCIEM_FLAGS_TYPE		0x00F0
+#define	PCIEM_TYPE_ENDPOINT		0x0000
+#define	PCIEM_TYPE_LEGACY_ENDPOINT	0x0010
+#define	PCIEM_TYPE_ROOT_PORT		0x0040
+#define	PCIEM_TYPE_UPSTREAM_PORT	0x0050
+#define	PCIEM_TYPE_DOWNSTREAM_PORT	0x0060
+#define	PCIEM_TYPE_PCI_BRIDGE		0x0070
+#define	PCIEM_TYPE_PCIE_BRIDGE		0x0080
+#define	PCIEM_TYPE_ROOT_INT_EP		0x0090
+#define	PCIEM_TYPE_ROOT_EC		0x00a0
+#define	PCIEM_FLAGS_SLOT		0x0100
+#define	PCIEM_FLAGS_IRQ			0x3e00
+#define	PCIER_DEVICE_CAP	0x4
+#define	PCIEM_CAP_MAX_PAYLOAD		0x00000007
+#define	PCIEM_CAP_PHANTHOM_FUNCS	0x00000018
+#define	PCIEM_CAP_EXT_TAG_FIELD		0x00000020
+#define	PCIEM_CAP_L0S_LATENCY		0x000001c0
+#define	PCIEM_CAP_L1_LATENCY		0x00000e00
+#define	PCIEM_CAP_ROLE_ERR_RPT		0x00008000
+#define	PCIEM_CAP_SLOT_PWR_LIM_VAL	0x03fc0000
+#define	PCIEM_CAP_SLOT_PWR_LIM_SCALE	0x0c000000
+#define	PCIEM_CAP_FLR			0x10000000
+#define	PCIER_DEVICE_CTL	0x8
+#define	PCIEM_CTL_COR_ENABLE		0x0001
+#define	PCIEM_CTL_NFER_ENABLE		0x0002
+#define	PCIEM_CTL_FER_ENABLE		0x0004
+#define	PCIEM_CTL_URR_ENABLE		0x0008
+#define	PCIEM_CTL_RELAXED_ORD_ENABLE	0x0010
+#define	PCIEM_CTL_MAX_PAYLOAD		0x00e0
+#define	PCIEM_CTL_EXT_TAG_FIELD		0x0100
+#define	PCIEM_CTL_PHANTHOM_FUNCS	0x0200
+#define	PCIEM_CTL_AUX_POWER_PM		0x0400
+#define	PCIEM_CTL_NOSNOOP_ENABLE	0x0800
+#define	PCIEM_CTL_MAX_READ_REQUEST	0x7000
+#define	PCIEM_CTL_BRDG_CFG_RETRY	0x8000	/* PCI-E - PCI/PCI-X bridges */
+#define	PCIEM_CTL_INITIATE_FLR		0x8000	/* FLR capable endpoints */
+#define	PCIER_DEVICE_STA	0xa
+#define	PCIEM_STA_CORRECTABLE_ERROR	0x0001
+#define	PCIEM_STA_NON_FATAL_ERROR	0x0002
+#define	PCIEM_STA_FATAL_ERROR		0x0004
+#define	PCIEM_STA_UNSUPPORTED_REQ	0x0008
+#define	PCIEM_STA_AUX_POWER		0x0010
+#define	PCIEM_STA_TRANSACTION_PND	0x0020
+#define	PCIER_LINK_CAP		0xc
+#define	PCIEM_LINK_CAP_MAX_SPEED	0x0000000f
+#define	PCIEM_LINK_CAP_MAX_WIDTH	0x000003f0
+#define	PCIEM_LINK_CAP_ASPM		0x00000c00
+#define	PCIEM_LINK_CAP_L0S_EXIT		0x00007000
+#define	PCIEM_LINK_CAP_L1_EXIT		0x00038000
+#define	PCIEM_LINK_CAP_CLOCK_PM		0x00040000
+#define	PCIEM_LINK_CAP_SURPRISE_DOWN	0x00080000
+#define	PCIEM_LINK_CAP_DL_ACTIVE	0x00100000
+#define	PCIEM_LINK_CAP_LINK_BW_NOTIFY	0x00200000
+#define	PCIEM_LINK_CAP_ASPM_COMPLIANCE	0x00400000
+#define	PCIEM_LINK_CAP_PORT		0xff000000
+#define	PCIER_LINK_CTL		0x10
+#define	PCIEM_LINK_CTL_ASPMC_DIS	0x0000
+#define	PCIEM_LINK_CTL_ASPMC_L0S	0x0001
+#define	PCIEM_LINK_CTL_ASPMC_L1		0x0002
+#define	PCIEM_LINK_CTL_ASPMC		0x0003
+#define	PCIEM_LINK_CTL_RCB		0x0008
+#define	PCIEM_LINK_CTL_LINK_DIS		0x0010
+#define	PCIEM_LINK_CTL_RETRAIN_LINK	0x0020
+#define	PCIEM_LINK_CTL_COMMON_CLOCK	0x0040
+#define	PCIEM_LINK_CTL_EXTENDED_SYNC	0x0080
+#define	PCIEM_LINK_CTL_ECPM		0x0100
+#define	PCIEM_LINK_CTL_HAWD		0x0200
+#define	PCIEM_LINK_CTL_LBMIE		0x0400
+#define	PCIEM_LINK_CTL_LABIE		0x0800
+#define	PCIER_LINK_STA		0x12
+#define	PCIEM_LINK_STA_SPEED		0x000f
+#define	PCIEM_LINK_STA_WIDTH		0x03f0
+#define	PCIEM_LINK_STA_TRAINING_ERROR	0x0400
+#define	PCIEM_LINK_STA_TRAINING		0x0800
+#define	PCIEM_LINK_STA_SLOT_CLOCK	0x1000
+#define	PCIEM_LINK_STA_DL_ACTIVE	0x2000
+#define	PCIEM_LINK_STA_LINK_BW_MGMT	0x4000
+#define	PCIEM_LINK_STA_LINK_AUTO_BW	0x8000
+#define	PCIER_SLOT_CAP		0x14
+#define	PCIEM_SLOT_CAP_APB		0x00000001
+#define	PCIEM_SLOT_CAP_PCP		0x00000002
+#define	PCIEM_SLOT_CAP_MRLSP		0x00000004
+#define	PCIEM_SLOT_CAP_AIP		0x00000008
+#define	PCIEM_SLOT_CAP_PIP		0x00000010
+#define	PCIEM_SLOT_CAP_HPS		0x00000020
+#define	PCIEM_SLOT_CAP_HPC		0x00000040
+#define	PCIEM_SLOT_CAP_SPLV		0x00007f80
+#define	PCIEM_SLOT_CAP_SPLS		0x00018000
+#define	PCIEM_SLOT_CAP_EIP		0x00020000
+#define	PCIEM_SLOT_CAP_NCCS		0x00040000
+#define	PCIEM_SLOT_CAP_PSN		0xfff80000
+#define	PCIER_SLOT_CTL		0x18
+#define	PCIEM_SLOT_CTL_ABPE		0x0001
+#define	PCIEM_SLOT_CTL_PFDE		0x0002
+#define	PCIEM_SLOT_CTL_MRLSCE		0x0004
+#define	PCIEM_SLOT_CTL_PDCE		0x0008
+#define	PCIEM_SLOT_CTL_CCIE		0x0010
+#define	PCIEM_SLOT_CTL_HPIE		0x0020
+#define	PCIEM_SLOT_CTL_AIC		0x00c0
+#define	PCIEM_SLOT_CTL_PIC		0x0300
+#define	PCIEM_SLOT_CTL_PCC		0x0400
+#define	PCIEM_SLOT_CTL_EIC		0x0800
+#define	PCIEM_SLOT_CTL_DLLSCE		0x1000
+#define	PCIER_SLOT_STA		0x1a
+#define	PCIEM_SLOT_STA_ABP		0x0001
+#define	PCIEM_SLOT_STA_PFD		0x0002
+#define	PCIEM_SLOT_STA_MRLSC		0x0004
+#define	PCIEM_SLOT_STA_PDC		0x0008
+#define	PCIEM_SLOT_STA_CC		0x0010
+#define	PCIEM_SLOT_STA_MRLSS		0x0020
+#define	PCIEM_SLOT_STA_PDS		0x0040
+#define	PCIEM_SLOT_STA_EIS		0x0080
+#define	PCIEM_SLOT_STA_DLLSC		0x0100
+#define	PCIER_ROOT_CTL		0x1c
+#define	PCIEM_ROOT_CTL_SERR_CORR	0x0001
+#define	PCIEM_ROOT_CTL_SERR_NONFATAL	0x0002
+#define	PCIEM_ROOT_CTL_SERR_FATAL	0x0004
+#define	PCIEM_ROOT_CTL_PME		0x0008
+#define	PCIEM_ROOT_CTL_CRS_VIS		0x0010
+#define	PCIER_ROOT_CAP		0x1e
+#define	PCIEM_ROOT_CAP_CRS_VIS		0x0001
+#define	PCIER_ROOT_STA		0x20
+#define	PCIEM_ROOT_STA_PME_REQID_MASK	0x0000ffff
+#define	PCIEM_ROOT_STA_PME_STATUS	0x00010000
+#define	PCIEM_ROOT_STA_PME_PEND		0x00020000
+#define	PCIER_DEVICE_CAP2	0x24
+#define	PCIEM_CAP2_ARI		0x20
+#define	PCIER_DEVICE_CTL2	0x28
+#define	PCIEM_CTL2_COMP_TIMEOUT_VAL	0x000f
+#define	PCIEM_CTL2_COMP_TIMEOUT_DIS	0x0010
+#define	PCIEM_CTL2_ARI			0x0020
+#define	PCIEM_CTL2_ATOMIC_REQ_ENABLE	0x0040
+#define	PCIEM_CTL2_ATOMIC_EGR_BLOCK	0x0080
+#define	PCIEM_CTL2_ID_ORDERED_REQ_EN	0x0100
+#define	PCIEM_CTL2_ID_ORDERED_CMP_EN	0x0200
+#define	PCIEM_CTL2_LTR_ENABLE		0x0400
+#define	PCIEM_CTL2_OBFF			0x6000
+#define	PCIEM_OBFF_DISABLE		0x0000
+#define	PCIEM_OBFF_MSGA_ENABLE		0x2000
+#define	PCIEM_OBFF_MSGB_ENABLE		0x4000
+#define	PCIEM_OBFF_WAKE_ENABLE		0x6000
+#define	PCIEM_CTL2_END2END_TLP		0x8000
+#define	PCIER_DEVICE_STA2	0x2a
+#define	PCIER_LINK_CAP2		0x2c
+#define	PCIER_LINK_CTL2		0x30
+#define	PCIER_LINK_STA2		0x32
+#define	PCIER_SLOT_CAP2		0x34
+#define	PCIER_SLOT_CTL2		0x38
+#define	PCIER_SLOT_STA2		0x3a
+
+/* MSI-X definitions */
+#define	PCIR_MSIX_CTRL		0x2
+#define	PCIM_MSIXCTRL_MSIX_ENABLE	0x8000
+#define	PCIM_MSIXCTRL_FUNCTION_MASK	0x4000
+#define	PCIM_MSIXCTRL_TABLE_SIZE	0x07FF
+#define	PCIR_MSIX_TABLE		0x4
+#define	PCIR_MSIX_PBA		0x8
+#define	PCIM_MSIX_BIR_MASK		0x7
+#define	PCIM_MSIX_BIR_BAR_10		0
+#define	PCIM_MSIX_BIR_BAR_14		1
+#define	PCIM_MSIX_BIR_BAR_18		2
+#define	PCIM_MSIX_BIR_BAR_1C		3
+#define	PCIM_MSIX_BIR_BAR_20		4
+#define	PCIM_MSIX_BIR_BAR_24		5
+#define	PCIM_MSIX_VCTRL_MASK		0x1
+
+/* PCI Advanced Features definitions */
+#define	PCIR_PCIAF_CAP		0x3
+#define	PCIM_PCIAFCAP_TP	0x01
+#define	PCIM_PCIAFCAP_FLR	0x02
+#define	PCIR_PCIAF_CTRL		0x4
+#define	PCIR_PCIAFCTRL_FLR	0x01
+#define	PCIR_PCIAF_STATUS	0x5
+#define	PCIR_PCIAFSTATUS_TP	0x01
+
+/* Advanced Error Reporting */
+#define	PCIR_AER_UC_STATUS	0x04
+#define	PCIM_AER_UC_TRAINING_ERROR	0x00000001
+#define	PCIM_AER_UC_DL_PROTOCOL_ERROR	0x00000010
+#define	PCIM_AER_UC_SURPRISE_LINK_DOWN	0x00000020
+#define	PCIM_AER_UC_POISONED_TLP	0x00001000
+#define	PCIM_AER_UC_FC_PROTOCOL_ERROR	0x00002000
+#define	PCIM_AER_UC_COMPLETION_TIMEOUT	0x00004000
+#define	PCIM_AER_UC_COMPLETER_ABORT	0x00008000
+#define	PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000
+#define	PCIM_AER_UC_RECEIVER_OVERFLOW	0x00020000
+#define	PCIM_AER_UC_MALFORMED_TLP	0x00040000
+#define	PCIM_AER_UC_ECRC_ERROR		0x00080000
+#define	PCIM_AER_UC_UNSUPPORTED_REQUEST	0x00100000
+#define	PCIM_AER_UC_ACS_VIOLATION	0x00200000
+#define	PCIM_AER_UC_INTERNAL_ERROR	0x00400000
+#define	PCIM_AER_UC_MC_BLOCKED_TLP	0x00800000
+#define	PCIM_AER_UC_ATOMIC_EGRESS_BLK	0x01000000
+#define	PCIM_AER_UC_TLP_PREFIX_BLOCKED	0x02000000
+#define	PCIR_AER_UC_MASK	0x08	/* Shares bits with UC_STATUS */
+#define	PCIR_AER_UC_SEVERITY	0x0c	/* Shares bits with UC_STATUS */
+#define	PCIR_AER_COR_STATUS	0x10
+#define	PCIM_AER_COR_RECEIVER_ERROR	0x00000001
+#define	PCIM_AER_COR_BAD_TLP		0x00000040
+#define	PCIM_AER_COR_BAD_DLLP		0x00000080
+#define	PCIM_AER_COR_REPLAY_ROLLOVER	0x00000100
+#define	PCIM_AER_COR_REPLAY_TIMEOUT	0x00001000
+#define	PCIM_AER_COR_ADVISORY_NF_ERROR	0x00002000
+#define	PCIM_AER_COR_INTERNAL_ERROR	0x00004000
+#define	PCIM_AER_COR_HEADER_LOG_OVFLOW	0x00008000
+#define	PCIR_AER_COR_MASK	0x14	/* Shares bits with COR_STATUS */
+#define	PCIR_AER_CAP_CONTROL	0x18
+#define	PCIM_AER_FIRST_ERROR_PTR	0x0000001f
+#define	PCIM_AER_ECRC_GEN_CAPABLE	0x00000020
+#define	PCIM_AER_ECRC_GEN_ENABLE	0x00000040
+#define	PCIM_AER_ECRC_CHECK_CAPABLE	0x00000080
+#define	PCIM_AER_ECRC_CHECK_ENABLE	0x00000100
+#define	PCIM_AER_MULT_HDR_CAPABLE	0x00000200
+#define	PCIM_AER_MULT_HDR_ENABLE	0x00000400
+#define	PCIM_AER_TLP_PREFIX_LOG_PRESENT	0x00000800
+#define	PCIR_AER_HEADER_LOG	0x1c
+#define	PCIR_AER_ROOTERR_CMD	0x2c	/* Only for root complex ports */
+#define	PCIM_AER_ROOTERR_COR_ENABLE	0x00000001
+#define	PCIM_AER_ROOTERR_NF_ENABLE	0x00000002
+#define	PCIM_AER_ROOTERR_F_ENABLE	0x00000004
+#define	PCIR_AER_ROOTERR_STATUS	0x30	/* Only for root complex ports */
+#define	PCIM_AER_ROOTERR_COR_ERR	0x00000001
+#define	PCIM_AER_ROOTERR_MULTI_COR_ERR	0x00000002
+#define	PCIM_AER_ROOTERR_UC_ERR		0x00000004
+#define	PCIM_AER_ROOTERR_MULTI_UC_ERR	0x00000008
+#define	PCIM_AER_ROOTERR_FIRST_UC_FATAL	0x00000010
+#define	PCIM_AER_ROOTERR_NF_ERR		0x00000020
+#define	PCIM_AER_ROOTERR_F_ERR		0x00000040
+#define	PCIM_AER_ROOTERR_INT_MESSAGE	0xf8000000
+#define	PCIR_AER_COR_SOURCE_ID	0x34	/* Only for root complex ports */
+#define	PCIR_AER_ERR_SOURCE_ID	0x36	/* Only for root complex ports */
+#define	PCIR_AER_TLP_PREFIX_LOG	0x38	/* Only for TLP prefix functions */
+
+/* Virtual Channel definitions */
+#define	PCIR_VC_CAP1		0x04
+#define	PCIM_VC_CAP1_EXT_COUNT		0x00000007
+#define	PCIM_VC_CAP1_LOWPRI_EXT_COUNT	0x00000070
+#define	PCIR_VC_CAP2		0x08
+#define	PCIR_VC_CONTROL		0x0C
+#define	PCIR_VC_STATUS		0x0E
+#define	PCIR_VC_RESOURCE_CAP(n)	(0x10 + (n) * 0x0C)
+#define	PCIR_VC_RESOURCE_CTL(n)	(0x14 + (n) * 0x0C)
+#define	PCIR_VC_RESOURCE_STA(n)	(0x18 + (n) * 0x0C)
+
+/* Serial Number definitions */
+#define	PCIR_SERIAL_LOW		0x04
+#define	PCIR_SERIAL_HIGH	0x08
+
+#endif /* __PCI_REG_H__*/
diff --git a/cpukit/libpci/pci_access.c b/cpukit/libpci/pci_access.c
index 8fdf7ca7c7..62336f12c6 100644
--- a/cpukit/libpci/pci_access.c
+++ b/cpukit/libpci/pci_access.c
@@ -55,10 +55,10 @@ void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val)
 {
 	uint32_t data;
 
-	pci_cfg_r32(dev, PCI_COMMAND, &data);
+	pci_cfg_r32(dev, PCIR_COMMAND, &data);
 	data &= ~mask;
 	data |= val;
-	pci_cfg_w32(dev, PCI_COMMAND, data);
+	pci_cfg_w32(dev, PCIR_COMMAND, data);
 }
 
 /* Register a driver for handling access to PCI */
diff --git a/cpukit/libpci/pci_cfg_auto.c b/cpukit/libpci/pci_cfg_auto.c
index 3f9c75fee8..2afc861a2d 100644
--- a/cpukit/libpci/pci_cfg_auto.c
+++ b/cpukit/libpci/pci_cfg_auto.c
@@ -302,14 +302,14 @@ static void pci_find_devs(struct pci_bus *bus)
 	DBG("Scanning bus %d\n", bus->num);
 
 	listptr = &bus->devs;
-	for (slot = 0; slot < PCI_MAX_DEVICES; slot++) {
+	for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
 
 		/* Slot address */
 		pcidev = PCI_DEV(bus->num, slot, 0);
 
-		for (func = 0; func < PCI_MAX_FUNCTIONS; func++, pcidev++) {
+		for (func = 0; func <= PCI_FUNCMAX; func++, pcidev++) {
 
-			fail = PCI_CFG_R32(pcidev, PCI_VENDOR_ID, &id);
+			fail = PCI_CFG_R32(pcidev, PCIR_VENDOR, &id);
 			if (fail || id == 0xffffffff || id == 0) {
 				/*
 				 * This slot is empty
@@ -326,27 +326,27 @@ static void pci_find_devs(struct pci_bus *bus)
 			/* Set command to reset values, it disables bus
 			 * mastering and address responses.
 			 */
-			PCI_CFG_W16(pcidev, PCI_COMMAND, 0);
+			PCI_CFG_W16(pcidev, PCIR_COMMAND, 0);
 
 			/* Clear any already set status bits */
-			PCI_CFG_W16(pcidev, PCI_STATUS, 0xf900);
+			PCI_CFG_W16(pcidev, PCIR_STATUS, 0xf900);
 
 			/* Set latency timer to 64 */
-			PCI_CFG_W8(pcidev, PCI_LATENCY_TIMER, 64);
+			PCI_CFG_W8(pcidev, PCIR_LATTIMER, 64);
 
-			PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &tmp);
+			PCI_CFG_R32(pcidev, PCIR_REVID, &tmp);
 			tmp >>= 16;
-			dev = pci_dev_create(tmp == PCI_CLASS_BRIDGE_PCI);
+			dev = pci_dev_create(tmp == PCID_PCI2PCI_BRIDGE);
 			*listptr = dev;
 			listptr = &dev->next;
 
 			dev->busdevfun = pcidev;
 			dev->bus = bus;
-			PCI_CFG_R16(pcidev, PCI_VENDOR_ID, &dev->vendor);
-			PCI_CFG_R16(pcidev, PCI_DEVICE_ID, &dev->device);
-			PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &dev->classrev);
+			PCI_CFG_R16(pcidev, PCIR_VENDOR, &dev->vendor);
+			PCI_CFG_R16(pcidev, PCIR_DEVICE, &dev->device);
+			PCI_CFG_R32(pcidev, PCIR_REVID, &dev->classrev);
 
-			if (tmp == PCI_CLASS_BRIDGE_PCI) {
+			if (tmp == PCID_PCI2PCI_BRIDGE) {
 				DBG("Found PCI-PCI Bridge 0x%x at "
 				    "(bus %x, slot %x, func %x)\n",
 				    id, bus, slot, func);
@@ -363,7 +363,7 @@ static void pci_find_devs(struct pci_bus *bus)
 				PCI_CFG_W32(pcidev, 0x2C, 0);
 				tmp = (64 << 24) | (0xff << 16) |
 				      (bridge->num << 8) | bridge->pri;
-				PCI_CFG_W32(pcidev, PCI_PRIMARY_BUS, tmp);
+				PCI_CFG_W32(pcidev, PCIR_PRIBUS_1, tmp);
 
 				/* Scan Secondary Bus */
 				pci_find_devs(bridge);
@@ -377,19 +377,19 @@ static void pci_find_devs(struct pci_bus *bus)
 				    bridge->pri, bridge->num, bridge->sord);
 			} else {
 				/* Disable Cardbus CIS Pointer */
-				PCI_CFG_W32(pcidev, PCI_CARDBUS_CIS, 0);
+				PCI_CFG_W32(pcidev, PCIR_CIS, 0);
 
 				/* Devices have subsytem device and vendor ID */
-				PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_VENDOR_ID,
+				PCI_CFG_R16(pcidev, PCIR_SUBVEND_0,
 							&dev->subvendor);
-				PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_ID,
+				PCI_CFG_R16(pcidev, PCIR_SUBDEV_0,
 							&dev->subdevice);
 			}
 
 			/* Stop if not a multi-function device */
 			if (func == 0) {
-				pci_cfg_r8(pcidev, PCI_HEADER_TYPE, &header);
-				if ((header & PCI_MULTI_FUNCTION) == 0)
+				pci_cfg_r8(pcidev, PCIR_HDRTYPE, &header);
+				if ((header & PCIM_MFDEV) == 0)
 					break;
 			}
 		}
@@ -415,12 +415,12 @@ static void pci_find_bar(struct pci_dev *dev, int bar)
 	res->bar = bar;
 	if (bar == DEV_RES_ROM) {
 		if (dev->flags & PCI_DEV_BRIDGE)
-			ofs = PCI_ROM_ADDRESS1;
+			ofs = PCIR_BIOS_1;
 		else
-			ofs = PCI_ROM_ADDRESS;
+			ofs = PCIR_BIOS;
 		disable = 0; /* ROM BARs have a unique enable bit per BAR */
 	} else {
-		ofs = PCI_BASE_ADDRESS_0 + (bar << 2);
+		ofs = PCIR_BAR(0) + (bar << 2);
 		disable = pci_invalid_address;
 	}
 
@@ -431,7 +431,7 @@ static void pci_find_bar(struct pci_dev *dev, int bar)
 	if (size == 0 || size == 0xffffffff)
 		return;
 	if (bar == DEV_RES_ROM) {
-		mask = PCI_ROM_ADDRESS_MASK;
+		mask = PCIM_BIOS_ADDR_MASK;
 		DBG_SET_STR(str, "ROM");
 		if (dev->bus->flags & PCI_BUS_MEM)
 			res->flags = PCI_RES_MEM;
@@ -731,10 +731,10 @@ static void pci_set_bar(struct pci_dev *dev, int residx)
 	if (res->bar == DEV_RES_ROM) {
 		/* ROM: 32-bit prefetchable memory BAR */
 		if (is_bridge)
-			ofs = PCI_ROM_ADDRESS1;
+			ofs = PCIR_BIOS_1;
 		else
-			ofs = PCI_ROM_ADDRESS;
-		PCI_CFG_W32(pcidev, ofs, res->start | PCI_ROM_ADDRESS_ENABLE);
+			ofs = PCIR_BIOS;
+		PCI_CFG_W32(pcidev, ofs, res->start | PCIM_BIOS_ENABLE);
 		DBG("PCI[%x:%x:%x]: ROM BAR: 0x%x-0x%x\n",
 			PCI_DEV_EXPAND(pcidev), res->start, res->end);
 	} else if (is_bridge && (res->bar == BRIDGE_RES_IO)) {
@@ -765,7 +765,7 @@ static void pci_set_bar(struct pci_dev *dev, int residx)
 		/* PCI Device */
 		DBG("PCI[%x:%x:%x]: DEV BAR%d: 0x%08x\n",
 			PCI_DEV_EXPAND(pcidev), res->bar, res->start);
-		ofs = PCI_BASE_ADDRESS_0 + res->bar*4;
+		ofs = PCIR_BAR(0) + res->bar*4;
 		PCI_CFG_W32(pcidev, ofs, res->start);
 	}
 
@@ -827,7 +827,7 @@ static int pci_set_irq_dev(struct pci_dev *dev, void *cfg)
 
 	psysirq = &dev->sysirq;
 	pcidev = dev->busdevfun;
-	PCI_CFG_R8(pcidev, PCI_INTERRUPT_PIN, &irq_pin);
+	PCI_CFG_R8(pcidev, PCIR_INTPIN, &irq_pin);
 
 	/* perform IRQ routing until we reach host bridge */
 	while (dev->bus && irq_pin != 0) {
@@ -844,7 +844,7 @@ static int pci_set_irq_dev(struct pci_dev *dev, void *cfg)
 	*psysirq = irq_line;
 
 	/* Set System Interrupt/Vector for device. 0 means no-IRQ */
-	PCI_CFG_W8(pcidev, PCI_INTERRUPT_LINE, irq_line);
+	PCI_CFG_W8(pcidev, PCIR_INTLINE, irq_line);
 
 	return 0;
 }
diff --git a/cpukit/libpci/pci_cfg_read.c b/cpukit/libpci/pci_cfg_read.c
index b68eb47898..a2154d2abe 100644
--- a/cpukit/libpci/pci_cfg_read.c
+++ b/cpukit/libpci/pci_cfg_read.c
@@ -109,11 +109,11 @@ static void pci_read_bar(struct pci_dev *dev, int bar)
 	res->bar = bar;
 	if (bar == DEV_RES_ROM) {
 		if (dev->flags & PCI_DEV_BRIDGE)
-			ofs = PCI_ROM_ADDRESS1;
+			ofs = PCIR_BIOS_1;
 		else
-			ofs = PCI_ROM_ADDRESS;
+			ofs = PCIR_BIOS;
 	} else {
-		ofs = PCI_BASE_ADDRESS_0 + (bar << 2);
+		ofs = PCIR_BAR(0) + (bar << 2);
 	}
 
 	PCI_CFG_R32(pcidev, ofs, &orig);
@@ -124,7 +124,7 @@ static void pci_read_bar(struct pci_dev *dev, int bar)
 	if (size == 0 || size == 0xffffffff)
 		return;
 	if (bar == DEV_RES_ROM) {
-		mask = PCI_ROM_ADDRESS_MASK;
+		mask = PCIM_BIOS_ADDR_MASK;
 		DBG_SET_STR(str, "ROM");
 		if (dev->bus->flags & PCI_BUS_MEM)
 			res->flags = PCI_RES_MEM;
@@ -192,14 +192,14 @@ static void pci_read_devs(struct pci_bus *bus)
 
 	max_sord = bus->num;
 	listptr = &bus->devs;
-	for (slot = 0; slot < PCI_MAX_DEVICES; slot++) {
+	for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
 
 		/* Slot address */
 		pcidev = PCI_DEV(bus->num, slot, 0);
 
-		for (func = 0; func < PCI_MAX_FUNCTIONS; func++, pcidev++) {
+		for (func = 0; func <= PCI_FUNCMAX; func++, pcidev++) {
 
-			fail = PCI_CFG_R32(pcidev, PCI_VENDOR_ID, &id);
+			fail = PCI_CFG_R32(pcidev, PCIR_VENDOR, &id);
 			if (fail || id == 0xffffffff || id == 0) {
 				/*
 				 * This slot is empty
@@ -213,26 +213,26 @@ static void pci_read_devs(struct pci_bus *bus)
 			DBG("Found PCIDEV 0x%x at (bus %x, slot %x, func %x)\n",
 							id, bus, slot, func);
 
-			PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &tmp);
+			PCI_CFG_R32(pcidev, PCIR_REVID, &tmp);
 			tmp >>= 16;
-			dev = pci_dev_create(tmp == PCI_CLASS_BRIDGE_PCI);
+			dev = pci_dev_create(tmp == PCID_PCI2PCI_BRIDGE);
 			*listptr = dev;
 			listptr = &dev->next;
 
 			dev->busdevfun = pcidev;
 			dev->bus = bus;
-			PCI_CFG_R16(pcidev, PCI_VENDOR_ID, &dev->vendor);
-			PCI_CFG_R16(pcidev, PCI_DEVICE_ID, &dev->device);
-			PCI_CFG_R32(pcidev, PCI_CLASS_REVISION, &dev->classrev);
+			PCI_CFG_R16(pcidev, PCIR_VENDOR, &dev->vendor);
+			PCI_CFG_R16(pcidev, PCIR_DEVICE, &dev->device);
+			PCI_CFG_R32(pcidev, PCIR_REVID, &dev->classrev);
 
-			if (tmp == PCI_CLASS_BRIDGE_PCI) {
+			if (tmp == PCID_PCI2PCI_BRIDGE) {
 				DBG("Found PCI-PCI Bridge 0x%x at "
 				    "(bus %x, slot %x, func %x)\n",
 				    id, bus, slot, func);
 				dev->flags = PCI_DEV_BRIDGE;
 				bridge = (struct pci_bus *)dev;
 
-				PCI_CFG_R32(pcidev, PCI_PRIMARY_BUS, &tmp);
+				PCI_CFG_R32(pcidev, PCIR_PRIBUS_1, &tmp);
 				bridge->pri = tmp & 0xff;
 				bridge->num = (tmp >> 8) & 0xff;
 				bridge->sord = (tmp >> 16) & 0xff;
@@ -308,9 +308,9 @@ static void pci_read_devs(struct pci_bus *bus)
 				maxbars = 2;
 			} else {
 				/* Devices have subsytem device and vendor ID */
-				PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_VENDOR_ID,
+				PCI_CFG_R16(pcidev, PCIR_SUBVEND_0,
 							&dev->subvendor);
-				PCI_CFG_R16(pcidev, PCI_SUBSYSTEM_ID,
+				PCI_CFG_R16(pcidev, PCIR_SUBDEV_0,
 							&dev->subdevice);
 
 				/* Normal PCI Device has max 6 BARs */
@@ -325,12 +325,12 @@ static void pci_read_devs(struct pci_bus *bus)
 			/* Get System Interrupt/Vector for device.
 			 * 0 means no-IRQ
 			 */
-			PCI_CFG_R8(pcidev, PCI_INTERRUPT_LINE, &dev->sysirq);
+			PCI_CFG_R8(pcidev, PCIR_INTLINE, &dev->sysirq);
 
 			/* Stop if not a multi-function device */
 			if (func == 0) {
-				pci_cfg_r8(pcidev, PCI_HEADER_TYPE, &header);
-				if ((header & PCI_MULTI_FUNCTION) == 0)
+				pci_cfg_r8(pcidev, PCIR_HDRTYPE, &header);
+				if ((header & PCIM_MFDEV) == 0)
 					break;
 			}
 		}
diff --git a/cpukit/libpci/pci_cfg_static.c b/cpukit/libpci/pci_cfg_static.c
index ad3182e91e..5ec224238d 100644
--- a/cpukit/libpci/pci_cfg_static.c
+++ b/cpukit/libpci/pci_cfg_static.c
@@ -45,36 +45,36 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 	/* Set command to reset values, it disables bus
 	 * mastering and address responses.
 	 */
-	PCI_CFG_W16(pcidev, PCI_COMMAND, 0);
+	PCI_CFG_W16(pcidev, PCIR_COMMAND, 0);
 
 	/* Clear any already set status bits */
-	PCI_CFG_W16(pcidev, PCI_STATUS, 0xf900);
+	PCI_CFG_W16(pcidev, PCIR_STATUS, 0xf900);
 
 	/* Set latency timer to 64 */
-	PCI_CFG_W8(pcidev, PCI_LATENCY_TIMER, 64);
+	PCI_CFG_W8(pcidev, PCIR_LATTIMER, 64);
 
 	/* Set System IRQ of PIN */
-	PCI_CFG_W8(pcidev, PCI_INTERRUPT_LINE, dev->sysirq);
+	PCI_CFG_W8(pcidev, PCIR_INTLINE, dev->sysirq);
 
 	cmd = dev->command;
 
 	if ((dev->flags & PCI_DEV_BRIDGE) == 0) {
 		/* Disable Cardbus CIS Pointer */
-		PCI_CFG_W32(pcidev, PCI_CARDBUS_CIS, 0);
+		PCI_CFG_W32(pcidev, PCIR_CIS, 0);
 
-		romofs = PCI_ROM_ADDRESS;
+		romofs = PCIR_BIOS;
 		maxbars = 6;
 	} else {
 		/* Init Bridge */
 
 		/* Configure bridge (no support for 64-bit) */
-		PCI_CFG_W32(pcidev, PCI_PREF_BASE_UPPER32, 0);
-		PCI_CFG_W32(pcidev, PCI_PREF_LIMIT_UPPER32, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0);
 
 		bridge = (struct pci_bus *)dev;
 		tmp = (64 << 24) | (bridge->sord << 16) |
 			(bridge->num << 8) | bridge->pri;
-		PCI_CFG_W32(pcidev, PCI_PRIMARY_BUS, tmp);
+		PCI_CFG_W32(pcidev, PCIR_PRIBUS_1, tmp);
 
 		/*** Setup I/O Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_IO];
@@ -82,44 +82,44 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 			tmp16 = ((res->end-1) & 0x0000f000) |
 				((res->start & 0x0000f000) >> 8);
 			tmp = ((res->end-1) & 0xffff0000) | (res->start >> 16);
-			cmd |= PCI_COMMAND_IO;
+			cmd |= PCIM_CMD_PORTEN;
 		} else {
 			tmp16 = 0x00ff;
 			tmp = 0;
 		}
 		/* I/O Limit and Base */
-		PCI_CFG_W16(pcidev, PCI_IO_BASE, tmp16);
-		PCI_CFG_W32(pcidev, PCI_IO_BASE_UPPER16, tmp);
+		PCI_CFG_W16(pcidev, PCIR_IOBASEL_1, tmp16);
+		PCI_CFG_W32(pcidev, PCIR_IOBASEH_1, tmp);
 
 		/*** Setup MEMIO Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_MEMIO];
 		if (res->size > 0) {
 			tmp = ((res->end-1) & 0xffff0000) |
 				(res->start >> 16);
-			cmd |= PCI_COMMAND_MEMORY;
+			cmd |= PCIM_CMD_MEMEN;
 		} else {
 			tmp = 0x0000ffff;
 		}
 		/* MEMIO Limit and Base */
-		PCI_CFG_W32(pcidev, PCI_MEMORY_BASE, tmp);
+		PCI_CFG_W32(pcidev, PCIR_MEMBASE_1, tmp);
 
 		/*** Setup MEM Bridge Window ***/
 		res = &dev->resources[BRIDGE_RES_MEM];
 		if (res->size > 0) {
 			tmp = ((res->end-1) & 0xffff0000) |
 				(res->start >> 16);
-			cmd |= PCI_COMMAND_MEMORY;
+			cmd |= PCIM_CMD_MEMEN;
 		} else {
 			tmp = 0x0000ffff;
 		}
 		/* MEM Limit and Base */
-		PCI_CFG_W32(pcidev, PCI_PREF_MEMORY_BASE, tmp);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEL_1, tmp);
 		/* 64-bit space not supported */
-		PCI_CFG_W32(pcidev, PCI_PREF_BASE_UPPER32, 0);
-		PCI_CFG_W32(pcidev, PCI_PREF_LIMIT_UPPER32, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMBASEH_1, 0);
+		PCI_CFG_W32(pcidev, PCIR_PMLIMITH_1, 0);
 
-		cmd |= PCI_COMMAND_MASTER;
-		romofs = PCI_ROM_ADDRESS1;
+		cmd |= PCIM_CMD_BUSMASTEREN;
+		romofs = PCIR_BIOS_1;
 		maxbars = 2;
 	}
 
@@ -127,20 +127,20 @@ static int pci_init_dev(struct pci_dev *dev, void *unused)
 	for (i = 0; i < maxbars; i++) {
 		res = &dev->resources[i];
 		if (res->flags & PCI_RES_TYPE_MASK) {
-			PCI_CFG_W32(pcidev, PCI_BASE_ADDRESS_0 + 4*i,
+			PCI_CFG_W32(pcidev, PCIR_BAR(0) + 4*i,
 								res->start);
 			if ((res->flags & PCI_RES_TYPE_MASK) == PCI_RES_IO)
-				cmd |= PCI_COMMAND_IO;
+				cmd |= PCIM_CMD_PORTEN;
 			else
-				cmd |= PCI_COMMAND_MEMORY;
+				cmd |= PCIM_CMD_MEMEN;
 		}
 	}
 	res = &dev->resources[DEV_RES_ROM];
 	if (res->flags & PCI_RES_TYPE_MASK) {
-		PCI_CFG_W32(pcidev, romofs, res->start|PCI_ROM_ADDRESS_ENABLE);
-		cmd |= PCI_COMMAND_MEMORY;
+		PCI_CFG_W32(pcidev, romofs, res->start|PCIM_BIOS_ENABLE);
+		cmd |= PCIM_CMD_MEMEN;
 	}
-	PCI_CFG_W16(pcidev, PCI_COMMAND, cmd);
+	PCI_CFG_W16(pcidev, PCIR_COMMAND, cmd);
 
 	return 0;
 }
diff --git a/cpukit/libpci/pci_find.c b/cpukit/libpci/pci_find.c
index a2575b7fed..42575a6a41 100644
--- a/cpukit/libpci/pci_find.c
+++ b/cpukit/libpci/pci_find.c
@@ -21,8 +21,8 @@ static int compare_dev_id(pci_dev_t pcidev, void *arg)
 	struct compare_info *info = arg;
 	uint16_t vid, did;
 
-	pci_cfg_r16(pcidev, PCI_VENDOR_ID, &vid);
-	pci_cfg_r16(pcidev, PCI_DEVICE_ID, &did);
+	pci_cfg_r16(pcidev, PCIR_VENDOR, &vid);
+	pci_cfg_r16(pcidev, PCIR_DEVICE, &did);
 	if ((vid != info->vendor) || (did != info->device))
 		return 0;
 	if (info->index-- == 0)
diff --git a/cpukit/libpci/pci_for_each.c b/cpukit/libpci/pci_for_each.c
index 88e4ac3935..9c54af2040 100644
--- a/cpukit/libpci/pci_for_each.c
+++ b/cpukit/libpci/pci_for_each.c
@@ -28,11 +28,11 @@ int pci_for_each(int (*func)(pci_dev_t, void*), void *arg)
 	pci_dev_t pcidev;
 
 	for (bus = 0; bus < maxbus ; bus++) {
-		for (dev = 0; dev < PCI_MAX_DEVICES; dev++) {
+		for (dev = 0; dev <= PCI_SLOTMAX; dev++) {
 			pcidev = PCI_DEV(bus, dev, 0);
 
-			for (fun = 0; fun < PCI_MAX_FUNCTIONS; fun++, pcidev++) {
-				fail = pci_cfg_r32(pcidev, PCI_VENDOR_ID, &id);
+			for (fun = 0; fun <= PCI_FUNCMAX; fun++, pcidev++) {
+				fail = pci_cfg_r32(pcidev, PCIR_VENDOR, &id);
 				if (fail || (0xffffffff == id) || (0 == id)) {
 					if (fun == 0)
 						break;
@@ -48,9 +48,9 @@ int pci_for_each(int (*func)(pci_dev_t, void*), void *arg)
 
 				/* Stop if not a multi-function device */
 				if (fun == 0) {
-					pci_cfg_r8(pcidev, PCI_HEADER_TYPE,
+					pci_cfg_r8(pcidev, PCIR_HDRTYPE,
 							&hd);
-					if ((hd & PCI_MULTI_FUNCTION) == 0)
+					if ((hd & PCIM_MFDEV) == 0)
 						break;
 				}
 			}
diff --git a/cpukit/libpci/pci_irq.c b/cpukit/libpci/pci_irq.c
index 2f4d332dc9..9c8fe0c62e 100644
--- a/cpukit/libpci/pci_irq.c
+++ b/cpukit/libpci/pci_irq.c
@@ -14,6 +14,6 @@
 int pci_dev_irq(pci_dev_t dev)
 {
 	uint8_t irq_line;
-	pci_cfg_r8(dev, PCI_INTERRUPT_LINE, &irq_line);
+	pci_cfg_r8(dev, PCIR_INTLINE, &irq_line);
 	return irq_line;
 }
diff --git a/cpukit/libpci/pci_print.c b/cpukit/libpci/pci_print.c
index 82baba91dc..fe9c6c41f2 100644
--- a/cpukit/libpci/pci_print.c
+++ b/cpukit/libpci/pci_print.c
@@ -31,26 +31,26 @@ void pci_print_dev(pci_dev_t dev)
 	maxbars = 6;
 	romadrs = 0x30;
 	str = "";
-	PCI_CFG_R32(dev, PCI_CLASS_REVISION, &tmp);
+	PCI_CFG_R32(dev, PCIR_REVID, &tmp);
 	tmp >>= 16;
-	if (tmp == PCI_CLASS_BRIDGE_PCI) {
+	if (tmp == PCID_PCI2PCI_BRIDGE) {
 		maxbars = 2;
 		romadrs = 0x38;
 		str = "(BRIDGE)";
 	}
 
-	PCI_CFG_R32(dev, PCI_VENDOR_ID, &id);
+	PCI_CFG_R32(dev, PCIR_VENDOR, &id);
 	printf("\nBus %x Slot %x function: %x [0x%x] %s\n",
 		PCI_DEV_EXPAND(dev), dev, str);
 	printf("\tVendor id: 0x%lx, device id: 0x%lx\n",
 		id & 0xffff, id >> 16);
 	if (maxbars == 2) {
-		PCI_CFG_R32(dev, PCI_PRIMARY_BUS, &tmp);
+		PCI_CFG_R32(dev, PCIR_PRIBUS_1, &tmp);
 		printf("\tPrimary: %lx  Secondary: %lx  Subordinate: %lx\n",
 			tmp & 0xff, (tmp >> 8) & 0xff, (tmp >> 16) & 0xff);
 	}
 
-	PCI_CFG_R16(dev, PCI_INTERRUPT_LINE, &irq);
+	PCI_CFG_R16(dev, PCIR_INTLINE, &irq);
 	irq_pin = irq >> 8;
 	if ((irq_pin > 0) && (irq_pin < 5))
 		printf("\tIRQ INT%c#  LINE: %d\n",
@@ -58,10 +58,10 @@ void pci_print_dev(pci_dev_t dev)
 
 	/* Print standard BARs */
 	for (pos = 0; pos < maxbars; pos++) {
-		PCI_CFG_R32(dev, PCI_BASE_ADDRESS_0 + pos*4, &tmp);
-		PCI_CFG_W32(dev, PCI_BASE_ADDRESS_0 + pos*4, 0xffffffff);
-		PCI_CFG_R32(dev, PCI_BASE_ADDRESS_0 + pos*4, &tmp2);
-		PCI_CFG_W32(dev, PCI_BASE_ADDRESS_0 + pos*4, tmp);
+		PCI_CFG_R32(dev, PCIR_BAR(0) + pos*4, &tmp);
+		PCI_CFG_W32(dev, PCIR_BAR(0) + pos*4, 0xffffffff);
+		PCI_CFG_R32(dev, PCIR_BAR(0) + pos*4, &tmp2);
+		PCI_CFG_W32(dev, PCIR_BAR(0) + pos*4, tmp);
 
 		if (tmp2 != 0 && tmp2 != 0xffffffff && ((tmp2 & 0x1) ||
 		    ((tmp2 & 0x6) == 0))) {
@@ -93,7 +93,7 @@ void pci_print_dev(pci_dev_t dev)
 	PCI_CFG_W32(dev, romadrs, tmp);
 	if (tmp2 & 1) {
 		/* ROM BAR available */
-		tmp2 &= PCI_ROM_ADDRESS_MASK;
+		tmp2 &= PCIM_BIOS_ADDR_MASK;
 		tmp2 = (~tmp2 + 1); /* Size of BAR */
 		if (tmp2 < 0x1000) {
 			str = "B";
@@ -165,19 +165,19 @@ void pci_print(void)
 
     printf("\nPCI devices found and configured:\n");
     for (bus = 0; bus < pci_bus_count(); bus++) {
-        for (slot = 0; slot < PCI_MAX_DEVICES; slot++) {
-            for (func=0; func < PCI_MAX_FUNCTIONS; func++) {
+        for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
+            for (func=0; func <= PCI_FUNCMAX; func++) {
 
                 dev = PCI_DEV(bus, slot, func);
-                fail = PCI_CFG_R32(dev, PCI_VENDOR_ID, &id);
+                fail = PCI_CFG_R32(dev, PCIR_VENDOR, &id);
 
                 if (!fail && id != PCI_INVALID_VENDORDEVICEID && id != 0) {
 	               	pci_print_dev(dev);
 
         	        /* Stop if not a multi-function device */
                 	if (func == 0) {
-	                    PCI_CFG_R8(dev, PCI_HEADER_TYPE, &header);
-        	            if ((header & PCI_MULTI_FUNCTION) == 0)
+	                    PCI_CFG_R8(dev, PCIR_HDRTYPE, &header);
+        	            if ((header & PCIM_MFDEV) == 0)
                 	        break;
 	                }
 		} else if (func == 0)
diff --git a/cpukit/libpci/preinstall.am b/cpukit/libpci/preinstall.am
index c76282593f..b9a8dd0400 100644
--- a/cpukit/libpci/preinstall.am
+++ b/cpukit/libpci/preinstall.am
@@ -64,6 +64,10 @@ $(PROJECT_INCLUDE)/pci/irq.h: pci/irq.h $(PROJECT_INCLUDE)/pci/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/irq.h
 
+$(PROJECT_INCLUDE)/pci/pcireg.h: pci/pcireg.h $(PROJECT_INCLUDE)/pci/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci/pcireg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/pcireg.h
+
 $(PROJECT_INCLUDE)/drvmgr/$(dirstamp):
 	@$(MKDIR_P) $(PROJECT_INCLUDE)/drvmgr
 	@: > $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)