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author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-10-25 12:41:27 -0500 |
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committer | Joel Sherrill <joel@rtems.org> | 2022-11-09 08:14:11 -0600 |
commit | 080dc5d873773f65a6cc89c80f4338fc929796a8 (patch) | |
tree | 9aea4402ab252588430b5ba4f6a2ca58fb6c16c6 /cpukit/include/rtems/confdefs/inittask.h | |
parent | bsps/aarch64: Ensure FPU trap state is consistent (diff) | |
download | rtems-080dc5d873773f65a6cc89c80f4338fc929796a8.tar.bz2 |
cpukit/aarch64: Emulate FPSR for FENV traps
The AArch64 TRM specifies that when FPCR is set to trap floating point
exceptions, the FPSR exception bits are not set. This ensures that FPSR
is updated as FENV expects even if floating point exception traps are
enabled.
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions