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| author | Chris Johns <chrisj@rtems.org> | 2018-01-23 13:23:55 +1100 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2018-02-01 14:59:55 +1100 |
| commit | 05015dc1886d08e9f9f3ed453688c52cebd4cc3f (patch) | |
| tree | 6b1401a111e2548a87aec4aa7e781f209233f9a9 /cpukit/dev/i2c | |
| parent | bsps: Rework cache manager implementation (diff) | |
| download | rtems-05015dc1886d08e9f9f3ed453688c52cebd4cc3f.tar.bz2 | |
Xilinx AXI I2C driver IP race condition causes clock glitch.
Setting the PIRQ to 0 before reading the data produces a short clock pulse.
Moving the write to after reading the data fixes the issue.
Close #3173
Diffstat (limited to 'cpukit/dev/i2c')
| -rw-r--r-- | cpukit/dev/i2c/xilinx-axi-i2c.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/cpukit/dev/i2c/xilinx-axi-i2c.c b/cpukit/dev/i2c/xilinx-axi-i2c.c index 45a1c90c37..11b0658161 100644 --- a/cpukit/dev/i2c/xilinx-axi-i2c.c +++ b/cpukit/dev/i2c/xilinx-axi-i2c.c @@ -512,8 +512,12 @@ xilinx_axi_i2c_read_rx_fifo(xilinx_axi_i2c_bus* bus) */ xilinx_axi_i2c_disable_clear_irq(bus, INT_TX_ERROR); xilinx_axi_i2c_set_cr(bus, CR_TXAK); - xilinx_axi_i2c_write_rx_pirq(bus, 0); xilinx_axi_i2c_read_rx_bytes(bus, level); + /* + * Set the RX PIRQ to 0 after the RX data has been read. There is an + * observed timing issue and glitch if written before. + */ + xilinx_axi_i2c_write_rx_pirq(bus, 0); break; case 0: |