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| author | Zenon <zenon.hans.taneka@dhs.sg> | 2018-11-06 18:50:38 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2018-11-06 18:51:32 -0600 |
| commit | 99d6172f06e11ff7f85f68552f9fea7bd317723f (patch) | |
| tree | 1479591fc564bd02f33440f19484e641dd1cb7a7 /cpukit/dev/i2c/xilinx-axi-i2c.c | |
| parent | psxtmonce01: New test written by Himanshu40 as part of GCI2018 (diff) | |
| download | rtems-99d6172f06e11ff7f85f68552f9fea7bd317723f.tar.bz2 | |
Correct minor spelling and grammar errors
This work was performed as a GCI 2018 task.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/dev/i2c/xilinx-axi-i2c.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/dev/i2c/xilinx-axi-i2c.c b/cpukit/dev/i2c/xilinx-axi-i2c.c index 11b0658161..fc8b4dd92c 100644 --- a/cpukit/dev/i2c/xilinx-axi-i2c.c +++ b/cpukit/dev/i2c/xilinx-axi-i2c.c @@ -502,7 +502,7 @@ xilinx_axi_i2c_read_rx_fifo(xilinx_axi_i2c_bus* bus) * One more byte to be received. This is set up by programming the RX * FIFO programmable depth interrupt register with a value that is 2 * less than the number we need (the register is minus 1). When we have - * one byte left disable the TX error interrupt because setting the NO + * one byte left, disable the TX error interrupt because setting the NO * ACK bit in the command register causes a TX error interrupt. Set the * TXAK bit in the CR to not-acknowledge the next byte received telling * the slave sender the master accepts no more data, then read the |