erc32 bsp supercedes sis

8 files changed, 1476 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc/erc32/start/startsis.s b/c/src/lib/libbsp/sparc/erc32/start/startsis.s
new file mode 100644
index 0000000000..225d70abf0
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/start/startsis.s
@@ -0,0 +1,309 @@
+/*
+ *  startsis.s
+ *
+ *  Start code for the ERC32.
+ *
+ *  This is based on the file srt0.s provided with the binary
+ *  distribution of the SPARC Instruction Simulator (SIS) found
+ *  at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
+ *
+ *  $Id$
+ */
+
+#include <asm.h>
+#include <erc32.h>
+
+/*
+ *  Unexpected trap will halt the processor by forcing it to error state
+ */
+
+#define BAD_TRAP \
+  ta 0; \
+  nop; \
+  nop; \
+  nop;
+
+/*
+ *  Software trap. Treat as BAD_TRAP for the time being...
+ */
+
+#define SOFT_TRAP BAD_TRAP
+
+
+  .seg    "text"
+  PUBLIC(start)
+  .global start
+
+SYM(start):
+start:
+
+/* 
+ *  The trap table has to be the first code in a boot PROM.  But because
+ *  the Memory Configuration comes up thinking we only have 4K of PROM, we
+ *  cannot have a full trap table and still have room left over to 
+ *  reprogram the Memory Configuration register correctly.  This file
+ *  uses an abbreviated trap which has every entry which might be used
+ *  before RTEMS installs its own trap table.
+ */
+
+
+  PUBLIC(trap_table)
+SYM(trap_table):
+
+  RTRAP( 0, SYM(hard_reset) );                   ! 00 reset trap 
+  BAD_TRAP;                                     ! 01 instruction access 
+                                                !    exception
+  BAD_TRAP;                                     ! 02 illegal instruction
+  BAD_TRAP;                                     ! 03 privileged instruction
+  BAD_TRAP;                                     ! 04 fp disabled
+  TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow
+  TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow
+  BAD_TRAP;                                     ! 07 memory address not aligned
+  BAD_TRAP;                                     ! 08 fp exception
+  BAD_TRAP;                                     ! 09 data access exception
+  BAD_TRAP;                                     ! 0A tag overflow
+  BAD_TRAP;                                     ! 0B undefined
+  BAD_TRAP;                                     ! 0C undefined
+  BAD_TRAP;                                     ! 0D undefined
+  BAD_TRAP;                                     ! 0E undefined
+  BAD_TRAP;                                     ! 0F undefined
+  BAD_TRAP;                                     ! 10 undefined
+
+  /* 
+   *  ERC32 defined traps
+   */
+
+  BAD_TRAP;                                     ! 11 masked errors
+  BAD_TRAP;                                     ! 12 external 1
+  BAD_TRAP;                                     ! 13 external 2
+  BAD_TRAP;                                     ! 14 UART A RX/TX
+  BAD_TRAP;                                     ! 15 UART B RX/TX
+  BAD_TRAP;                                     ! 16 correctable memory error
+  BAD_TRAP;                                     ! 17 UART error
+  BAD_TRAP;                                     ! 18 DMA access error
+  BAD_TRAP;                                     ! 19 DMA timeout
+  BAD_TRAP;                                     ! 1A external 3
+  BAD_TRAP;                                     ! 1B external 4
+  BAD_TRAP;                                     ! 1C general purpose timer
+  BAD_TRAP;                                     ! 1D real time clock
+  BAD_TRAP;                                     ! 1E external 5
+  BAD_TRAP;                                     ! 1F watchdog timeout
+
+
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 20 - 23 undefined
+  BAD_TRAP;                                     ! 24 cp_disabled
+            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 25 - 27 undefined
+  BAD_TRAP;                                     ! 28 cp_exception
+            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 29 - 2B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 2C - 2F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 30 - 33 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 34 - 37 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 38 - 3B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 3C - 3F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 40 - 43 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 44 - 47 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 48 - 4B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 4C - 4F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 50 - 53 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 54 - 57 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 58 - 5B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 5C - 5F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 60 - 63 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 64 - 67 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 68 - 6B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 6C - 6F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 70 - 73 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 74 - 77 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 78 - 7B undefined
+
+/* 
+   This is a sad patch to make sure that we know where the
+   MEC timer control register mirror is so we can stop the timers
+   from an external debugger. It is needed because the control
+   register is write-only. Trap 0x7C cannot occure in ERC32...
+
+   We also use this location to store the last location of the
+   usable RAM in order not to overwrite the remote debugger with
+   the RTEMS work-space area.
+
+*/
+
+	.global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED
+
+_rdb_start:
+__ERC32_MEC_Timer_Control_Mirror:
+
+  BAD_TRAP; BAD_TRAP;                           ! 7C - 7D undefined
+
+_CLOCK_SPEED:
+  BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP;       ! 7E - 7F undefined
+
+  /* 
+   *  Software traps
+   *
+   *  NOTE: At the risk of being redundant... this is not a full
+   *        table.  The setjmp on the SPARC requires a window flush trap
+   *        handler and RTEMS will preserve the entries that were
+   *        installed before.
+   */
+
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;              ! 80 - 82
+  TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap
+
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 84 - 87
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 88 - 8B
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 8C - 8F
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 90 - 93
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 94 - 97
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 98 - 9B
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 9C - 9F
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A0 - A3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A4 - A7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A8 - AB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! AC - AF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B0 - B3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B4 - B7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B8 - BB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! BC - BF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C0 - C3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C4 - C7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C8 - CB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! CC - CF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D0 - D3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D4 - D7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D8 - DB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! DC - DF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E0 - E3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E4 - E7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E8 - EB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! EC - EF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F0 - F3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F4 - F7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F8 - FB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! FC - FF
+
+/*
+ *  This is the hard reset code.
+ */
+
+#define PSR_INIT   0x10c0       /* Disable traps, set s and ps */
+#define WIM_INIT   2
+#define STACK_SIZE 16 * 1024
+
+        PUBLIC(hard_reset)
+SYM(hard_reset):
+
+        set     _trap_table, %g1           ! Initialize TBR
+        mov     %g1, %tbr
+
+	set	(SYM(rdb_start)), %g6	   ! End of work-space area
+	st	%sp, [%g6]
+
+
+/* Check if MEC is initialised. If not, this means that we are
+   running on the simulator. Initiate some of the parameters
+   that are done by the boot-prom otherwise.
+*/
+
+        set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
+	ld	[%g3], %g2		
+	set	0xfe080000, %g1
+	andcc	%g1, %g2, %g0
+	bne	1f
+	set	0x00101000, %g1		! 2M ROM, 4M RAM
+                                         ! set the Memory Configuration
+        st     %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
+        
+	set	SYM(RAM_END), %sp	   ! End of work-space area
+	st	%sp, [%g6]
+
+	set	_CLOCK_SPEED, %g6	! Use 14 MHz in simulator
+	set	14, %g1
+	st	%g1, [%g6]
+
+/* Common initialisation */
+1:
+        set     WIM_INIT, %g1           ! Initialize WIM
+        mov     %g1, %wim               
+
+        set     PSR_INIT, %g1
+        wr      %g1, 0x20, %psr         ! enable traps
+
+        nop
+        nop
+        nop
+
+        sethi   %hi(stack_space + STACK_SIZE), %g1
+        or      %g1,%lo(stack_space + STACK_SIZE),%g1 
+                                        ! g1 = top of stack
+        mov     %g1, %sp                ! Set stack pointer
+        mov     %sp, %fp                ! Set frame pointer
+        nop
+
+        /*
+         *  Copy the initialized data to RAM
+         *
+         *  FROM:   _endtext 
+         *  TO:     _data_start 
+         *  LENGTH: (__bss_start - _data_start) bytes
+         */
+ 
+
+        sethi %hi(_endtext),%g2
+        or    %g2,%lo(_endtext),%g2     ! g2 = start of initialized data in ROM
+
+        sethi %hi(_data_start),%g3
+        or    %g3,%lo(_data_start),%g3  ! g3 = start of initialized data in RAM
+
+        sethi %hi(__bss_start),%g4
+        or    %g4,%lo(__bss_start),%g4  ! g4 = end of initialized data in RAM
+
+	cmp   %g2, %g3
+	be    1f
+	nop
+
+copy_data:
+        ldd   [ %g2 ], %g6
+        std   %g6 , [ %g3 ]             ! copy this double word
+        add   %g3, 8, %g3               ! bump the destination pointer
+        add   %g2, 8, %g2               ! bump the source pointer
+        cmp   %g3, %g4                  ! Is the pointer past the end of dest?
+        bl    copy_data
+        nop
+
+        /* clear the bss */
+1:
+
+        sethi %hi(_edata),%g2
+        or    %g2,%lo(_edata),%g2       ! g2 = start of bss
+        sethi %hi(_end),%g3
+        or    %g3,%lo(_end),%g3         ! g3 = end of bss
+        mov   %g0,%g1                   ! so std has two zeros
+zerobss:
+        std    %g0,[%g2]
+        add    %g2,8,%g2
+        cmp    %g2,%g3
+        bleu,a zerobss
+        nop
+
+        mov     %0, %o2                 ! environ
+        mov     %0, %o1                 ! argv
+        mov     %0, %o0                 ! argc
+        call    SYM(main)
+        sub     %sp, 0x60, %sp          ! room for main to save args
+        nop
+
+        PUBLIC(BSP_fatal_return)
+SYM(BSP_fatal_return):
+        ta      0                       ! Halt if _main returns ...
+        nop
+
+        /*
+         *  There does not seem to be a way to get this aligned AND
+         *  in the BSS.
+         */
+ 
+        .align  32
+        .comm   stack_space, STACK_SIZE
+
+/* end of file */
diff --git a/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s b/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s
new file mode 100644
index 0000000000..225d70abf0
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s
@@ -0,0 +1,309 @@
+/*
+ *  startsis.s
+ *
+ *  Start code for the ERC32.
+ *
+ *  This is based on the file srt0.s provided with the binary
+ *  distribution of the SPARC Instruction Simulator (SIS) found
+ *  at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
+ *
+ *  $Id$
+ */
+
+#include <asm.h>
+#include <erc32.h>
+
+/*
+ *  Unexpected trap will halt the processor by forcing it to error state
+ */
+
+#define BAD_TRAP \
+  ta 0; \
+  nop; \
+  nop; \
+  nop;
+
+/*
+ *  Software trap. Treat as BAD_TRAP for the time being...
+ */
+
+#define SOFT_TRAP BAD_TRAP
+
+
+  .seg    "text"
+  PUBLIC(start)
+  .global start
+
+SYM(start):
+start:
+
+/* 
+ *  The trap table has to be the first code in a boot PROM.  But because
+ *  the Memory Configuration comes up thinking we only have 4K of PROM, we
+ *  cannot have a full trap table and still have room left over to 
+ *  reprogram the Memory Configuration register correctly.  This file
+ *  uses an abbreviated trap which has every entry which might be used
+ *  before RTEMS installs its own trap table.
+ */
+
+
+  PUBLIC(trap_table)
+SYM(trap_table):
+
+  RTRAP( 0, SYM(hard_reset) );                   ! 00 reset trap 
+  BAD_TRAP;                                     ! 01 instruction access 
+                                                !    exception
+  BAD_TRAP;                                     ! 02 illegal instruction
+  BAD_TRAP;                                     ! 03 privileged instruction
+  BAD_TRAP;                                     ! 04 fp disabled
+  TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow
+  TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow
+  BAD_TRAP;                                     ! 07 memory address not aligned
+  BAD_TRAP;                                     ! 08 fp exception
+  BAD_TRAP;                                     ! 09 data access exception
+  BAD_TRAP;                                     ! 0A tag overflow
+  BAD_TRAP;                                     ! 0B undefined
+  BAD_TRAP;                                     ! 0C undefined
+  BAD_TRAP;                                     ! 0D undefined
+  BAD_TRAP;                                     ! 0E undefined
+  BAD_TRAP;                                     ! 0F undefined
+  BAD_TRAP;                                     ! 10 undefined
+
+  /* 
+   *  ERC32 defined traps
+   */
+
+  BAD_TRAP;                                     ! 11 masked errors
+  BAD_TRAP;                                     ! 12 external 1
+  BAD_TRAP;                                     ! 13 external 2
+  BAD_TRAP;                                     ! 14 UART A RX/TX
+  BAD_TRAP;                                     ! 15 UART B RX/TX
+  BAD_TRAP;                                     ! 16 correctable memory error
+  BAD_TRAP;                                     ! 17 UART error
+  BAD_TRAP;                                     ! 18 DMA access error
+  BAD_TRAP;                                     ! 19 DMA timeout
+  BAD_TRAP;                                     ! 1A external 3
+  BAD_TRAP;                                     ! 1B external 4
+  BAD_TRAP;                                     ! 1C general purpose timer
+  BAD_TRAP;                                     ! 1D real time clock
+  BAD_TRAP;                                     ! 1E external 5
+  BAD_TRAP;                                     ! 1F watchdog timeout
+
+
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 20 - 23 undefined
+  BAD_TRAP;                                     ! 24 cp_disabled
+            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 25 - 27 undefined
+  BAD_TRAP;                                     ! 28 cp_exception
+            BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 29 - 2B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 2C - 2F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 30 - 33 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 34 - 37 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 38 - 3B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 3C - 3F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 40 - 43 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 44 - 47 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 48 - 4B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 4C - 4F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 50 - 53 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 54 - 57 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 58 - 5B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 5C - 5F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 60 - 63 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 64 - 67 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 68 - 6B undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 6C - 6F undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 70 - 73 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 74 - 77 undefined
+  BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP;       ! 78 - 7B undefined
+
+/* 
+   This is a sad patch to make sure that we know where the
+   MEC timer control register mirror is so we can stop the timers
+   from an external debugger. It is needed because the control
+   register is write-only. Trap 0x7C cannot occure in ERC32...
+
+   We also use this location to store the last location of the
+   usable RAM in order not to overwrite the remote debugger with
+   the RTEMS work-space area.
+
+*/
+
+	.global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED
+
+_rdb_start:
+__ERC32_MEC_Timer_Control_Mirror:
+
+  BAD_TRAP; BAD_TRAP;                           ! 7C - 7D undefined
+
+_CLOCK_SPEED:
+  BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP;       ! 7E - 7F undefined
+
+  /* 
+   *  Software traps
+   *
+   *  NOTE: At the risk of being redundant... this is not a full
+   *        table.  The setjmp on the SPARC requires a window flush trap
+   *        handler and RTEMS will preserve the entries that were
+   *        installed before.
+   */
+
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;              ! 80 - 82
+  TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap
+
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 84 - 87
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 88 - 8B
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 8C - 8F
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 90 - 93
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 94 - 97
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 98 - 9B
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! 9C - 9F
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A0 - A3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A4 - A7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! A8 - AB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! AC - AF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B0 - B3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B4 - B7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! B8 - BB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! BC - BF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C0 - C3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C4 - C7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! C8 - CB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! CC - CF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D0 - D3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D4 - D7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! D8 - DB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! DC - DF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E0 - E3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E4 - E7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! E8 - EB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! EC - EF
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F0 - F3
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F4 - F7
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! F8 - FB
+  SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP;   ! FC - FF
+
+/*
+ *  This is the hard reset code.
+ */
+
+#define PSR_INIT   0x10c0       /* Disable traps, set s and ps */
+#define WIM_INIT   2
+#define STACK_SIZE 16 * 1024
+
+        PUBLIC(hard_reset)
+SYM(hard_reset):
+
+        set     _trap_table, %g1           ! Initialize TBR
+        mov     %g1, %tbr
+
+	set	(SYM(rdb_start)), %g6	   ! End of work-space area
+	st	%sp, [%g6]
+
+
+/* Check if MEC is initialised. If not, this means that we are
+   running on the simulator. Initiate some of the parameters
+   that are done by the boot-prom otherwise.
+*/
+
+        set     SYM(ERC32_MEC), %g3  ! g3 = base address of peripherals
+	ld	[%g3], %g2		
+	set	0xfe080000, %g1
+	andcc	%g1, %g2, %g0
+	bne	1f
+	set	0x00101000, %g1		! 2M ROM, 4M RAM
+                                         ! set the Memory Configuration
+        st     %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
+        
+	set	SYM(RAM_END), %sp	   ! End of work-space area
+	st	%sp, [%g6]
+
+	set	_CLOCK_SPEED, %g6	! Use 14 MHz in simulator
+	set	14, %g1
+	st	%g1, [%g6]
+
+/* Common initialisation */
+1:
+        set     WIM_INIT, %g1           ! Initialize WIM
+        mov     %g1, %wim               
+
+        set     PSR_INIT, %g1
+        wr      %g1, 0x20, %psr         ! enable traps
+
+        nop
+        nop
+        nop
+
+        sethi   %hi(stack_space + STACK_SIZE), %g1
+        or      %g1,%lo(stack_space + STACK_SIZE),%g1 
+                                        ! g1 = top of stack
+        mov     %g1, %sp                ! Set stack pointer
+        mov     %sp, %fp                ! Set frame pointer
+        nop
+
+        /*
+         *  Copy the initialized data to RAM
+         *
+         *  FROM:   _endtext 
+         *  TO:     _data_start 
+         *  LENGTH: (__bss_start - _data_start) bytes
+         */
+ 
+
+        sethi %hi(_endtext),%g2
+        or    %g2,%lo(_endtext),%g2     ! g2 = start of initialized data in ROM
+
+        sethi %hi(_data_start),%g3
+        or    %g3,%lo(_data_start),%g3  ! g3 = start of initialized data in RAM
+
+        sethi %hi(__bss_start),%g4
+        or    %g4,%lo(__bss_start),%g4  ! g4 = end of initialized data in RAM
+
+	cmp   %g2, %g3
+	be    1f
+	nop
+
+copy_data:
+        ldd   [ %g2 ], %g6
+        std   %g6 , [ %g3 ]             ! copy this double word
+        add   %g3, 8, %g3               ! bump the destination pointer
+        add   %g2, 8, %g2               ! bump the source pointer
+        cmp   %g3, %g4                  ! Is the pointer past the end of dest?
+        bl    copy_data
+        nop
+
+        /* clear the bss */
+1:
+
+        sethi %hi(_edata),%g2
+        or    %g2,%lo(_edata),%g2       ! g2 = start of bss
+        sethi %hi(_end),%g3
+        or    %g3,%lo(_end),%g3         ! g3 = end of bss
+        mov   %g0,%g1                   ! so std has two zeros
+zerobss:
+        std    %g0,[%g2]
+        add    %g2,8,%g2
+        cmp    %g2,%g3
+        bleu,a zerobss
+        nop
+
+        mov     %0, %o2                 ! environ
+        mov     %0, %o1                 ! argv
+        mov     %0, %o0                 ! argc
+        call    SYM(main)
+        sub     %sp, 0x60, %sp          ! room for main to save args
+        nop
+
+        PUBLIC(BSP_fatal_return)
+SYM(BSP_fatal_return):
+        ta      0                       ! Halt if _main returns ...
+        nop
+
+        /*
+         *  There does not seem to be a way to get this aligned AND
+         *  in the BSS.
+         */
+ 
+        .align  32
+        .comm   stack_space, STACK_SIZE
+
+/* end of file */
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/bspclean.c b/c/src/lib/libbsp/sparc/erc32/startup/bspclean.c
new file mode 100644
index 0000000000..2e34ced28e
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startup/bspclean.c
@@ -0,0 +1,37 @@
+/*  bspclean.c
+ *
+ *  This file contains cleanup code executed when the application exits.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+
+/*
+ * The app has "exited" (rtems_shutdown_executive returns control to main)
+ */
+
+void bsp_cleanup( void )
+{
+    /*
+     * "halt" by trapping to the simulator command line.
+     */
+
+
+  asm volatile( "ta 0" );
+}
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/bspstart.c b/c/src/lib/libbsp/sparc/erc32/startup/bspstart.c
new file mode 100644
index 0000000000..8a885e69de
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startup/bspstart.c
@@ -0,0 +1,373 @@
+/*  bspstart.c
+ *
+ *  This set of routines starts the application.  It includes application,
+ *  board, and monitor specific initialization and configuration.
+ *  The generic CPU dependent initialization has been performed
+ *  before any of these are invoked.
+ *
+ *  Called by RTEMS::RTEMS constructor in rtems-ctor.cc
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+
+#include <libcsupport.h>
+
+#include <string.h>
+#include <fcntl.h>
+
+#ifdef STACK_CHECKER_ON
+#include <stackchk.h>
+#endif
+
+/*
+ *  The original table from the application and our copy of it with
+ *  some changes.
+ */
+ 
+extern rtems_configuration_table  Configuration;
+rtems_configuration_table         BSP_Configuration;
+
+rtems_cpu_table   Cpu_table;
+rtems_unsigned32  bsp_isr_level;
+
+/*
+ *  Tells us where to put the workspace in case remote debugger is present.
+ */
+
+extern rtems_unsigned32  rdb_start;
+
+/*
+ * Amount to increment itimer by each pass
+ * It is a variable instead of a #define to allow the 'looptest'
+ * script to bump it without recompiling rtems
+ *
+ *  NOTE:  This is based on the PA-RISC simulator.  I don't know if we
+ *         can actually pull this trick on the SPARC simulator.
+ */
+
+rtems_unsigned32 CPU_SPARC_CLICKS_PER_TICK;
+
+#if SIMSPARC_FAST_IDLE
+
+/*
+ * Many of the tests are very slow on the simulator because they have
+ * have 5 second delays hardwired in.
+ *
+ * Try to speed those tests up by speeding up the clock when in the idle task.
+ *
+ *  NOTE:  At the current setting, 5 second delays in the tests take 
+ *         approximately 5 seconds of wall time. 
+ */
+
+rtems_extension
+fast_idle_switch_hook(rtems_tcb *current_task,
+                      rtems_tcb *heir_task)
+{
+    static rtems_unsigned32 normal_clock = ~0;
+    static rtems_unsigned32 fast_clock;
+
+    /* init our params on first call */
+    if (normal_clock == ~0)
+    {
+        normal_clock = CPU_SPARC_CLICKS_PER_TICK;
+        fast_clock = CPU_SPARC_CLICKS_PER_TICK / 0x08;
+        if (fast_clock == 0)    /* handle pathological case */
+            fast_clock++;
+    }
+
+    /*
+     * Run the clock faster when idle is in place.
+     */
+
+    if (heir_task == _Thread_Idle)
+        CPU_SPARC_CLICKS_PER_TICK = fast_clock;
+    else if (current_task == _Thread_Idle)
+        CPU_SPARC_CLICKS_PER_TICK = normal_clock;
+}
+
+#endif
+
+/*
+ *  bsp_libc_init
+ *
+ *  Initialize whatever libc we are using called from bsp_postdriver_hook.
+ */
+
+void bsp_libc_init(void)
+{
+  extern int end;
+  rtems_unsigned32 heap_start;
+  rtems_unsigned32 heap_size;
+
+  heap_start = (rtems_unsigned32) &end;
+  if (heap_start & (CPU_ALIGNMENT-1))
+    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+
+  heap_size = BSP_Configuration.work_space_start - (void *)&end;
+  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
+
+  RTEMS_Malloc_Initialize((void *) heap_start, heap_size, 0);
+
+  /*
+   *  Init the RTEMS libio facility to provide UNIX-like system
+   *  calls for use by newlib (ie: provide __rtems_open, __rtems_close, etc)
+   *  Uses malloc() to get area for the iops, so must be after malloc init
+   */
+ 
+  rtems_libio_init();
+ 
+  /*
+   * Set up for the libc handling.
+   */
+ 
+  if (BSP_Configuration.ticks_per_timeslice > 0)
+    libc_init(1);                /* reentrant if possible */
+  else
+    libc_init(0);                /* non-reentrant */
+
+}
+
+
+/*
+ *  bsp_pretasking_hook
+ *
+ *  BSP pretasking hook.  Called just before drivers are initialized.
+ *  Used to setup libc and install any BSP extensions.
+ */
+
+void bsp_pretasking_hook(void)
+{
+  bsp_libc_init();
+
+#if SIMSPARC_FAST_IDLE
+  /*
+   *  Install the fast idle task switch extension
+   *
+   *  On MP systems, might not want to do this; it confuses at least
+   *  one test (mp06) on the PA-RISC simulator
+   */
+
+#if 0
+  if (BSP_Configuration.User_multiprocessing_table == 0)
+#endif
+  {
+    rtems_extensions_table  fast_idle_extension;
+    rtems_id                extension_id;
+    rtems_status_code       rc;
+
+    memset(&fast_idle_extension, 0, sizeof(fast_idle_extension));
+
+    fast_idle_extension.thread_switch  = fast_idle_switch_hook;
+
+    rc = rtems_extension_create(
+      rtems_build_name('F', 'D', 'L', 'E'),
+      &fast_idle_extension, 
+      &extension_id
+    );
+    if (rc != RTEMS_SUCCESSFUL)
+      rtems_fatal_error_occurred(rc);
+  }
+#endif
+
+
+#ifdef STACK_CHECKER_ON
+  /*
+   *  Initialize the stack bounds checker
+   *  We can either turn it on here or from the app.
+   */
+
+  Stack_check_Initialize();
+#endif
+
+#ifdef RTEMS_DEBUG
+  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
+#endif
+
+}
+
+/*
+ *  bsp_postdriver_hook
+ *
+ *  After drivers are setup, register some "filenames"
+ *  and open stdin, stdout, stderr files
+ *
+ *  Newlib will automatically associate the files with these
+ *  (it hardcodes the numbers)
+ */
+ 
+void
+bsp_postdriver_hook(void)
+{
+  int stdin_fd, stdout_fd, stderr_fd;
+  int error_code;
+ 
+  error_code = 'S' << 24 | 'T' << 16;
+ 
+  if ((stdin_fd = __rtems_open("/dev/console", O_RDONLY, 0)) == -1)
+    rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' );
+ 
+  if ((stdout_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
+    rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' );
+ 
+  if ((stderr_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
+    rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' );
+ 
+  if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2))
+    rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' );
+ 
+  if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2))
+    rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' );
+}
+
+/*
+ *  bsp_start
+ *
+ *  This routine does the bulk of the system initialization.
+ */
+
+void bsp_start( void )
+{
+  unsigned char *work_space_start;
+
+  /* Check if MEc is initialised */
+
+  if (!(ERC32_MEC.Control & 0xfe080000)) {
+
+  /*
+   *  DISABLE THE HARDWARE WATCHDOG!!!
+   */
+
+    ERC32_MEC.Watchdog_Trap_Door_Set = 0;          /* value is irrelevant */
+
+  /*
+   *  Reduce the number of wait states to 0 for all memory areas.
+   */
+
+    ERC32_MEC.Wait_State_Configuration = 0; 
+
+  }
+  
+  /*
+   * Set up our hooks
+   * Make sure libc_init is done before drivers initialized so that
+   * they can use atexit()
+   */
+
+  Cpu_table.pretasking_hook = bsp_pretasking_hook;    /* init libc, etc. */
+
+  Cpu_table.predriver_hook = NULL; /* bsp_spurious_initialize;*/
+
+  Cpu_table.postdriver_hook = bsp_postdriver_hook;
+
+  Cpu_table.idle_task = NULL;  /* do not override system IDLE task */
+
+  /*
+   *  SIS does zero out memory BUT only when IT begins execution.  Thus
+   *  if we want to have a clean slate in the workspace each time we
+   *  begin execution of OUR application, then we must zero the workspace.
+   */
+
+  Cpu_table.do_zero_of_workspace = TRUE;
+
+  /*
+   *  This should be enough interrupt stack.
+   */
+
+  Cpu_table.interrupt_stack_size = (12 * 1024);
+
+  /*
+   *  SIS does not support MP configurations so there is really no way
+   *  to check this out.
+   */
+
+  Cpu_table.extra_mpci_receive_server_stack = 0;
+
+  /*
+   *  Copy the table and allocate memory for the RTEMS Workspace
+   */
+
+  BSP_Configuration = Configuration;
+
+  work_space_start = 
+    (unsigned char *)rdb_start - BSP_Configuration.work_space_size;
+
+  if ( work_space_start <= (unsigned char *)&end ) {
+    DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
+    BSP_fatal_return();
+  }
+
+  BSP_Configuration.work_space_start = work_space_start;
+
+  /*
+   * Add 1 region for RTEMS Malloc
+   */
+
+  BSP_Configuration.RTEMS_api_configuration->maximum_regions++;
+
+#ifdef RTEMS_NEWLIB
+  /*
+   * Add 1 extension for newlib libc
+   */
+
+  BSP_Configuration.maximum_extensions++;
+#endif
+
+#ifdef STACK_CHECKER_ON
+  /*
+   * Add 1 extension for stack checker
+   */
+
+  BSP_Configuration.maximum_extensions++;
+#endif
+
+#if SIMSPARC_FAST_IDLE
+  /*
+   * Add 1 extension for fast idle
+   */
+
+  BSP_Configuration.maximum_extensions++;
+#endif
+
+  /*
+   * Add 1 extension for MPCI_fatal
+   */
+
+  if (BSP_Configuration.User_multiprocessing_table)
+    BSP_Configuration.maximum_extensions++;
+
+  /*
+   * Set the "clicks per tick" for the simulator
+   *  used by XXX/clock/clock.c to schedule interrupts
+   */
+
+  CPU_SPARC_CLICKS_PER_TICK = BSP_Configuration.microseconds_per_tick;
+
+  /*
+   *  Initialize RTEMS. main() will finish it up and start multitasking.
+   */
+
+  rtems_libio_config( &BSP_Configuration, BSP_LIBIO_MAX_FDS );
+ 
+  bsp_isr_level = rtems_initialize_executive_early(
+     &BSP_Configuration,
+     &Cpu_table
+  );
+}
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/linkcmds b/c/src/lib/libbsp/sparc/erc32/startup/linkcmds
new file mode 100644
index 0000000000..8b68dd2c05
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startup/linkcmds
@@ -0,0 +1,132 @@
+/*  linkcmds
+ *
+ *  $Id$
+ */
+
+OUTPUT_ARCH(sparc)
+__DYNAMIC  =  0;
+
+/*
+ * The memory map looks like this:
+ * +--------------------+ <- low memory
+ * | .text              |
+ * |        etext       |
+ * |        ctor list   | the ctor and dtor lists are for
+ * |        dtor list   | C++ support
+ * |        _endtext    |
+ * +--------------------+
+ * | .data              | initialized data goes here
+ * |        _sdata      |
+ * |        _edata      |
+ * +--------------------+
+ * | .bss               |
+ * |        __bss_start | start of bss, cleared by crt0
+ * |        _end        | start of heap, used by sbrk()
+ * +--------------------+
+ * |    heap space      |
+ * |        _ENDHEAP    |
+ * |    stack space     | 
+ * |        __stack     | top of stack
+ * +--------------------+ <- high memory
+ */
+
+
+/*
+ * User modifiable values:
+ *
+ * _CLOCK_SPEED               in Mhz (used to program the counter/timers)
+ *
+ * _PROM_SIZE                 size of PROM (permissible values are 4K, 8K, 16K
+ *                               32K, 64K, 128K, 256K, and 512K)
+ * _RAM_SIZE                  size of RAM (permissible values are 256K, 512K,
+ *                               1MB, 2Mb, 4Mb, 8Mb, 16Mb, and 32Mb)
+ *
+ *  MAKE SURE THESE MATCH THE MEMORY DESCRIPTION SECTION!!!
+ */
+
+/*
+_CLOCK_SPEED = 10;
+*/
+
+_PROM_SIZE = 512K;
+_RAM_SIZE = 2M;
+
+_RAM_START = 0x02000000;
+_RAM_END = _RAM_START + _RAM_SIZE;
+
+_PROM_START = 0x00000000;
+_PROM_END = _PROM_START + _PROM_SIZE;
+
+/*
+ *  Base address of the on-CPU peripherals
+ */
+
+_ERC32_MEC = 0x01f80000;
+
+MEMORY
+{
+  rom     : ORIGIN = 0x00000000, LENGTH = 512K
+  ram     : ORIGIN = 0x02000000, LENGTH = 2M
+}
+
+/*
+ * stick everything in ram (of course)
+ */
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    text_start = .;
+    _text_start = .;
+    *(.text)
+    etext = ALIGN(0x10);
+    _etext = .;
+    __CTOR_LIST__ = .;
+    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+    *(.ctors)
+    LONG(0)
+    __CTOR_END__ = .;
+    __DTOR_LIST__ = .;
+    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+    *(.dtors)
+    LONG(0)
+    __DTOR_END__ = .;
+    *(.lit)
+    *(.shdata)
+    _endtext = .;
+  } > ram
+  .data :
+  {
+    data_start = .;
+    _data_start = .;
+    _sdata = . ;
+    *(.data)
+    CONSTRUCTORS
+    edata = ALIGN(0x10);
+    _edata = .;
+  } > ram
+  .shbss :
+  {
+    *(.shbss)
+  } > ram
+  .bss :
+  {
+    __bss_start = ALIGN(0x8);
+    _bss_start = .;
+    bss_start = .;
+    *(.bss)
+    *(COMMON)
+    end = .;
+    _end = ALIGN(0x8);
+    __end = ALIGN(0x8);
+  } > ram
+  .stab . (NOLOAD) :
+  {
+    [ .stab ]
+  }
+  .stabstr . (NOLOAD) :
+  {
+    [ .stabstr ]
+  }
+}
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/setvec.c b/c/src/lib/libbsp/sparc/erc32/startup/setvec.c
new file mode 100644
index 0000000000..12b72f3139
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startup/setvec.c
@@ -0,0 +1,63 @@
+/*  set_vector
+ *
+ *  This routine installs an interrupt vector on the SPARC simulator.
+ *
+ *  INPUT PARAMETERS:
+ *    handler - interrupt handler entry point
+ *    vector  - vector number
+ *    type    - 0 indicates raw hardware connect
+ *              1 indicates RTEMS interrupt connect
+ *
+ *  OUTPUT PARAMETERS:  NONE
+ *
+ *  RETURNS:
+ *    address of previous interrupt handler
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+
+rtems_isr_entry set_vector(                   /* returns old vector */
+  rtems_isr_entry     handler,                /* isr routine        */
+  rtems_vector_number vector,                 /* vector number      */
+  int                 type                    /* RTEMS or RAW intr  */
+)
+{
+  rtems_isr_entry previous_isr;
+  unsigned32      real_trap;
+  unsigned32      source;
+
+  if ( type )
+    rtems_interrupt_catch( handler, vector, &previous_isr );
+  else 
+    _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
+
+  real_trap = SPARC_REAL_TRAP_NUMBER( vector );
+
+  if ( ERC32_Is_MEC_Trap( real_trap ) ) {
+    
+    source = ERC32_TRAP_SOURCE( real_trap );
+
+    ERC32_Clear_interrupt( source );
+    ERC32_Unmask_interrupt( source );
+  }
+
+  return previous_isr;
+}
+
diff --git a/c/src/lib/libbsp/sparc/erc32/startup/spurious.c b/c/src/lib/libbsp/sparc/erc32/startup/spurious.c
new file mode 100644
index 0000000000..fa1a704079
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/startup/spurious.c
@@ -0,0 +1,164 @@
+/*
+ *  ERC32 Spurious Trap Handler
+ *
+ *  This is just enough of a trap handler to let us know what 
+ *  the likely source of the trap was.
+ *
+ *  Developed as part of the port of RTEMS to the ERC32 implementation 
+ *  of the SPARC by On-Line Applications Research Corporation (OAR) 
+ *  under contract to the European Space Agency (ESA).
+ *
+ *  COPYRIGHT (c) 1995. European Space Agency.
+ *
+ *  This terms of the RTEMS license apply to this file.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+
+#include <string.h>
+
+static const char digits[16] = "0123456789abcdef";
+
+/*
+ *  bsp_spurious_handler
+ *
+ *  Print a message on the debug console and then die
+ */
+
+rtems_isr bsp_spurious_handler(
+   rtems_vector_number trap
+)
+{
+  char line[ 80 ];
+  int length;
+  rtems_unsigned32 real_trap;
+
+  DEBUG_puts( "Spurious Trap" );
+
+  real_trap = SPARC_REAL_TRAP_NUMBER(trap);
+
+  switch (real_trap) {
+
+    /*
+     *  First the ones defined by the basic architecture
+     */
+
+    case 0x00: 
+      DEBUG_puts( "reset" );
+      break;
+    case 0x01: 
+      DEBUG_puts( "instruction access exception" );
+      break;
+    case 0x02: 
+      DEBUG_puts( "illegal instruction" );
+      break;
+    case 0x03: 
+      DEBUG_puts( "privileged instruction" );
+      break;
+    case 0x04: 
+      DEBUG_puts( "fp disabled" );
+      break;
+    case 0x07: 
+      DEBUG_puts( "memory address not aligned" );
+      break;
+    case 0x08: 
+      DEBUG_puts( "fp exception" );
+      break;
+    case 0x09: 
+      DEBUG_puts( "data access exception" );
+      break;
+    case 0x0A: 
+      DEBUG_puts( "tag overflow" );
+      break;
+
+    /*
+     *  Then the ones defined by the ERC32 in particular
+     */
+
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ):
+      DEBUG_puts( "ERC32_INTERRUPT_MASKED_ERRORS" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_1 ):
+      DEBUG_puts( "ERC32_INTERRUPT_EXTERNAL_1" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_2 ):
+      DEBUG_puts( "ERC32_INTERRUPT_EXTERNAL_2" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_A_RX_TX ):
+      DEBUG_puts( "ERC32_INTERRUPT_UART_A_RX_TX" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_B_RX_TX ):
+      DEBUG_puts( "ERC32_INTERRUPT_UART_A_RX_TX" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR ):
+      DEBUG_puts( "ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_ERROR ):
+      DEBUG_puts( "ERC32_INTERRUPT_UART_ERROR" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_ACCESS_ERROR ):
+      DEBUG_puts( "ERC32_INTERRUPT_DMA_ACCESS_ERROR" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_TIMEOUT ):
+      DEBUG_puts( "ERC32_INTERRUPT_DMA_TIMEOUT" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_3 ):
+      DEBUG_puts( "ERC32_INTERRUPT_EXTERNAL_3" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_4 ):
+      DEBUG_puts( "ERC32_INTERRUPT_EXTERNAL_4" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER ):
+      DEBUG_puts( "ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_REAL_TIME_CLOCK ):
+      DEBUG_puts( "ERC32_INTERRUPT_REAL_TIME_CLOCK" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_5 ):
+      DEBUG_puts( "ERC32_INTERRUPT_EXTERNAL_5" );
+      break;
+    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ):
+      DEBUG_puts( "ERC32_INTERRUPT_WATCHDOG_TIMEOUT" );
+      break;
+
+    default:
+      strcpy( line, "Number 0x  " );
+      length = strlen ( line );
+      line[ length - 2 ] = digits[ real_trap >> 4 ];
+      line[ length - 1 ] = digits[ real_trap & 0xf ];
+      DEBUG_puts( line ); 
+      break;
+  }
+
+  /*
+   *  What else can we do but stop ...
+   */
+
+  asm volatile( "ta 0x0" );
+}
+
+/*
+ *  bsp_spurious_initialize
+ *
+ *  Install the spurious handler for most traps.
+ */
+
+void bsp_spurious_initialize()
+{
+  rtems_unsigned32 trap;
+
+  for ( trap=0 ; trap<256 ; trap++ ) {
+
+    /*
+     *  Skip window overflow, underflow, and flush as well as software
+     *  trap 0 which we will use as a shutdown.
+     */
+
+    if ( trap == 5 || trap == 6 || trap == 0x83 || trap == 0x80)
+      continue;
+
+    set_vector( bsp_spurious_handler, SPARC_SYNCHRONOUS_TRAP( trap ), 1 );
+  }
+}
diff --git a/c/src/lib/libbsp/sparc/erc32/timer/timer.c b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
new file mode 100644
index 0000000000..bfa4482daa
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/timer/timer.c
@@ -0,0 +1,89 @@
+/*  timer.c
+ *
+ *  This file implements a benchmark timer using the General Purpose Timer on
+ *  the MEC.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+
+#include <bsp.h>
+
+rtems_boolean Timer_driver_Find_average_overhead;
+
+rtems_boolean Timer_driver_Is_initialized = FALSE;
+
+void Timer_initialize()
+{
+  /*
+   *  Timer runs long and accurate enough not to require an interrupt.
+   */
+
+  if ( Timer_driver_Is_initialized == FALSE ) {
+
+    /* approximately 1 us per countdown */
+    ERC32_MEC.General_Purpose_Timer_Scalar  = CLOCK_SPEED - 1;
+    ERC32_MEC.General_Purpose_Timer_Counter = 0xffffffff;
+
+  } else {
+    Timer_driver_Is_initialized = TRUE;
+  }
+
+  ERC32_MEC_Set_General_Purpose_Timer_Control( 
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
+      ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
+  );
+
+  ERC32_MEC_Set_General_Purpose_Timer_Control( 
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING
+  );
+
+}
+
+#define AVG_OVERHEAD      3  /* It typically takes 3.0 microseconds */
+                             /*     to start/stop the timer. */
+#define LEAST_VALID       2  /* Don't trust a value lower than this */
+
+int Read_timer()
+{
+  rtems_unsigned32  total;
+
+  total = ERC32_MEC.General_Purpose_Timer_Counter;
+
+  total = 0xffffffff - total;
+
+  if ( Timer_driver_Find_average_overhead == 1 )
+    return total;          /* in one microsecond units */
+
+  if ( total < LEAST_VALID )
+    return 0;            /* below timer resolution */
+
+  return total - AVG_OVERHEAD;
+}
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}