diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-08-09 20:57:11 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-08-09 20:57:11 +0000 |
| commit | 783669fcb3d0196034df104ca172bbb215a60237 (patch) | |
| tree | bbfbed63163fe3657cfbce2a31df4a2816436d02 /c | |
| parent | * libnetworking/rtems/rtems_mii_ioctl_kern.c: (diff) | |
| download | rtems-783669fcb3d0196034df104ca172bbb215a60237.tar.bz2 | |
2006-08-09 Kolja Waschk <waschk@telos.de>
* ChangeLog, Makefile.am, README, acinclude.m4, configure.ac,
nios2_iss/ChangeLog, nios2_iss/Makefile.am, nios2_iss/bsp_specs,
nios2_iss/configure.ac, nios2_iss/nios2_iss.ptf,
nios2_iss/nios2_iss.sh, nios2_iss/times, nios2_iss/console/console.c,
nios2_iss/include/bsp.h, nios2_iss/include/bspopts.h.in,
nios2_iss/include/coverhd.h, nios2_iss/include/tm27.h,
nios2_iss/shmsupp/addrconv.c, nios2_iss/shmsupp/getcfg.c,
nios2_iss/shmsupp/lock.c, nios2_iss/shmsupp/mpisr.c,
nios2_iss/start/crtnn.s, nios2_iss/start/start.S,
nios2_iss/startup/bspclean.c, nios2_iss/startup/bspstart.c,
nios2_iss/startup/linkcmds, nios2_iss/startup/main.c,
nios2_iss/startup/setvec.c, nios2_iss/timer/timer.c: New files.
Diffstat (limited to 'c')
29 files changed, 4136 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/nios2/ChangeLog b/c/src/lib/libbsp/nios2/ChangeLog new file mode 100644 index 0000000000..546e31c227 --- /dev/null +++ b/c/src/lib/libbsp/nios2/ChangeLog @@ -0,0 +1,109 @@ +2006-08-09 Kolja Waschk <waschk@telos.de> + + * ChangeLog, Makefile.am, README, acinclude.m4, configure.ac, + nios2_iss/ChangeLog, nios2_iss/Makefile.am, nios2_iss/bsp_specs, + nios2_iss/configure.ac, nios2_iss/nios2_iss.ptf, + nios2_iss/nios2_iss.sh, nios2_iss/times, nios2_iss/console/console.c, + nios2_iss/include/bsp.h, nios2_iss/include/bspopts.h.in, + nios2_iss/include/coverhd.h, nios2_iss/include/tm27.h, + nios2_iss/shmsupp/addrconv.c, nios2_iss/shmsupp/getcfg.c, + nios2_iss/shmsupp/lock.c, nios2_iss/shmsupp/mpisr.c, + nios2_iss/start/crtnn.s, nios2_iss/start/start.S, + nios2_iss/startup/bspclean.c, nios2_iss/startup/bspstart.c, + nios2_iss/startup/linkcmds, nios2_iss/startup/main.c, + nios2_iss/startup/setvec.c, nios2_iss/timer/timer.c: New files. + +2004-09-24 Ralf Corsepius <ralf_corsepius@rtems.org> + + * configure.ac: Require automake > 1.9. + +2004-02-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * acinclude.m4: Regenerate. + +2004-02-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]). + +2004-01-13 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use @RTEMS_BSP_FAMILY@ instead of + $(RTEMS_BSP_FAMILY). + +2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Require automake >= 1.8, autoconf >= 2.59. + +2003-10-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * acinclude.m4: Reflect changes to bootstrap. + * configure.ac: Remove RTEMS_CHECK_CUSTON_BSP. + +2003-08-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Reflect having moved aclocal/. + +2003-08-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Reflect having moved automake/. + +2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Use rtems-bugs@rtems.com as bug report email address. + +2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove AC_CONFIG_AUX_DIR. + +2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: AM_INIT_AUTOMAKE([1.7.2]). + +2003-02-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: AC_PREREQ(2.57). + +2002-12-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: Remove RTEMS_CHECK_BSP_CACHE. + +2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Reformat. + Add autom4te*cache. + Remove autom4te.cache. + +2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * configure.ac: + AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). + AM_INIT_AUTOMAKE([no-define foreign 1.6]). + * Makefile.am: Remove AUTOMAKE_OPTIONS. + +2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * .cvsignore: Add autom4te.cache for autoconf > 2.52. + * configure.in: Remove. + * configure.ac: New file, generated from configure.in by autoupdate. + +2001-10-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * acinclude.m4: New file. + * configure.in: Use RTEMS_BSP_SUBDIR. + +2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. + +2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. + +2000-10-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> + + * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. + Switch to GNU canonicalization. + +2000-08-10 Joel Sherrill <joel@OARcorp.com> + + * ChangeLog: New file. diff --git a/c/src/lib/libbsp/nios2/Makefile.am b/c/src/lib/libbsp/nios2/Makefile.am new file mode 100644 index 0000000000..e60a8966ac --- /dev/null +++ b/c/src/lib/libbsp/nios2/Makefile.am @@ -0,0 +1,11 @@ +## +## $Id$ +## + +ACLOCAL_AMFLAGS = -I ../../../aclocal + +# Descend into the @RTEMS_BSP_FAMILY@ directory +SUBDIRS = @RTEMS_BSP_FAMILY@ + +include $(top_srcdir)/../../../automake/subdirs.am +include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libbsp/nios2/README b/c/src/lib/libbsp/nios2/README new file mode 100644 index 0000000000..d427bb2266 --- /dev/null +++ b/c/src/lib/libbsp/nios2/README @@ -0,0 +1,79 @@ +# +# $Id$ +# +# Goal is to have BSPs build almost completely automatically from a template +# and information that comes from SOPC Builder as a .PTF file. Most of the +# code will go to a shared/ BSP directory. +# +# Ideally, updates to the PTF shouldn't cause any pain for the maintainer +# of a specific BSP (possibly with enhancements not covered by the +# automatic BSP creation). +# +# Some first steps toward utilizing SOPC Builder PTF output can be found +# in top level /tools/cpu/nios2. Also see the README there. +# +# Implemented (in shared/ subdirectory) +# Clock driver +# Timer driver +# Console via JTAG UART +# +# Todo; +# Support more peripherals. My priorities: +# - (improve) Altera Avalon JTAG UART +# - Altera Avalon UART +# - OpenCores.org I2C Master +# - Altera SPI Core / EPCS Configuration Device +# - OpenCores.org 10/100 Ethernet MAC (use existing driver) +# - (more) Altera Avalon Timer +# +# Put all drivers aside in a shared/ subdirectory. +# Update the "times" file for NIOS2 with and without icache. +# +# Missing (although it looks like it's there) +# Data cache handling (for now, don't use the "fast" NIOS2) +# SHM support (just taken over the code from no_cpu/no_bsp) +# +# Kolja Waschk, 6/2006 +# + +BSP NAME: nios2_eb2_1 +BOARD: Altera Instruction Set Simulator Default plus second timer +BUS: Avalon +CPU FAMILY: nios2 +CPU: small +COPROCESSORS: none +MODE: 32 bit mode + +DEBUG MONITOR: none + +PERIPHERALS +=========== +TIMERS: Altera Avalon Timer + RESOLUTION: .0001 microseconds +SERIAL PORTS: Altera Avalon JTAG UART +REAL-TIME CLOCK: none +DMA: none +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: Altera Avalon Timer +IOSUPP DRIVER: none +SHMSUPP: polled +TIMER DRIVER: Altera Avalon Timer +TTY DRIVER: none + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: JTAG +BAUD: 115200 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + diff --git a/c/src/lib/libbsp/nios2/acinclude.m4 b/c/src/lib/libbsp/nios2/acinclude.m4 new file mode 100644 index 0000000000..153d18b51c --- /dev/null +++ b/c/src/lib/libbsp/nios2/acinclude.m4 @@ -0,0 +1,10 @@ +# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY) +AC_DEFUN([RTEMS_CHECK_BSPDIR], +[ + case "$1" in + nios2_iss ) + AC_CONFIG_SUBDIRS([nios2_iss]);; + *) + AC_MSG_ERROR([Invalid BSP]);; + esac +]) diff --git a/c/src/lib/libbsp/nios2/configure.ac b/c/src/lib/libbsp/nios2/configure.ac new file mode 100644 index 0000000000..a008231d64 --- /dev/null +++ b/c/src/lib/libbsp/nios2/configure.ac @@ -0,0 +1,21 @@ +## Process this file with autoconf to produce a configure script. +## +## $Id$ + +AC_PREREQ(2.59) +AC_INIT([rtems-c-src-lib-libbsp-nios2],[_RTEMS_VERSION],[rtems-bugs@rtems.com]) +AC_CONFIG_SRCDIR([nios2_iss]) +RTEMS_TOP(../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define foreign 1.9]) +AM_MAINTAINER_MODE + +RTEMS_ENV_RTEMSBSP +RTEMS_PROJECT_ROOT + +RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY]) + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/nios2/nios2_iss/ChangeLog b/c/src/lib/libbsp/nios2/nios2_iss/ChangeLog new file mode 100644 index 0000000000..c3cd7a3171 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/ChangeLog @@ -0,0 +1,4 @@ +2005-12-12 Kolja Waschk + + * derived from no_cpu BSP + diff --git a/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am b/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am new file mode 100644 index 0000000000..b51a4aeef1 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/Makefile.am @@ -0,0 +1,121 @@ +## +## $Id$ +## + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am +include $(top_srcdir)/../../bsp.am + + +dist_project_lib_DATA = bsp_specs + +include_HEADERS = include/bsp.h +include_HEADERS += include/tm27.h + +nodist_include_HEADERS = include/bspopts.h +DISTCLEANFILES = include/bspopts.h + +noinst_PROGRAMS = + +include_HEADERS += include/coverhd.h + +EXTRA_DIST = start/start.S start/crtnn.s times +crtnn.$(OBJEXT): start/crtnn.s + $(CPPASCOMPILE) -DASM -o $@ -c $< +start.$(OBJEXT): start/start.S + $(CPPASCOMPILE) -DASM -o $@ -c $< +project_lib_DATA = start.$(OBJEXT) crtnn.$(OBJEXT) + +dist_project_lib_DATA += startup/linkcmds + +noinst_PROGRAMS += clock.rel +clock_rel_SOURCES = clock/clock.c +clock_rel_CPPFLAGS = $(AM_CPPFLAGS) +clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +noinst_PROGRAMS += console.rel +console_rel_SOURCES = console/console.c +console_rel_CPPFLAGS = $(AM_CPPFLAGS) +console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +if HAS_MP +noinst_PROGRAMS += shmsupp.rel +shmsupp_rel_SOURCES = shmsupp/addrconv.c shmsupp/getcfg.c shmsupp/lock.c \ + shmsupp/mpisr.c +shmsupp_rel_CPPFLAGS = $(AM_CPPFLAGS) +shmsupp_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) +endif + +noinst_PROGRAMS += startup.rel +startup_rel_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \ + ../../shared/bsppost.c startup/bspstart.c ../../shared/main.c \ + ../../shared/bootcard.c ../../shared/sbrk.c startup/setvec.c \ + ../../shared/gnatinstallhandler.c +startup_rel_CPPFLAGS = $(AM_CPPFLAGS) +startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +noinst_PROGRAMS += timer.rel +timer_rel_SOURCES = timer/timer.c +timer_rel_CPPFLAGS = $(AM_CPPFLAGS) +timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +noinst_LIBRARIES = libbsp.a +libbsp_a_SOURCES = +libbsp_a_LIBADD = startup.rel clock.rel console.rel timer.rel +if HAS_MP +libbsp_a_LIBADD += shmsupp.rel +endif + +all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES) + +PREINSTALL_DIRS = +PREINSTALL_FILES = +TMPINSTALL_FILES = + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(mkdir_p) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_LIB)/$(dirstamp): + @$(mkdir_p) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/crtnn.$(OBJEXT): crtnn.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/crtnn.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/crtnn.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds + +CLEANFILES = $(PREINSTALL_FILES) +DISTCLEANFILES += $(PREINSTALL_DIRS) + +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/nios2/nios2_iss/bsp_specs b/c/src/lib/libbsp/nios2/nios2_iss/bsp_specs new file mode 100644 index 0000000000..c460ce5502 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/bsp_specs @@ -0,0 +1,27 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} %{!nostdlib: %{qrtems: --start-group \ +%{!qrtems_debug: -lrtemsbsp -lrtemscpu} %{qrtems_debug: -lrtemsbsp_g -lrtemscpu_g} \ +-lc -lgcc --end-group \ +%{!qnolinkcmds: -T linkcmds%s}}} + +*startfile: +%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems: \ +%{!qrtems_debug: start.o%s} \ +%{qrtems_debug: start_g.o%s} \ +crti.o%s crtbegin.o%s }} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start} + +*endfile: +%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtnn.o%s} + diff --git a/c/src/lib/libbsp/nios2/nios2_iss/configure.ac b/c/src/lib/libbsp/nios2/nios2_iss/configure.ac new file mode 100644 index 0000000000..4562dc81d5 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/configure.ac @@ -0,0 +1,20 @@ +## Process this file with autoconf to produce a configure script. +## +## $Id$ + +AC_PREREQ(2.59) +AC_INIT([rtems-c-src-lib-libbsp-nios2-nios2_iss],[_RTEMS_VERSION],[rtems-bugs@rtems.com]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm]) +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/nios2/nios2_iss/console/console.c b/c/src/lib/libbsp/nios2/nios2_iss/console/console.c new file mode 100644 index 0000000000..c0e572e550 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/console/console.c @@ -0,0 +1,264 @@ +/* + * This file implements simple console IO via JTAG UART. + * + * Based on no_cpu/console.c + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Altera-specific code is + * COPYRIGHT (c) 2005-2006 Kolja Waschk, rtemsdev/ixo.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#define NO_BSP_INIT + +#include <bsp.h> +#include <rtems/libio.h> + +/* #define JTAG_UART_REGS ((altera_avalon_jtag_uart_regs*)NIOS2_IO_BASE(JTAG_UART_BASE)) */ + +#if 0 +extern rtems_cpu_table Cpu_table; /* owned by BSP */ + +#define XOFFchar 0x13 +#define XONchar 0x11 +#endif + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code status; + + status = rtems_io_register_name( + "/dev/console", + major, + (rtems_device_minor_number) 0 + ); + + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + + return RTEMS_SUCCESSFUL; +} + +/* is_character_ready + * + * If a character is available, this routine reads it and stores + * it in + * reads the character and stores + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_boolean is_character_ready( + char *ch +) +{ + altera_avalon_jtag_uart_regs *ajur = NIOS2_IO_BASE(JTAG_UART_BASE); + unsigned int data = ajur->data; + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) + { + *ch = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) + >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + return TRUE; + }; + + return FALSE; +} + +/* inbyte + * + * This routine reads a character from the SOURCE. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + * character read from SOURCE + */ + +char inbyte( void ) +{ + /* + * Wait until a character is available. + */ + char ch; + while(!is_character_ready(&ch)); + return ch; +} + +/* outbyte + * + * This routine transmits a character out the SOURCE. It may support + * XON/XOFF flow control. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ + altera_avalon_jtag_uart_regs *ajur = NIOS2_IO_BASE(JTAG_UART_BASE); + /* + * Carriage Return/New line translation. + */ + + if ( ch == '\n' ) + outbyte( '\r' ); + + /* + * Wait for the transmitter to be ready. + * Check for flow control requests and process. + * Then output the character. + */ + + while ((ajur->control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) == 0); + +#if 0 + if (Cpu_table.serial_xon_xoff) + { + while (is_character_ready(&status)) + { + if (status == XOFFchar) + do + { + while (!is_character_ready(&status)); + } + while (status != XONchar); + } + } +#endif + + ajur->data = ch; +} + +/* + * Open entry point + */ + +rtems_device_driver console_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} + +/* + * Close entry point + */ + +rtems_device_driver console_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} + +/* + * read bytes from the serial port. We only have stdin. + */ + +rtems_device_driver console_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + rtems_libio_rw_args_t *rw_args; + char *buffer; + int maximum; + int count = 0; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + buffer[ count ] = inbyte(); + if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { + buffer[ count++ ] = '\n'; + break; + } + } + + rw_args->bytes_moved = count; + return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; +} + +/* + * write bytes to the serial port. Stdout and stderr are the same. + */ + +rtems_device_driver console_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + int count; + int maximum; + rtems_libio_rw_args_t *rw_args; + char *buffer; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + if ( buffer[ count ] == '\n') { + outbyte('\r'); + } + outbyte( buffer[ count ] ); + } + + rw_args->bytes_moved = maximum; + return 0; +} + +/* + * IO Control entry point + */ + +rtems_device_driver console_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h b/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h new file mode 100644 index 0000000000..8a1ea7e0f4 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h @@ -0,0 +1,173 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _BSP_H +#define _BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <bspopts.h> + +#include <rtems.h> +#include <rtems/console.h> +#include <rtems/clockdrv.h> + + +/* + * confdefs.h overrides for this BSP: + * - number of termios serial ports (defaults to 1) + * - Interrupt stack space is not minimum if defined. + */ + +/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */ +#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define rtems_bsp_delay( microseconds ) \ + { \ + } + +/* ============================================ */ + +/* SOPC-specific Constants */ + +#define SYSTEM_BUS_WIDTH 32 + +#define RAM_BASE 0 +#define RAM_BYTES 0x00800000 + +#define JTAG_UART_BASE 0x08000000 +#define JTAG_UART_IRQ 2 + +#define CLOCK_BASE 0x08001000 +#define CLOCK_FREQ 50000000 +#define CLOCK_VECTOR 1 + +#define TIMER_BASE 0x08002000 +#define TIMER_FREQ 50000000 +#define TIMER_VECTOR 3 + +/* ============================================ */ + +#define NIOS2_BYPASS_CACHE ((uint32_t)0x80000000ul) +#define NIOS2_IO_BASE(x) ( (void*) ((uint32_t)x | NIOS2_BYPASS_CACHE ) ) +#define NIOS2_IENABLE(x) do{ __builtin_wrctl(3,__builtin_rdctl(3)|x);}while(0) +#define NIOS2_IRQ_ENABLE(x) do {__builtin_wrctl(3,__builtin_rdctl(3)|x);} while(0) + +/* ============================================ */ +/* TODO: Put this in an external header file */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH is undefined +#endif + +#if SYSTEM_BUS_WIDTH != 32 +#error Only SYSTEM_BUS_WIDTH 32 is supported +#endif + +typedef struct +{ + volatile uint32_t status; + volatile uint32_t control; + volatile uint32_t period_lo; + volatile uint32_t period_hi; + volatile uint32_t snap_lo; + volatile uint32_t snap_hi; +} +altera_avalon_timer_regs; + +#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) +#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) +#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) +#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) + +#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) +#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) +#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) + +typedef struct +{ + volatile uint32_t data; + volatile uint32_t control; +} +altera_avalon_jtag_uart_regs; + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FFu) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000u) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000u) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000u) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +/* ============================================ */ + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* functions */ + +void bsp_cleanup( void ); + +nios2_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/nios2/nios2_iss/include/bspopts.h.in b/c/src/lib/libbsp/nios2/nios2_iss/include/bspopts.h.in new file mode 100644 index 0000000000..f11cf7efbb --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/include/bspopts.h.in @@ -0,0 +1,16 @@ +/* include/bspopts.h.in. Generated from configure.ac by autoheader. */ + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION diff --git a/c/src/lib/libbsp/nios2/nios2_iss/include/coverhd.h b/c/src/lib/libbsp/nios2/nios2_iss/include/coverhd.h new file mode 100644 index 0000000000..5a87063f9a --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/include/coverhd.h @@ -0,0 +1,106 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 0 +#define CALLING_OVERHEAD_CLOCK_SET 0 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#endif diff --git a/c/src/lib/libbsp/nios2/nios2_iss/include/tm27.h b/c/src/lib/libbsp/nios2/nios2_iss/include/tm27.h new file mode 100644 index 0000000000..a10e11cab1 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/include/tm27.h @@ -0,0 +1,32 @@ +/* + * tm27.h + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.ptf b/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.ptf new file mode 100644 index 0000000000..7f3dd0fcf6 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.ptf @@ -0,0 +1,1800 @@ +SYSTEM Nios2_system +{ + System_Wizard_Version = "4.10"; + System_Wizard_Build = "181"; + WIZARD_SCRIPT_ARGUMENTS + { + device_family = "STRATIX"; + clock_freq = "50000000"; + generate_hdl = "0"; + generate_sdk = "0"; + do_build_sim = "0"; + hdl_language = "vhdl"; + view_master_columns = "1"; + view_master_priorities = "0"; + board_class = ""; + name_column_width = "75"; + desc_column_width = "75"; + bustype_column_width = "0"; + base_column_width = "75"; + end_column_width = "75"; + view_frame_window = "170:208:1280:900"; + do_log_history = "0"; + device_family_id = "STRATIX"; + BOARD_INFO + { + device_is_engineering_sample = ""; + } + } + MODULE cpu_0 + { + class = "altera_nios2"; + class_version = "1.0"; + iss_model_name = "altera_nios2"; + HDL_INFO + { + PLI_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd"; + Precompiled_Simulation_Library_Files = ""; + Synthesis_Only_Files = ""; + } + MASTER instruction_master + { + PORT_WIRING + { + PORT i_address + { + direction = "output"; + type = "address"; + width = "28"; + } + PORT i_read + { + direction = "output"; + type = "read"; + width = "1"; + } + PORT i_readdata + { + direction = "input"; + type = "readdata"; + width = "32"; + } + PORT i_readdatavalid + { + direction = "input"; + type = "readdatavalid"; + width = "1"; + } + PORT i_waitrequest + { + direction = "input"; + type = "waitrequest"; + width = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "32"; + Address_Width = "8"; + Is_Instruction_Master = "1"; + Has_IRQ = "0"; + Irq_Scheme = "individual_requests"; + Interrupt_Range = "0-0"; + Is_Enabled = "1"; + } + } + MASTER data_master + { + PORT_WIRING + { + PORT clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT d_address + { + direction = "output"; + type = "address"; + width = "28"; + } + PORT d_byteenable + { + direction = "output"; + type = "byteenable"; + width = "4"; + } + PORT d_irq + { + direction = "input"; + type = "irq"; + width = "32"; + } + PORT d_read + { + direction = "output"; + type = "read"; + width = "1"; + } + PORT d_readdata + { + direction = "input"; + type = "readdata"; + width = "32"; + } + PORT d_waitrequest + { + direction = "input"; + type = "waitrequest"; + width = "1"; + } + PORT d_write + { + direction = "output"; + type = "write"; + width = "1"; + } + PORT d_writedata + { + direction = "output"; + type = "writedata"; + width = "32"; + } + PORT jtag_debug_module_debugaccess_to_roms + { + direction = "output"; + type = "debugaccess"; + width = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "32"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "1"; + Irq_Scheme = "individual_requests"; + Interrupt_Range = "0-31"; + Is_Enabled = "1"; + } + } + SLAVE oci_core + { + PORT_WIRING + { + PORT byteenable + { + direction = "input"; + type = "byteenable"; + width = "4"; + } + PORT oci_core_address + { + direction = "input"; + type = "address"; + width = "9"; + } + PORT oci_core_begintransfer + { + direction = "input"; + type = "begintransfer"; + width = "1"; + } + PORT oci_core_clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT oci_core_readdata + { + direction = "output"; + type = "readdata"; + width = "32"; + } + PORT oci_core_reset + { + direction = "input"; + type = "reset"; + width = "1"; + } + PORT oci_core_resetrequest + { + direction = "output"; + type = "resetrequest"; + width = "1"; + } + PORT oci_core_select + { + direction = "input"; + type = "chipselect"; + width = "1"; + } + PORT oci_core_write + { + direction = "input"; + type = "write"; + width = "1"; + } + PORT oci_core_writedata + { + direction = "input"; + type = "writedata"; + width = "32"; + } + PORT reset_n + { + direction = "input"; + type = "reset_n"; + width = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Read_Wait_States = "1"; + Write_Wait_States = "1"; + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Address_Width = "9"; + Accepts_Internal_Connections = "1"; + Requires_Internal_Connections = "instruction_master,data_master"; + Accepts_External_Connections = "0"; + Is_Enabled = "1"; + Address_Alignment = "dynamic"; + Base_Address = "0x08100000"; + Is_Memory_Device = "1"; + Is_Printable_Device = "1"; + Uses_Tri_State_Data_Bus = "0"; + Has_IRQ = "0"; + JTAG_Hub_Base_Id = "69702"; + JTAG_Hub_Instance_Id = "0"; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + WIZARD_SCRIPT_ARGUMENTS + { + CPU_Architecture = "nios2"; + do_generate = "1"; + cpu_selection = "f"; + CPU_Implementation = "fast"; + cache_has_dcache = "1"; + cache_has_icache = "1"; + cache_dcache_size = "2048"; + cache_icache_size = "4096"; + include_debug = "0"; + include_trace = "0"; + include_oci = "1"; + debug_level = "2"; + oci_offchip_trace = "0"; + oci_onchip_trace = "0"; + oci_trace_addr_width = "7"; + oci_num_xbrk = "0"; + oci_num_dbrk = "0"; + oci_dbrk_trace = "0"; + oci_dbrk_pairs = "0"; + oci_debugreq_signals = "0"; + oci_instance_number = "1"; + hardware_multiply_present = "1"; + hardware_divide_present = "0"; + bht_ptr_sz = "8"; + reset_slave = "onchip_memory_0/s1"; + reset_offset = "0x00000000"; + exc_slave = "onchip_memory_0/s1"; + exc_offset = "0x00000600"; + break_slave = "cpu_0/jtag_debug_module"; + break_offset = "0x00000020"; + altera_internal_test = "0"; + full_waveform_signals = "0"; + activate_model_checker = "0"; + bit_31_bypass_dcache = "1"; + always_bypass_dcache = "0"; + always_unsigned_mul = "0"; + consistent_synthesis = "0"; + ibuf_ptr_sz = "4"; + jtb_ptr_sz = "5"; + performance_counters_present = "0"; + performance_counters_width = "32"; + ras_ptr_sz = "4"; + inst_decode_in_submodule = "0"; + register_dependency_in_submodule = "0"; + source_operands_in_submodule = "0"; + alu_in_submodule = "0"; + stdata_in_submodule = "0"; + shift_rot_2N_in_submodule = "0"; + control_regs_in_submodule = "0"; + mult_cell_in_submodule = "0"; + M_inst_result_mux_in_submodule = "0"; + dcache_load_aligner_in_submodule = "0"; + hardware_divide_in_submodule = "0"; + mult_result_mux_in_submodule = "0"; + shift_rotate_in_submodule = "0"; + register_file_write_data_mux_in_submodule = "0"; + avalon_imaster_in_submodule = "0"; + avalon_dmaster_in_submodule = "0"; + avalon_load_aligner_in_submodule = "0"; + hbreak_test = "0"; + iss_trace_on = "0"; + iss_trace_warning = "1"; + iss_trace_info = "1"; + iss_trace_disassembly = "0"; + iss_trace_registers = "0"; + iss_trace_instr_count = "0"; + iss_software_debug = "0"; + iss_software_debug_port = "9996"; + iss_memory_dump_start = ""; + iss_memory_dump_end = ""; + CONSTANTS + { + CONSTANT __nios_catch_irqs__ + { + value = "1"; + comment = "Include panic handler for all irqs (needs uart)"; + } + CONSTANT __nios_use_constructors__ + { + value = "1"; + comment = "Call c++ static constructors"; + } + CONSTANT __nios_use_small_printf__ + { + value = "1"; + comment = "Smaller non-ANSI printf, with no floating point"; + } + CONSTANT nasys_has_icache + { + value = "0"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_icache_size + { + value = "4096"; + comment = "Size in bytes of instruction cache"; + } + CONSTANT nasys_icache_line_size + { + value = "32"; + comment = "Size in bytes of each icache line"; + } + CONSTANT nasys_icache_line_size_log2 + { + value = "5"; + comment = "Log2 size in bytes of each icache line"; + } + CONSTANT nasys_has_dcache + { + value = "0"; + comment = "True if instruction cache present"; + } + CONSTANT nasys_dcache_size + { + value = "2048"; + comment = "Size in bytes of data cache"; + } + CONSTANT nasys_dcache_line_size + { + value = "4"; + comment = "Size in bytes of each dcache line"; + } + CONSTANT nasys_dcache_line_size_log2 + { + value = "2"; + comment = "Log2 size in bytes of each dcache line"; + } + } + mainmem_slave = ""; + datamem_slave = ""; + maincomm_slave = ""; + debugcomm_slave = ""; + germs_monitor_id = ""; + asp_debug = "0"; + asp_core_debug = "0"; + include_third_party_debug_port = "0"; + oci_data_trace = "0"; + oci_num_pm = "0"; + oci_pm_width = "40"; + oci_trigger_arming = "1"; + break_slave_override = ""; + break_offset_override = "0x20"; + legacy_sdk_support = "0"; + altera_show_unreleased_features = "0"; + illegal_instructions_trap = "0"; + remove_hardware_multiplier = "0"; + large_dcache_allow_mram = "0"; + cache_omit_dcache = "0"; + cache_omit_icache = "0"; + omit_instruction_master = "0"; + omit_data_master = "0"; + num_local_data_masters = "0"; + num_local_instruction_masters = "0"; + gui_branch_prediction_type = "Automatic"; + branch_prediction_type = "Dynamic"; + bht_index_pc_only = "0"; + mmu_present = "0"; + process_id_num_bits = "10"; + dtlb_ptr_sz = "7"; + dtlb_num_ways = "4"; + udtlb_num_entries = "6"; + itlb_ptr_sz = "7"; + itlb_num_ways = "4"; + uitlb_num_entries = "4"; + fast_tlb_miss_exc_slave = "onchip_memory_0/s1"; + fast_tlb_miss_exc_offset = "0x00000000"; + always_encrypt = "1"; + activate_monitors = "1"; + activate_test_end_checker = "0"; + activate_trace = "1"; + clear_x_bits_ld_non_bypass = "1"; + hdl_sim_caches_cleared = "1"; + allow_full_address_range = "0"; + Boot_Copier = "boot_loader_cfi.srec"; + Boot_Copier_EPCS = "boot_loader_epcs.srec"; + license_status = "ocp"; + } + SYSTEM_BUILDER_INFO + { + Parameters_Signature = ""; + Is_CPU = "1"; + Is_Enabled = "1"; + Instantiate_In_System_Module = "1"; + Default_Module_Name = "cpu"; + View + { + MESSAGES + { + } + Is_Collapsed = "0"; + Settings_Summary = "Nios II/f + <br> 4-Kbyte Instruction Cache + <br> 2-Kbyte Data Cache + <br> JTAG Debug Module + "; + } + Required_Device_Family = "STRATIX,STRATIXII,CYCLONE"; + } + SOFTWARE_COMPONENT altera_hal + { + class = "altera_hal"; + class_version = "1.0"; + WIZARD_SCRIPT_ARGUMENTS + { + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + } + } + SOFTWARE_COMPONENT altera_nios2_test + { + class = "altera_nios2_test"; + class_version = "2.0"; + WIZARD_SCRIPT_ARGUMENTS + { + CONSTANTS + { + CONSTANT debug_on + { + value = "0"; + comment = "Enable debug features"; + } + } + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "0"; + } + } + SOFTWARE_COMPONENT altera_plugs_library + { + class = "altera_plugs_library"; + class_version = "2.1"; + WIZARD_SCRIPT_ARGUMENTS + { + CONSTANTS + { + CONSTANT PLUGS_PLUG_COUNT + { + value = "5"; + comment = "Maximum number of plugs"; + } + CONSTANT PLUGS_ADAPTER_COUNT + { + value = "2"; + comment = "Maximum number of adapters"; + } + CONSTANT PLUGS_DNS + { + value = "1"; + comment = "Have routines for DNS lookups"; + } + CONSTANT PLUGS_PING + { + value = "1"; + comment = "Respond to icmp echo (ping) messages"; + } + CONSTANT PLUGS_TCP + { + value = "1"; + comment = "Support tcp in/out connections"; + } + CONSTANT PLUGS_IRQ + { + value = "1"; + comment = "Run at interrupte level"; + } + CONSTANT PLUGS_DEBUG + { + value = "1"; + comment = "Support debug routines"; + } + } + } + SYSTEM_BUILDER_INFO + { + Is_Enabled = "1"; + } + } + PORT_WIRING + { + } + SIMULATION + { + DISPLAY + { + SIGNAL aaa + { + format = "Logic"; + name = "i_readdata"; + radix = "hexadecimal"; + } + SIGNAL aab + { + format = "Logic"; + name = "i_readdatavalid"; + radix = "hexadecimal"; + } + SIGNAL aac + { + format = "Logic"; + name = "i_waitrequest"; + radix = "hexadecimal"; + } + SIGNAL aad + { + format = "Logic"; + name = "i_address"; + radix = "hexadecimal"; + } + SIGNAL aae + { + format = "Logic"; + name = "i_read"; + radix = "hexadecimal"; + } + SIGNAL aaf + { + format = "Logic"; + name = "clk"; + radix = "hexadecimal"; + } + SIGNAL aag + { + format = "Logic"; + name = "reset_n"; + radix = "hexadecimal"; + } + SIGNAL aah + { + format = "Logic"; + name = "d_readdata"; + radix = "hexadecimal"; + } + SIGNAL aai + { + format = "Logic"; + name = "d_waitrequest"; + radix = "hexadecimal"; + } + SIGNAL aaj + { + format = "Logic"; + name = "d_irq"; + radix = "hexadecimal"; + } + SIGNAL aak + { + format = "Logic"; + name = "d_address"; + radix = "hexadecimal"; + } + SIGNAL aal + { + format = "Logic"; + name = "d_byteenable"; + radix = "hexadecimal"; + } + SIGNAL aam + { + format = "Logic"; + name = "d_read"; + radix = "hexadecimal"; + } + SIGNAL aan + { + format = "Logic"; + name = "d_write"; + radix = "hexadecimal"; + } + SIGNAL aao + { + format = "Logic"; + name = "d_writedata"; + radix = "hexadecimal"; + } + SIGNAL aap + { + format = "Divider"; + name = "base pipeline"; + radix = ""; + } + SIGNAL aaq + { + format = "Logic"; + name = "clk"; + radix = "hexadecimal"; + } + SIGNAL aar + { + format = "Logic"; + name = "reset_n"; + radix = "hexadecimal"; + } + SIGNAL aas + { + format = "Logic"; + name = "D_stall"; + radix = "hexadecimal"; + } + SIGNAL aat + { + format = "Logic"; + name = "A_stall"; + radix = "hexadecimal"; + } + SIGNAL aau + { + format = "Logic"; + name = "F_pcb_nxt"; + radix = "hexadecimal"; + } + SIGNAL aav + { + format = "Logic"; + name = "F_pcb"; + radix = "hexadecimal"; + } + SIGNAL aaw + { + format = "Logic"; + name = "D_pcb"; + radix = "hexadecimal"; + } + SIGNAL aax + { + format = "Logic"; + name = "E_pcb"; + radix = "hexadecimal"; + } + SIGNAL aay + { + format = "Logic"; + name = "M_pcb"; + radix = "hexadecimal"; + } + SIGNAL aaz + { + format = "Logic"; + name = "A_pcb"; + radix = "hexadecimal"; + } + SIGNAL aba + { + format = "Logic"; + name = "W_pcb"; + radix = "hexadecimal"; + } + SIGNAL abb + { + format = "Logic"; + name = "F_vinst"; + radix = "ascii"; + } + SIGNAL abc + { + format = "Logic"; + name = "D_vinst"; + radix = "ascii"; + } + SIGNAL abd + { + format = "Logic"; + name = "E_vinst"; + radix = "ascii"; + } + SIGNAL abe + { + format = "Logic"; + name = "M_vinst"; + radix = "ascii"; + } + SIGNAL abf + { + format = "Logic"; + name = "A_vinst"; + radix = "ascii"; + } + SIGNAL abg + { + format = "Logic"; + name = "W_vinst"; + radix = "ascii"; + } + SIGNAL abh + { + format = "Logic"; + name = "F_inst_ram_hit"; + radix = "hexadecimal"; + } + SIGNAL abi + { + format = "Logic"; + name = "F_issue"; + radix = "hexadecimal"; + } + SIGNAL abj + { + format = "Logic"; + name = "F_kill"; + radix = "hexadecimal"; + } + SIGNAL abk + { + format = "Logic"; + name = "D_kill"; + radix = "hexadecimal"; + } + SIGNAL abl + { + format = "Logic"; + name = "D_refetch"; + radix = "hexadecimal"; + } + SIGNAL abm + { + format = "Logic"; + name = "D_issue"; + radix = "hexadecimal"; + } + SIGNAL abn + { + format = "Logic"; + name = "D_valid"; + radix = "hexadecimal"; + } + SIGNAL abo + { + format = "Logic"; + name = "E_valid"; + radix = "hexadecimal"; + } + SIGNAL abp + { + format = "Logic"; + name = "M_valid"; + radix = "hexadecimal"; + } + SIGNAL abq + { + format = "Logic"; + name = "A_valid"; + radix = "hexadecimal"; + } + SIGNAL abr + { + format = "Logic"; + name = "W_valid"; + radix = "hexadecimal"; + } + SIGNAL abs + { + format = "Logic"; + name = "W_wr_dst_reg"; + radix = "hexadecimal"; + } + SIGNAL abt + { + format = "Logic"; + name = "W_dst_regnum"; + radix = "hexadecimal"; + } + SIGNAL abu + { + format = "Logic"; + name = "W_wr_data"; + radix = "hexadecimal"; + } + SIGNAL abv + { + format = "Logic"; + name = "D_en"; + radix = "hexadecimal"; + } + SIGNAL abw + { + format = "Logic"; + name = "E_en"; + radix = "hexadecimal"; + } + SIGNAL abx + { + format = "Logic"; + name = "M_en"; + radix = "hexadecimal"; + } + SIGNAL aby + { + format = "Logic"; + name = "A_en"; + radix = "hexadecimal"; + } + SIGNAL abz + { + format = "Logic"; + name = "F_iw"; + radix = "hexadecimal"; + } + SIGNAL aca + { + format = "Logic"; + name = "D_iw"; + radix = "hexadecimal"; + } + SIGNAL acb + { + format = "Logic"; + name = "E_iw"; + radix = "hexadecimal"; + } + SIGNAL acc + { + format = "Logic"; + name = "E_cancel"; + radix = "hexadecimal"; + } + SIGNAL acd + { + format = "Logic"; + name = "E_pipe_flush"; + radix = "hexadecimal"; + } + SIGNAL ace + { + format = "Logic"; + name = "E_pipe_flush_baddr"; + radix = "hexadecimal"; + } + SIGNAL acf + { + format = "Logic"; + name = "A_status_reg_pie"; + radix = "hexadecimal"; + } + SIGNAL acg + { + format = "Logic"; + name = "A_ienable_reg"; + radix = "hexadecimal"; + } + SIGNAL ach + { + format = "Logic"; + name = "intr_req"; + radix = "hexadecimal"; + } + } + } + MASTER data_master2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER local_data_master_0 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER local_data_master_1 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER local_data_master_2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER local_data_master_3 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Data_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER local_instruction_master_0 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Register_Incoming_Signals = "0"; + Bus_Type = "avalon"; + Data_Width = "32"; + Max_Address_Width = "31"; + Address_Width = "8"; + Is_Instruction_Master = "1"; + Has_IRQ = "0"; + Is_Enabled = "0"; + } + } + MASTER custom_instruction_master + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "nios_custom_instruction"; + Data_Width = "32"; + Address_Width = "8"; + Max_Address_Width = "8"; + Base_Address = "N/A"; + Is_Visible = "0"; + Is_Custom_Instruction = "0"; + Is_Enabled = "0"; + } + } + SLAVE jtag_debug_module + { + PORT_WIRING + { + PORT jtag_debug_module_address + { + direction = "input"; + type = "address"; + width = "9"; + } + PORT jtag_debug_module_begintransfer + { + direction = "input"; + type = "begintransfer"; + width = "1"; + } + PORT jtag_debug_module_byteenable + { + direction = "input"; + type = "byteenable"; + width = "4"; + } + PORT jtag_debug_module_clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT jtag_debug_module_debugaccess + { + direction = "input"; + type = "debugaccess"; + width = "1"; + } + PORT jtag_debug_module_readdata + { + direction = "output"; + type = "readdata"; + width = "32"; + } + PORT jtag_debug_module_reset + { + direction = "input"; + type = "reset"; + width = "1"; + } + PORT jtag_debug_module_resetrequest + { + direction = "output"; + type = "resetrequest"; + width = "1"; + } + PORT jtag_debug_module_select + { + direction = "input"; + type = "chipselect"; + width = "1"; + } + PORT jtag_debug_module_write + { + direction = "input"; + type = "write"; + width = "1"; + } + PORT jtag_debug_module_writedata + { + direction = "input"; + type = "writedata"; + width = "32"; + } + PORT reset_n + { + direction = "input"; + type = "reset_n"; + width = "1"; + } + } + SYSTEM_BUILDER_INFO + { + Read_Wait_States = "1"; + Write_Wait_States = "1"; + Register_Incoming_Signals = "1"; + Bus_Type = "avalon"; + Data_Width = "32"; + Address_Width = "9"; + Accepts_Internal_Connections = "1"; + Requires_Internal_Connections = "instruction_master,data_master"; + Accepts_External_Connections = "0"; + Is_Enabled = "1"; + Address_Alignment = "dynamic"; + Base_Address = "0x08200800"; + Is_Memory_Device = "1"; + Is_Printable_Device = "0"; + Uses_Tri_State_Data_Bus = "0"; + Has_IRQ = "0"; + JTAG_Hub_Base_Id = "593990"; + JTAG_Hub_Instance_Id = "0"; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + } + MODULE onchip_memory_0 + { + class = "altera_avalon_onchip_memory2"; + class_version = "4.0"; + iss_model_name = "altera_memory"; + HDL_INFO + { + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory_1.vhd"; + Synthesis_Only_Files = ""; + } + WIZARD_SCRIPT_ARGUMENTS + { + allow_mram_sim_contents_only_file = "0"; + ram_block_type = "M-RAM"; + gui_ram_block_type = "Automatic"; + Writeable = "1"; + dual_port = "0"; + Size_Value = "8192"; + Size_Multiple = "1024"; + MAKE + { + TARGET delete_placeholder_warning + { + onchip_memory_1 + { + Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; + Is_Phony = "1"; + Target_File = "do_delete_placeholder_warning"; + } + } + TARGET hex + { + onchip_memory_1 + { + Command1 = "@echo Post-processing to create $(notdir $@)"; + Command2 = "elf2hex $(ELF) 0x00000000 0x7FF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex --create-lanes=0"; + Dependency = "$(ELF)"; + Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex"; + } + } + TARGET sim + { + onchip_memory_1 + { + Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; + Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \(Note: This does not affect the instruction set simulator.\)"; + Command3 = "touch $(SIMDIR)/dummy_file"; + Dependency = "$(ELF)"; + Target_File = "$(SIMDIR)/dummy_file"; + } + } + } + contents_info = "QUARTUS_PROJECT_DIR/onchip_memory_1.hex 1092402177 "; + } + SYSTEM_BUILDER_INFO + { + Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM"; + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Default_Module_Name = "onchip_memory"; + View + { + MESSAGES + { + } + Is_Collapsed = "1"; + } + } + SLAVE s1 + { + PORT_WIRING + { + PORT address + { + direction = "input"; + type = "address"; + width = "9"; + } + PORT byteenable + { + direction = "input"; + type = "byteenable"; + width = "4"; + } + PORT chipselect + { + direction = "input"; + type = "chipselect"; + width = "1"; + } + PORT clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT readdata + { + direction = "output"; + type = "readdata"; + width = "32"; + } + PORT write + { + direction = "input"; + type = "write"; + width = "1"; + } + PORT writedata + { + direction = "input"; + type = "writedata"; + width = "32"; + } + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Memory_Device = "1"; + Address_Alignment = "dynamic"; + Address_Width = "21"; + Data_Width = "32"; + Has_IRQ = "0"; + Read_Wait_States = "0"; + Write_Wait_States = "0"; + Address_Span = "134217728"; + Read_Latency = "1"; + MASTERED_BY cpu_0/instruction_master + { + priority = "1"; + } + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + Base_Address = "0x00000000"; + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "NC"; + } + } + } + SLAVE s2 + { + PORT_WIRING + { + } + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Memory_Device = "1"; + Address_Alignment = "dynamic"; + Address_Width = "21"; + Data_Width = "32"; + Has_IRQ = "0"; + Read_Wait_States = "0"; + Write_Wait_States = "0"; + Address_Span = "8388608"; + Read_Latency = "1"; + Is_Enabled = "0"; + } + } + SIMULATION + { + DISPLAY + { + SIGNAL a + { + name = "chipselect"; + conditional = "1"; + } + SIGNAL b + { + name = "write"; + conditional = "1"; + } + SIGNAL c + { + name = "address"; + radix = "hexadecimal"; + } + SIGNAL d + { + name = "byteenable"; + radix = "binary"; + conditional = "1"; + } + SIGNAL e + { + name = "readdata"; + radix = "hexadecimal"; + } + SIGNAL f + { + name = "writedata"; + radix = "hexadecimal"; + conditional = "1"; + } + } + } + PORT_WIRING + { + } + } + MODULE jtag_uart_0 + { + class = "altera_avalon_jtag_uart"; + class_version = "1.0"; + iss_model_name = "altera_avalon_jtag_uart"; + SLAVE avalon_jtag_slave + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Printable_Device = "1"; + Address_Alignment = "native"; + Address_Width = "1"; + Data_Width = "32"; + Has_IRQ = "1"; + Read_Wait_States = "peripheral_controlled"; + Write_Wait_States = "peripheral_controlled"; + JTAG_Hub_Base_Id = "0x04006E"; + JTAG_Hub_Instance_Id = "0"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "2"; + } + Base_Address = "0x08000000"; + } + PORT_WIRING + { + PORT clk + { + type = "clk"; + direction = "input"; + width = "1"; + } + PORT rst_n + { + type = "reset_n"; + direction = "input"; + width = "1"; + } + PORT av_chipselect + { + type = "chipselect"; + direction = "input"; + width = "1"; + } + PORT av_address + { + type = "address"; + direction = "input"; + width = "1"; + } + PORT av_read_n + { + type = "read_n"; + direction = "input"; + width = "1"; + } + PORT av_readdata + { + type = "readdata"; + direction = "output"; + width = "32"; + } + PORT av_write_n + { + type = "write_n"; + direction = "input"; + width = "1"; + } + PORT av_writedata + { + type = "writedata"; + direction = "input"; + width = "32"; + } + PORT av_waitrequest + { + type = "waitrequest"; + direction = "output"; + width = "1"; + } + PORT av_irq + { + type = "irq"; + direction = "output"; + width = "1"; + } + PORT dataavailable + { + direction = "output"; + type = "dataavailable"; + width = "1"; + } + PORT readyfordata + { + direction = "output"; + type = "readyfordata"; + width = "1"; + } + } + } + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + Iss_Launch_Telnet = "0"; + View + { + Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8 + <br>Read Depth: 64; Read IRQ Threshold: 8"; + MESSAGES + { + } + Is_Collapsed = "1"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + write_depth = "64"; + read_depth = "64"; + write_threshold = "8"; + read_threshold = "8"; + read_char_stream = ""; + showascii = "1"; + read_le = "0"; + write_le = "0"; + } + SIMULATION + { + Fix_Me_Up = ""; + DISPLAY + { + SIGNAL av_chipselect + { + name = "av_chipselect"; + } + SIGNAL av_address + { + name = "av_address"; + radix = "hexadecimal"; + } + SIGNAL av_read_n + { + name = "av_read_n"; + } + SIGNAL av_readdata + { + name = "av_readdata"; + radix = "hexadecimal"; + } + SIGNAL av_write_n + { + name = "av_write_n"; + } + SIGNAL av_writedata + { + name = "av_writedata"; + radix = "hexadecimal"; + } + SIGNAL av_waitrequest + { + name = "av_waitrequest"; + } + SIGNAL av_irq + { + name = "av_irq"; + } + SIGNAL dataavailable + { + name = "dataavailable"; + } + SIGNAL readyfordata + { + name = "readyfordata"; + } + } + INTERACTIVE_IN drive + { + enable = "0"; + file = "_input_data_stream.dat"; + mutex = "_input_data_mutex.dat"; + log = "_in.log"; + rate = "100"; + signals = "temp,list"; + exe = "nios2-terminal"; + } + INTERACTIVE_OUT log + { + enable = "1"; + exe = "perl -- atail-f.pl"; + file = "_output_stream.dat"; + radix = "ascii"; + signals = "temp,list"; + } + } + HDL_INFO + { + Precompiled_Simulation_Library_Files = ""; + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd"; + Synthesis_Only_Files = ""; + } + PORT_WIRING + { + } + } + MODULE timer_0 + { + class = "altera_avalon_timer"; + class_version = "2.1"; + iss_model_name = "altera_avalon_timer"; + SLAVE s1 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Address_Width = "3"; + Data_Width = "16"; + Has_IRQ = "1"; + Read_Wait_States = "1"; + Write_Wait_States = "0"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "1"; + } + Base_Address = "0x08001000"; + } + PORT_WIRING + { + PORT address + { + direction = "input"; + type = "address"; + width = "3"; + } + PORT chipselect + { + direction = "input"; + type = "chipselect"; + width = "1"; + } + PORT clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT irq + { + direction = "output"; + type = "irq"; + width = "1"; + } + PORT readdata + { + direction = "output"; + type = "readdata"; + width = "16"; + } + PORT reset_n + { + direction = "input"; + type = "reset_n"; + width = "1"; + } + PORT write_n + { + direction = "input"; + type = "write_n"; + width = "1"; + } + PORT writedata + { + direction = "input"; + type = "writedata"; + width = "16"; + } + } + } + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + View + { + Settings_Summary = "Timer with 1 ms timeout period."; + MESSAGES + { + } + Is_Collapsed = "1"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + always_run = "0"; + fixed_period = "0"; + snapshot = "1"; + period = "1"; + period_units = "ms"; + reset_output = "0"; + timeout_pulse_output = "0"; + mult = "0.001"; + } + HDL_INFO + { + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.vhd"; + Precompiled_Simulation_Library_Files = ""; + Synthesis_Only_Files = ""; + } + PORT_WIRING + { + } + } + MODULE timer_1 + { + class = "altera_avalon_timer"; + class_version = "2.1"; + iss_model_name = "altera_avalon_timer"; + SLAVE s1 + { + SYSTEM_BUILDER_INFO + { + Bus_Type = "avalon"; + Is_Printable_Device = "0"; + Address_Alignment = "native"; + Address_Width = "3"; + Data_Width = "16"; + Has_IRQ = "1"; + Read_Wait_States = "1"; + Write_Wait_States = "0"; + MASTERED_BY cpu_0/data_master + { + priority = "1"; + } + IRQ_MASTER cpu_0/data_master + { + IRQ_Number = "3"; + } + Base_Address = "0x08002000"; + } + PORT_WIRING + { + PORT address + { + direction = "input"; + type = "address"; + width = "3"; + } + PORT chipselect + { + direction = "input"; + type = "chipselect"; + width = "1"; + } + PORT clk + { + direction = "input"; + type = "clk"; + width = "1"; + } + PORT irq + { + direction = "output"; + type = "irq"; + width = "1"; + } + PORT readdata + { + direction = "output"; + type = "readdata"; + width = "16"; + } + PORT reset_n + { + direction = "input"; + type = "reset_n"; + width = "1"; + } + PORT write_n + { + direction = "input"; + type = "write_n"; + width = "1"; + } + PORT writedata + { + direction = "input"; + type = "writedata"; + width = "16"; + } + } + } + SYSTEM_BUILDER_INFO + { + Instantiate_In_System_Module = "1"; + Is_Enabled = "1"; + View + { + Settings_Summary = "Timer with 1 ms timeout period."; + MESSAGES + { + } + Is_Collapsed = "1"; + } + } + WIZARD_SCRIPT_ARGUMENTS + { + always_run = "0"; + fixed_period = "0"; + snapshot = "1"; + period = "1"; + period_units = "ms"; + reset_output = "0"; + timeout_pulse_output = "0"; + mult = "0.001"; + } + HDL_INFO + { + Simulation_HDL_Files = ""; + Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_1.vhd"; + Precompiled_Simulation_Library_Files = ""; + Synthesis_Only_Files = ""; + } + PORT_WIRING + { + } + } +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.sh b/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.sh new file mode 100755 index 0000000000..c6cf2d36e3 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/nios2_iss.sh @@ -0,0 +1,6 @@ +#!/bin/sh +IOD=jtag_uart_0 +PTF=nios2_iss.ptf +EXE="$1" +# e.g. hello.nxe +nios2-iss -c --stdin=${IOD} --stdout=${IOD} --stderr=${IOD} -f "${EXE}" -p "${PTF}" diff --git a/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/addrconv.c b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/addrconv.c new file mode 100644 index 0000000000..444c1e4d87 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/addrconv.c @@ -0,0 +1,30 @@ +/* Shm_Convert_address + * + * No address range conversion is required. + * + * Input parameters: + * address - address to convert + * + * Output parameters: + * returns - converted address + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <shm_driver.h> + +void *Shm_Convert_address( + void *address +) +{ + return ( address ); +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/getcfg.c b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/getcfg.c new file mode 100644 index 0000000000..fc3b3ba062 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/getcfg.c @@ -0,0 +1,75 @@ +/* void Shm_Get_configuration( localnode, &shmcfg ) + * + * This routine initializes, if necessary, and returns a pointer + * to the Shared Memory Configuration Table for the XXX target. + * + * INPUT PARAMETERS: + * localnode - local node number + * shmcfg - address of pointer to SHM Config Table + * + * OUTPUT PARAMETERS: + * *shmcfg - pointer to SHM Config Table + * +XXX: FIX THE COMMENTS BELOW WHEN THE CPU IS KNOWN + * NOTES: The XYZ does not have an interprocessor interrupt. + * + * The following table illustrates the configuration limitations: + * + * BUS MAX + * MODE ENDIAN NODES + * ========= ====== ======= + * POLLED BIG 2+ + * INTERRUPT **** NOT SUPPORTED **** + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <shm_driver.h> + +/* + * configured if currently polling of interrupt driven + */ + +#define INTERRUPT 0 /* XXX: */ +#define POLLING 1 /* XXX: fix me -- is polling ONLY!!! */ + +shm_config_table BSP_shm_cfgtbl; + +void Shm_Get_configuration( + uint32_t localnode, + shm_config_table **shmcfg +) +{ + BSP_shm_cfgtbl.base = 0x0; + BSP_shm_cfgtbl.length = 1 * MEGABYTE; + BSP_shm_cfgtbl.format = SHM_BIG; + + /* + * Override cause_intr or shm_isr if your target has + * special requirements. + */ + + BSP_shm_cfgtbl.cause_intr = Shm_Cause_interrupt; + +#ifdef NEUTRAL_BIG + BSP_shm_cfgtbl.convert = NULL_CONVERT; +#else + BSP_shm_cfgtbl.convert = CPU_swap_u32; +#endif + + BSP_shm_cfgtbl.poll_intr = POLLED_MODE; + BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.value = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.length = NO_INTERRUPT; + + *shmcfg = &BSP_shm_cfgtbl; +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/lock.c b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/lock.c new file mode 100644 index 0000000000..c0d29adf00 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/lock.c @@ -0,0 +1,84 @@ +/* Shared Memory Lock Routines + * + * This shared memory locked queue support routine need to be + * able to lock the specified locked queue. Interrupts are + * disabled while the queue is locked to prevent preemption + * and deadlock when two tasks poll for the same lock. + * previous level. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <shm_driver.h> + +/* + * Shm_Initialize_lock + * + * Initialize the lock for the specified locked queue. + */ + +void Shm_Initialize_lock( + Shm_Locked_queue_Control *lq_cb +) +{ + lq_cb->lock = LQ_UNLOCKED; +} + +/* void _Shm_Lock( &lq_cb ) + * + * This shared memory locked queue support routine locks the + * specified locked queue. It disables interrupts to prevent + * a deadlock condition. + */ + +void Shm_Lock( + Shm_Locked_queue_Control *lq_cb +) +{ + uint32_t isr_level; + uint32_t *lockptr = (uint32_t*) &lq_cb->lock; + uint32_t lock_value; + + lock_value = 0x80000000; + rtems_interrupt_disable( isr_level ); + + Shm_isrstat = isr_level; + while ( lock_value ) { + asm volatile( "" + : "=r" (lockptr), "=r" (lock_value) + : "0" (lockptr), "1" (lock_value) + ); + /* + * If not available, then may want to delay to reduce load on lock. + */ + + if ( lock_value ) + rtems_bsp_delay( 10 ); /* approximately 10 microseconds */ + } +} + +/* + * Shm_Unlock + * + * Unlock the lock for the specified locked queue. + */ + +void Shm_Unlock( + Shm_Locked_queue_Control *lq_cb +) +{ + uint32_t isr_level; + + lq_cb->lock = SHM_UNLOCK_VALUE; + isr_level = Shm_isrstat; + rtems_interrupt_enable( isr_level ); +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/mpisr.c b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/mpisr.c new file mode 100644 index 0000000000..c5f47933a4 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/shmsupp/mpisr.c @@ -0,0 +1,46 @@ +/* Shm_isr_nobsp() + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <shm_driver.h> + +rtems_isr Shm_isr_nobsp( void ) +{ + /* + * If this routine has to do anything other than the mpisr.c + * found in the generic driver, then copy the contents of the generic + * mpisr.c and augment it to satisfy this particular board. Typically, + * you need to have a board specific mpisr.c when the interrupt + * must be cleared. + * + * If the generic mpisr.c satisifies your requirements, then + * remove this routine from your target's shmsupp/mpisb.c file. + * Then simply install the generic Shm_isr in the Shm_setvec + * routine below. + */ +} + +/* Shm_setvec + * + * This driver routine sets the SHM interrupt vector to point to the + * driver's SHM interrupt service routine. + * + * Input parameters: NONE + * + * Output parameters: NONE + */ + +void Shm_setvec( void ) +{ + /* XXX: FIX ME!!! */ +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.s b/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.s new file mode 100644 index 0000000000..ebadb9e870 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/start/crtnn.s @@ -0,0 +1,45 @@ +/* NIOS2 crtn.asm fix
+ *
+ * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+/* Can't use the original crtn.asm from Altera because it doesn't
+ restore the stack pointer correctly (in 5.1b73, the stack pointer
+ is further decreased by 48 instead of increased). This is named
+ differently (crtnn instead crtn) to make sure it can be picked up
+ using custom gcc specs instead of gcc's crtn. - kawk */
+
+ .section .init
+ ldw ra, 44(sp)
+ ldw r23, 40(sp)
+ ldw r22, 36(sp)
+ ldw r21, 32(sp)
+ ldw r20, 28(sp)
+ ldw r19, 24(sp)
+ ldw r18, 20(sp)
+ ldw r17, 16(sp)
+ ldw r16, 12(sp)
+ ldw fp, 8(sp)
+ addi sp, sp, 48
+ ret
+
+ .section .fini
+ ldw ra, 44(sp)
+ ldw r23, 40(sp)
+ ldw r22, 36(sp)
+ ldw r21, 32(sp)
+ ldw r20, 28(sp)
+ ldw r19, 24(sp)
+ ldw r18, 20(sp)
+ ldw r17, 16(sp)
+ ldw r16, 12(sp)
+ ldw fp, 8(sp)
+ addi sp, sp, 48
+ ret
+
diff --git a/c/src/lib/libbsp/nios2/nios2_iss/start/start.S b/c/src/lib/libbsp/nios2/nios2_iss/start/start.S new file mode 100644 index 0000000000..532c12616e --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/start/start.S @@ -0,0 +1,124 @@ +/* NIOS2 startup code + * + * This is the entry point on reset and when loading the + * executive from a bootloader. + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + + .section .entry + .align 3 + movhi et, %hiadj(start) + addi et, et, %lo(start) + jmp et + + .section .irq + .align 3 + movhi et, %hiadj(_exception_vector) + addi et, et, %lo(_exception_vector) + jmp et + + .section .text + .align 3 + .globl start + .type start,@function + + .extern _exception_vector + +start: + #------------------------------------------------------ + # disable interrupts + wrctl status, zero + wrctl ienable, zero + + #------------------------------------------------------ + # invalidate instruction cache + mov r2, r0 + movhi r3, %hi(__nios2_icache_size) + ori r3, r3, %lo(__nios2_icache_size) +icache_init_loop: + initi r2 + addi r2, r2, __nios2_icache_line_size + bltu r2, r3, icache_init_loop + + #------------------------------------------------------ + # invalidate data cache + mov r2, r0 + movhi r3, %hi(__nios2_dcache_size) + ori r3, r3, %lo(__nios2_dcache_size) +dcache_init_loop: + initd 0(r2) + addi r2, r2, __nios2_dcache_line_size + bltu r2, r3, dcache_init_loop + + #------------------------------------------------------ + # initialize stack pointer + movhi sp, %hiadj(__alt_stack_pointer - 4) + addi sp, sp, %lo(__alt_stack_pointer - 4) + + # initialize global pointer + movhi gp, %hiadj(_gp) + addi gp, gp, %lo(_gp) + + # initialize exception tmp register + movhi et, %hiadj(_end) + addi et, et, %lo(_end) + + #------------------------------------------------------ + # TODO: copy data from flash to RAM, if not there already + # For now its save to assume it is there already when we're + # loading code though JTAG into RAM-only system + + # at least copy exception code to right place + movhi r2, %hiadj(__ram_exceptions_start) + addi r2, r2, %lo(__ram_exceptions_start) + + movhi r3, %hiadj(brto_ev) + addi r3, r3, %lo(brto_ev) + ldw r4, 0(r3) + stw r4, 0(r2) + ldw r4, 4(r3) + stw r4, 4(r2) + ldw r4, 8(r3) + stw r4, 8(r2) + ldw r4, 12(r3) + stw r4, 12(r2) + + #------------------------------------------------------ + # clear bss + movhi r2, %hiadj(__bss_start) + addi r2, r2, %lo(__bss_start) + + movhi r3, %hiadj(__bss_end) + addi r3, r3, %lo(__bss_end) + + beq r2, r3, 1f +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b +1: + #------------------------------------------------------ + # jump to (shared) boot_card (never comes back) + mov r4, zero + mov r5, zero + mov r6, zero + call boot_card + # but just in case it does come back, stick here. +_stuck_in_start: + br _stuck_in_start + + #------------------------------------------------------ + # code to be placed at exception address +brto_ev: + movhi et, %hiadj(_exception_vector) + addi et, et, %lo(_exception_vector) + jmp et + + diff --git a/c/src/lib/libbsp/nios2/nios2_iss/startup/bspclean.c b/c/src/lib/libbsp/nios2/nios2_iss/startup/bspclean.c new file mode 100644 index 0000000000..b38f0e1d57 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/startup/bspclean.c @@ -0,0 +1,31 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * Derived from no_cpu/no_bsp/startup/bspclean.c 1.7. + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <rtems/score/cpu.h> + +void bsp_cleanup( void ) +{ + int level; + _CPU_ISR_Disable(level); + for(;;); +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/startup/bspstart.c b/c/src/lib/libbsp/nios2/nios2_iss/startup/bspstart.c new file mode 100644 index 0000000000..8317b59516 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/startup/bspstart.c @@ -0,0 +1,143 @@ +/* + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * Derived from no_cpu/no_bsp/startup/bspstart.c 1.23. + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <string.h> + +#include <bsp.h> +#include <rtems/libio.h> +#include <rtems/libcsupport.h> + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +/* + * Use the shared implementations of the following routines + */ + +extern void bsp_postdriver_hook(void); +extern void bsp_libc_init( void *, uint32_t, int ); +extern rtems_configuration_table BSP_Configuration; + +#if 0 +extern char _RAMBase[]; +extern char _RAMSize[]; +extern char _WorkspaceBase[]; +extern char _HeapSize[]; +#else +extern char __alt_heap_start[]; +#endif + +/* + * Function: bsp_pretasking_hook + * Created: 95/03/10 + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void bsp_pretasking_hook(void) +{ + unsigned long heapStart; +#if 0 + unsigned long heapSize = (unsigned long)_HeapSize; +#endif + unsigned long ramSpace; + + heapStart = (unsigned long)BSP_Configuration.work_space_start + + BSP_Configuration.work_space_size; + + if (heapStart & (CPU_ALIGNMENT-1)) + heapStart = (heapStart + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + +#if 0 + ramSpace = (unsigned long)_RAMBase + (unsigned long)_RAMSize - heapStart; +#else +#if 0 + ramSpace = SRAM_0_BASE + + (SRAM_0_SRAM_MEMORY_SIZE * SRAM_0_SRAM_MEMORY_UNITS) + - heapStart; +#else + ramSpace = RAM_BASE + RAM_BYTES - heapStart; +#endif +#endif + + /* TODO */ + ramSpace -= 16384; /* Space for initial stack, not to be zeroed */ + +#if 0 + if (heapSize < 10) + heapSize = ramSpace; + else if (heapSize > ramSpace) + rtems_fatal_error_occurred (('H'<<24) | ('E'<<16) | ('A'<<8) | 'P'); + + bsp_libc_init((void *)heapStart, heapSize, 0); +#else + bsp_libc_init((void *)heapStart, ramSpace, 0); +#endif + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + +/* + * bsp_start + * + * This routine does the bulk of the system initialization. + */ + +void bsp_start( void ) +{ + /* Fixed */ + + BSP_Configuration.microseconds_per_tick = 1000; + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + +#if 0 + BSP_Configuration.work_space_start = (void *)_WorkspaceBase; +#else + BSP_Configuration.work_space_start = (void *)__alt_heap_start; +#endif + + /* + * initialize the CPU table for this BSP + */ + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.postdriver_hook = bsp_postdriver_hook; + Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/startup/linkcmds b/c/src/lib/libbsp/nios2/nios2_iss/startup/linkcmds new file mode 100644 index 0000000000..7128baf9c2 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/startup/linkcmds @@ -0,0 +1,331 @@ +/* generated.x + * + * Machine generated for a CPU named "cpu_0" as defined in: + * D:\eb2_nios2\kawkos.ptf + * + * Generated: 2005-07-10 11:52:46.899 + * + */ + +/* + +DO NOT MODIFY THIS FILE + + Changing this file will have subtle consequences + which will almost certainly lead to a nonfunctioning + system. If you do modify this file, be aware that your + changes will be overwritten and lost when this file + is generated again. + +DO NOT MODIFY THIS FILE + +*/ + +MEMORY +{ + reset : ORIGIN = 0x00000000, LENGTH = 0x00000600 + exceptions : ORIGIN = 0x00000600, LENGTH = 0x00000A00 + onchip_memory_0 : ORIGIN = 0x00001000, LENGTH = 0x007FF000 +} + + /* Define symbols for each memory base-address */ + __alt_mem_onchip_memory_0 = 0x00000000 ; + + __nios2_icache_size = 4096 ; + __nios2_icache_line_size = 32 ; + __nios2_dcache_size = 0 ; + __nios2_dcache_line_size = 4 ; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* Do we need any of these for elf? + __DYNAMIC = 0; + */ + +SECTIONS +{ + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + *(.irq) + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > exceptions + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* Special FreeBSD sysctl sections. */ + . = ALIGN (16); + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = ABSOLUTE(.); + *(set_domain_*); + *(set_pseudo_*); + +/* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(32 / 8); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(32 / 8); + } > onchip_memory_0 = 0x3a880100 /* NOP on Nios2 (big endian) */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(32 / 8); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(32 / 8); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > onchip_memory_0 + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + .rwdata : + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(32 / 8); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(32 / 8); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > onchip_memory_0 + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + .bss : + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(32 / 8); + __bss_end = ABSOLUTE(.); + } > onchip_memory_0 + + /* + * One output section for each of the available partitions. These are not + * used by default, but can be used by users applications using the .section + * directive. + * + * The memory partition used for the heap is treated in special way, i.e. a + * symbol is added to point to the heap start. + * + * Note that when running from flash, these sections are not loaded by the + * HAL. + * + */ + + .onchip_memory_0 : + { + PROVIDE (_alt_partition_onchip_memory_0_start = ABSOLUTE(.)); + *(.onchip_memory_0 .onchip_memory_0.*) + . = ALIGN(32 / 8); + PROVIDE (_alt_partition_onchip_memory_0_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + + } > onchip_memory_0 + + PROVIDE (_alt_partition_onchip_memory_0_load_addr = LOADADDR(.onchip_memory_0)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x00800000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = _end ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); + diff --git a/c/src/lib/libbsp/nios2/nios2_iss/startup/main.c b/c/src/lib/libbsp/nios2/nios2_iss/startup/main.c new file mode 100644 index 0000000000..4e28f28fe2 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/startup/main.c @@ -0,0 +1,39 @@ +/* main() + * + * This is the entry point for the application. It calls + * the bsp_start routine to the actual dirty work. + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * Derived from no_cpu/no_bsp/startup/main.c 1.9, + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +int main( + int argc, + char **argv, + char **environp +) +{ + extern void bsp_start( int, char**, char ** ); + + bsp_start( argc, argv, environp ); + + /* + * May be able to return to the "crt/start.s" code but also + * may not be able to. Do something here which is board dependent. + */ + + rtems_fatal_error_occurred( 0 ); + + return 0; /* just to satisfy the native compiler */ +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/startup/setvec.c b/c/src/lib/libbsp/nios2/nios2_iss/startup/setvec.c new file mode 100644 index 0000000000..a35618a8c5 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/startup/setvec.c @@ -0,0 +1,44 @@ +/* set_vector + * + * This routine installs an interrupt vector on the target Board/CPU. + * This routine is allowed to be as board dependent as necessary. + * + * INPUT: + * handler - interrupt handler entry point + * vector - vector number + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * Derived from no_cpu/no_bsp/startup/setvec.c 1.8, + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +nios2_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +) +{ + nios2_isr_entry previous_isr; + + if ( type ) + rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); + else { + /* XXX: install non-RTEMS ISR as "raw" interupt */ + } + return previous_isr; +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/timer/timer.c b/c/src/lib/libbsp/nios2/nios2_iss/timer/timer.c new file mode 100644 index 0000000000..18ddb2bf4f --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/timer/timer.c @@ -0,0 +1,151 @@ +/* timer.c + * + * This file manages the benchmark timer used by the RTEMS Timing Test + * Suite. Each measured time period is demarcated by calls to + * Timer_initialize() and Read_timer(). Read_timer() usually returns + * the number of microseconds since Timer_initialize() exitted. + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 2005-2006 Kolja Waschk rtemsdev/ixo.de + * Derived from no_cpu/no_bsp/timer/timer.c 1.9, + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#define TIMER_WRAPS_AFTER_1MS 0 + +#include <rtems.h> +#include <rtems/score/cpu.h> +#include <bsp.h> + +volatile uint32_t Timer_interrupts; +rtems_boolean Timer_driver_Find_average_overhead; + +#define TIMER_REGS ((altera_avalon_timer_regs*)NIOS2_IO_BASE(TIMER_BASE)) + +void timerisr( void ) +{ + TIMER_REGS->status = 0; + Timer_interrupts++; +} + +void Timer_initialize( void ) +{ + uint32_t old_ie; + + /* Disable timer interrupt, stop timer */ + + TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_STOP_MSK; + + set_vector((nios2_isr_entry *)timerisr, TIMER_VECTOR, 1); + + /* Enable interrupt processing */ + + NIOS2_IENABLE(1 << TIMER_VECTOR); + +#if TIMER_WRAPS_AFTER_1MS + /* Writing to periodl/h resets the counter and eventually + stops it. If the timer hasn't been configured with fixed + period, set it to 1 ms now */ + + TIMER_REGS->period_hi = (TIMER_FREQ/1000)>>16; + TIMER_REGS->period_lo = (TIMER_FREQ/1000)&0xFFFF; +#else + /* Writing to periodl/h resets the counter and eventually + stops it. Set max period */ + + TIMER_REGS->period_hi = 0xFFFF; + TIMER_REGS->period_lo = 0xFFFF; +#endif + + /* For timers that can be stopped, writing to periodl/h + also stopped the timer and we have to manually start it. */ + + TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_ITO_MSK | + ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | + ALTERA_AVALON_TIMER_CONTROL_START_MSK; + + /* This is the most safe place for resetting the overflow + counter - just _after_ we reset the timer. Depending + on the SOPC configuration, the counter may not be + stoppable and it doesn't make sense to assume that + there is any "safe" period before resetting. */ + + Timer_interrupts = 0; +} + +/* + * The following controls the behavior of Read_timer(). + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 2 /* It typically takes 2 microseconds */ + /* to start/stop the timer. */ + +#define LEAST_VALID AVG_OVERHEAD /* Don't trust a value lower than this */ + +int Read_timer( void ) +{ + uint32_t timer_wraps; + uint32_t timer_snap; + uint32_t timer_ticks; + uint32_t total; + uint32_t old_ie; + + /* Hold timer */ + TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_STOP_MSK; + + /* Write to request snapshot of timer value */ + TIMER_REGS->snap_lo = 0; + /* Get snapshot */ + timer_snap = ((TIMER_REGS->snap_hi)<<16) | TIMER_REGS->snap_lo; + timer_wraps = Timer_interrupts; + + /* Restart timer */ + TIMER_REGS->control = ALTERA_AVALON_TIMER_CONTROL_START_MSK; + +#if TIMER_WRAPS_AFTER_1MS + timer_ticks = (TIMER_FREQ / 1000) - 1 - timer_snap; + total = timer_wraps * 1000; +#else + timer_ticks = 0xFFFFFFFF - timer_snap; + total = timer_wraps * 0x80000000 / (TIMER_FREQ / 2000000L); +#endif + total += timer_ticks / (TIMER_FREQ / 1000000L); + + if(total < LEAST_VALID) return 0; + + if(Timer_driver_Find_average_overhead != TRUE) total-= AVG_OVERHEAD; + + return total; +} + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/nios2/nios2_iss/times b/c/src/lib/libbsp/nios2/nios2_iss/times new file mode 100644 index 0000000000..2ac0b9ee22 --- /dev/null +++ b/c/src/lib/libbsp/nios2/nios2_iss/times @@ -0,0 +1,194 @@ +# +# Timing Test Suite Results for the NO_BSP +# +# NOTE: This is just a template. The times are irrelevant since this BSP +# can only be compiled -- not executed. +# +# $Id$ +# + +Board: +CPU: include coprocessor if applicable +Clock Speed: +Memory Configuration: SRAM, DRAM, cache, etc +Wait States: + +Times Reported in: cycles, microseconds, etc +Timer Source: Count Down Timer, on-CPU cycle counter, etc + +Column X: +Column Y: + +# DESCRIPTION A B +== ================================================================= ==== ==== + 1 rtems_semaphore_create 20 + rtems_semaphore_delete 21 + rtems_semaphore_obtain: available 15 + rtems_semaphore_obtain: not available -- NO_WAIT 15 + rtems_semaphore_release: no waiting tasks 16 + + 2 rtems_semaphore_obtain: not available -- caller blocks 62 + + 3 rtems_semaphore_release: task readied -- preempts caller 55 + + 4 rtems_task_restart: blocked task -- preempts caller 77 + rtems_task_restart: ready task -- preempts caller 70 + rtems_semaphore_release: task readied -- returns to caller 25 + rtems_task_create 57 + rtems_task_start 31 + rtems_task_restart: suspended task -- returns to caller 36 + rtems_task_delete: suspended task 47 + rtems_task_restart: ready task -- returns to caller 37 + rtems_task_restart: blocked task -- returns to caller 46 + rtems_task_delete: blocked task 50 + + 5 rtems_task_suspend: calling task 51 + rtems_task_resume: task readied -- preempts caller 49 + + 6 rtems_task_restart: calling task 59 + rtems_task_suspend: returns to caller 18 + rtems_task_resume: task readied -- returns to caller 19 + rtems_task_delete: ready task 50 + + 7 rtems_task_restart: suspended task -- preempts caller 70 + + 8 rtems_task_set_priority: obtain current priority 12 + rtems_task_set_priority: returns to caller 27 + rtems_task_mode: obtain current mode 5 + rtems_task_mode: no reschedule 5 + rtems_task_mode: reschedule -- returns to caller 8 + rtems_task_mode: reschedule -- preempts caller 39 + rtems_task_set_note 13 + rtems_task_get_note 13 + rtems_clock_set 33 + rtems_clock_get 3 + + 9 rtems_message_queue_create 110 + rtems_message_queue_send: no waiting tasks 37 + rtems_message_queue_urgent: no waiting tasks 37 + rtems_message_queue_receive: available 31 + rtems_message_queue_flush: no messages flushed 12 + rtems_message_queue_flush: messages flushed 16 + rtems_message_queue_delete 26 + +10 rtems_message_queue_receive: not available -- NO_WAIT 15 + rtems_message_queue_receive: not available -- caller blocks 62 + +11 rtems_message_queue_send: task readied -- preempts caller 72 + +12 rtems_message_queue_send: task readied -- returns to caller 39 + +13 rtems_message_queue_urgent: task readied -- preempts caller 72 + +14 rtems_message_queue_urgent: task readied -- returns to caller 39 + +15 rtems_event_receive: obtain current events 1 + rtems_event_receive: not available -- NO_WAIT 12 + rtems_event_receive: not available -- caller blocks 56 + rtems_event_send: no task readied 12 + rtems_event_receive: available 12 + rtems_event_send: task readied -- returns to caller 24 + +16 rtems_event_send: task readied -- preempts caller 55 + +17 rtems_task_set_priority: preempts caller 62 + +18 rtems_task_delete: calling task 83 + +19 rtems_signal_catch 9 + rtems_signal_send: returns to caller 15 + rtems_signal_send: signal to self 18 + exit ASR overhead: returns to calling task 22 + exit ASR overhead: returns to preempting task 49 + +20 rtems_partition_create 35 + rtems_region_create 23 + rtems_partition_get_buffer: available 15 + rtems_partition_get_buffer: not available 13 + rtems_partition_return_buffer 18 + rtems_partition_delete 16 + rtems_region_get_segment: available 22 + rtems_region_get_segment: not available -- NO_WAIT 21 + rtems_region_return_segment: no waiting tasks 19 + rtems_region_get_segment: not available -- caller blocks 64 + rtems_region_return_segment: task readied -- preempts caller 74 + rtems_region_return_segment: task readied -- returns to caller 44 + rtems_region_delete 16 + rtems_io_initialize 2 + rtems_io_open 1 + rtems_io_close 1 + rtems_io_read 1 + rtems_io_write 1 + rtems_io_control 1 + +21 rtems_task_ident 149 + rtems_message_queue_ident 145 + rtems_semaphore_ident 156 + rtems_partition_ident 145 + rtems_region_ident 148 + rtems_port_ident 145 + rtems_timer_ident 145 + rtems_rate_monotonic_ident 145 + +22 rtems_message_queue_broadcast: task readied -- returns to caller 42 + rtems_message_queue_broadcast: no waiting tasks 17 + rtems_message_queue_broadcast: task readied -- preempts caller 78 + +23 rtems_timer_create 14 + rtems_timer_fire_after: inactive 22 + rtems_timer_fire_after: active 24 + rtems_timer_cancel: active 15 + rtems_timer_cancel: inactive 13 + rtems_timer_reset: inactive 21 + rtems_timer_reset: active 23 + rtems_timer_fire_when: inactive 34 + rtems_timer_fire_when: active 34 + rtems_timer_delete: active 19 + rtems_timer_delete: inactive 17 + rtems_task_wake_when 69 + +24 rtems_task_wake_after: yield -- returns to caller 9 + rtems_task_wake_after: yields -- preempts caller 45 + +25 rtems_clock_tick 4 + +26 _ISR_Disable 0 + _ISR_Flash 1 + _ISR_Enable 1 + _Thread_Disable_dispatch 0 + _Thread_Enable_dispatch 7 + _Thread_Set_state 11 + _Thread_Disptach (NO FP) 31 + context switch: no floating point contexts 21 + context switch: self 10 + context switch: to another task 10 + context switch: restore 1st FP task 25 + fp context switch: save idle, restore idle 31 + fp context switch: save idle, restore initialized 19 + fp context switch: save initialized, restore initialized 20 + _Thread_Resume 7 + _Thread_Unblock 7 + _Thread_Ready 9 + _Thread_Get 4 + _Semaphore_Get 2 + _Thread_Get: invalid id 0 + +27 interrupt entry overhead: returns to interrupted task 6 + interrupt exit overhead: returns to interrupted task 6 + interrupt entry overhead: returns to nested interrupt 6 + interrupt exit overhead: returns to nested interrupt 5 + interrupt entry overhead: returns to preempting task 7 + interrupt exit overhead: returns to preempting task 36 + +28 rtems_port_create 16 + rtems_port_external_to_internal 11 + rtems_port_internal_to_external 11 + rtems_port_delete 16 + +29 rtems_rate_monotonic_create 15 + rtems_rate_monotonic_period: initiate period -- returns to caller 21 + rtems_rate_monotonic_period: obtain status 13 + rtems_rate_monotonic_cancel 16 + rtems_rate_monotonic_delete: inactive 18 + rtems_rate_monotonic_delete: active 20 + rtems_rate_monotonic_period: conclude periods -- caller blocks 53 |