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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-05 14:02:57 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-05 14:02:57 +0000 |
| commit | 133dcd92c99bb5a63ff248a19c6d51d876412444 (patch) | |
| tree | c2f1b2554a0268ab9009ecaf0b6b7ad3bf53e254 /c | |
| parent | Regenerated. (diff) | |
| download | rtems-133dcd92c99bb5a63ff248a19c6d51d876412444.tar.bz2 | |
Patch from Eric Valette <valette@crf.canon.fr> with two small
fixes related to GDB over TCP/IP debug.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S | 8 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S | 8 | ||||
| -rw-r--r-- | c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S | 2 | ||||
| -rw-r--r-- | c/src/librdbg/src/powerpc/rdbg_cpu_asm.S | 2 |
4 files changed, 20 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S index 3d09c16c15..043108155f 100644 --- a/c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S @@ -6,6 +6,10 @@ * found in found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * + * Modified to support the MCP750. + * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * * $Id$ */ @@ -219,6 +223,10 @@ nested: /* * store it at the right place */ + stw r2, GPR1_OFFSET(r1) + /* + * Call High Level signal handling code + */ bl _ISR_Signals_to_thread_executing /* * start restoring exception like frame diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S index 3d09c16c15..043108155f 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S @@ -6,6 +6,10 @@ * found in found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * + * Modified to support the MCP750. + * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * * $Id$ */ @@ -219,6 +223,10 @@ nested: /* * store it at the right place */ + stw r2, GPR1_OFFSET(r1) + /* + * Call High Level signal handling code + */ bl _ISR_Signals_to_thread_executing /* * start restoring exception like frame diff --git a/c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S b/c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S index d45d6b52da..657a279830 100644 --- a/c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S +++ b/c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S @@ -25,6 +25,8 @@ PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache) SYM (copyback_data_cache_and_invalidate_instr_cache): + /* make sure the data changed is in the cache */ + sync /* r3 address to handle, r4 length in bytes */ addi r6, r0, PPC_CACHE_ALIGNMENT /* r5 = last address to handle */ diff --git a/c/src/librdbg/src/powerpc/rdbg_cpu_asm.S b/c/src/librdbg/src/powerpc/rdbg_cpu_asm.S index d45d6b52da..657a279830 100644 --- a/c/src/librdbg/src/powerpc/rdbg_cpu_asm.S +++ b/c/src/librdbg/src/powerpc/rdbg_cpu_asm.S @@ -25,6 +25,8 @@ PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache) SYM (copyback_data_cache_and_invalidate_instr_cache): + /* make sure the data changed is in the cache */ + sync /* r3 address to handle, r4 length in bytes */ addi r6, r0, PPC_CACHE_ALIGNMENT /* r5 = last address to handle */ |