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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-10-16 17:14:38 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-10-16 17:14:38 +0000 |
| commit | 814986ce3e39531cb73c8ea248188aa0a6828d40 (patch) | |
| tree | d5e4f9453dc27c3b32554365695c17897889acec /c | |
| parent | 2007-10-15 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
| download | rtems-814986ce3e39531cb73c8ea248188aa0a6828d40.tar.bz2 | |
2007-10-14 Eric Norum <norume@aps.anl.gov>
* clock/clock.c: Add nanoseconds since tick support.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/m68k/uC5282/ChangeLog | 4 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/uC5282/clock/clock.c | 25 |
2 files changed, 23 insertions, 6 deletions
diff --git a/c/src/lib/libbsp/m68k/uC5282/ChangeLog b/c/src/lib/libbsp/m68k/uC5282/ChangeLog index 4ab6ccbe4e..8d09523178 100644 --- a/c/src/lib/libbsp/m68k/uC5282/ChangeLog +++ b/c/src/lib/libbsp/m68k/uC5282/ChangeLog @@ -1,3 +1,7 @@ +2007-10-14 Eric Norum <norume@aps.anl.gov> + + * clock/clock.c: Add nanoseconds since tick support. + 2007-05-03 Joel Sherrill <joel@OARcorp.com> * startup/linkcmds: Handle .data.* sections diff --git a/c/src/lib/libbsp/m68k/uC5282/clock/clock.c b/c/src/lib/libbsp/m68k/uC5282/clock/clock.c index 25a3043d81..37e623ee34 100644 --- a/c/src/lib/libbsp/m68k/uC5282/clock/clock.c +++ b/c/src/lib/libbsp/m68k/uC5282/clock/clock.c @@ -30,8 +30,19 @@ extern int __SRAMBASE[]; #define IDLE_COUNTER __SRAMBASE[0] #define FILTERED_IDLE __SRAMBASE[1] #define MAX_IDLE_COUNT __SRAMBASE[2] +#define PCNTR_AT_TICK (*(uint16 *)&__SRAMBASE[3]) #define FILTER_SHIFT 6 +uint32_t bsp_clock_nanoseconds_since_last_tick(void) +{ + int i = MCF5282_PIT3_PCNTR; + if (MCF5282_PIT3_PCSR & MCF5282_PIT_PCSR_PIF) + i = MCF5282_PIT3_PCNTR + MCF5282_PIT3_PMR; + return (i - PCNTR_AT_TICK) * 1000; +} + +#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick + /* * Periodic interval timer interrupt handler */ @@ -42,14 +53,15 @@ extern int __SRAMBASE[]; if (idle > MAX_IDLE_COUNT) \ MAX_IDLE_COUNT = idle; \ FILTERED_IDLE = idle + FILTERED_IDLE - (FILTERED_IDLE>>FILTER_SHIFT);\ + PCNTR_AT_TICK = MCF5282_PIT3_PCNTR; \ MCF5282_PIT3_PCSR |= MCF5282_PIT_PCSR_PIF; \ } while (0) /* * Attach clock interrupt handler */ -#define Clock_driver_support_install_isr( _new, _old ) \ - do { \ +#define Clock_driver_support_install_isr( _new, _old ) \ + do { \ _old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \ } while(0) @@ -84,17 +96,18 @@ extern int __SRAMBASE[]; MCF5282_INTC_ICR_IP(PIT3_IRQ_PRIORITY); \ rtems_interrupt_disable( level ); \ MCF5282_INTC0_IMRH &= ~MCF5282_INTC_IMRH_INT58; \ - MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ + MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ rtems_interrupt_enable( level ); \ - MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ + MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ MCF5282_PIT_PCSR_OVW | \ MCF5282_PIT_PCSR_PIE | \ MCF5282_PIT_PCSR_RLD; \ - MCF5282_PIT3_PMR = BSP_Configuration.microseconds_per_tick - 1; \ - MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ + MCF5282_PIT3_PMR = BSP_Configuration.microseconds_per_tick - 1; \ + MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ MCF5282_PIT_PCSR_PIE | \ MCF5282_PIT_PCSR_RLD | \ MCF5282_PIT_PCSR_EN; \ + PCNTR_AT_TICK = MCF5282_PIT3_PCNTR; \ } while (0) /* |