diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-30 16:52:23 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-30 16:52:23 +0000 |
| commit | 125d4c61b7cb38d0b4c12dc524918eaf8fc2d38d (patch) | |
| tree | 783b11226959a4afb6673eb8611488a8cc0d7c65 /c | |
| parent | 2007-11-30 Daniel Hellstrom <daniel@gaisler.com> (diff) | |
| download | rtems-125d4c61b7cb38d0b4c12dc524918eaf8fc2d38d.tar.bz2 | |
2007-11-30 Daniel Hellstrom <daniel@gaisler.com>
* shared/can/occan.c: LEON2/3 OCCAN CAN driver. Fixes typecast to
volatile integer where needed. Fixes bug where closing the driver and
opening it again could make the driver not starting transmission due
to the software fifo was not cleared.
Diffstat (limited to 'c')
| -rw-r--r-- | c/src/lib/libbsp/sparc/ChangeLog | 7 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/can/occan.c | 18 |
2 files changed, 23 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/sparc/ChangeLog b/c/src/lib/libbsp/sparc/ChangeLog index 81c8350043..76c706e294 100644 --- a/c/src/lib/libbsp/sparc/ChangeLog +++ b/c/src/lib/libbsp/sparc/ChangeLog @@ -1,5 +1,12 @@ 2007-11-30 Daniel Hellstrom <daniel@gaisler.com> + * shared/can/occan.c: LEON2/3 OCCAN CAN driver. Fixes typecast to + volatile integer where needed. Fixes bug where closing the driver and + opening it again could make the driver not starting transmission due + to the software fifo was not cleared. + +2007-11-30 Daniel Hellstrom <daniel@gaisler.com> + * shared/can/grcan.c, shared/can/grcan_rasta.c, shared/include/ambapp.h: GRCAN CAN driver. Fixes Interrupt enabling/disabling in the driver, interrupt may not be restored diff --git a/c/src/lib/libbsp/sparc/shared/can/occan.c b/c/src/lib/libbsp/sparc/shared/can/occan.c index 66e27f2a4b..2a62f586f5 100644 --- a/c/src/lib/libbsp/sparc/shared/can/occan.c +++ b/c/src/lib/libbsp/sparc/shared/can/occan.c @@ -253,6 +253,7 @@ static int occan_fifo_full(occan_fifo *fifo); static int occan_fifo_empty(occan_fifo *fifo); static void occan_fifo_get(occan_fifo *fifo); static CANMsg *occan_fifo_claim_get(occan_fifo *fifo); +static void occan_fifo_clr(occan_fifo *fifo); /**** Hardware related Interface ****/ static int occan_calc_speedregs(unsigned int clock_hz, unsigned int rate, occan_speed_regs *result); @@ -288,7 +289,7 @@ static unsigned int sys_freq_hz; /* Read byte bypassing */ #ifdef OCCAN_DONT_BYPASS_CACHE - #define READ_REG(address) (*(unsigned char *)(address)) + #define READ_REG(address) (*(volatile unsigned char *)(address)) #else /* Bypass cache */ #define READ_REG(address) _OCCAN_REG_READ((unsigned int)(address)) @@ -302,7 +303,7 @@ static unsigned int sys_freq_hz; } #endif -#define WRITE_REG(address,data) (*(unsigned char *)(address) = (data)) +#define WRITE_REG(address,data) (*(volatile unsigned char *)(address) = (data)) /* Mode register bit definitions */ #define PELICAN_MOD_RESET 0x1 @@ -439,6 +440,12 @@ static int pelican_start(occan_priv *priv){ if ( !priv->rxfifo || !priv->txfifo ) return -1; + /* In case we were started before and stopped we + * should empty the TX fifo or try to resend those + * messages. We make it simple... + */ + occan_fifo_clr(priv->txfifo); + /* Clear status bits */ priv->status = 0; @@ -1904,4 +1911,11 @@ static void occan_fifo_get(occan_fifo *fifo){ fifo->tail = (fifo->tail >= &fifo->base[fifo->cnt-1])? fifo->base : fifo->tail+1; fifo->full = 0; } + +static void occan_fifo_clr(occan_fifo *fifo){ + fifo->full = 0; + fifo->ovcnt = 0; + fifo->head = fifo->tail = fifo->base; +} + /*******************************************************************************/ |