2005-09-12 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>

	PR 822/bsps
	* console/console.c, startup/bspstart.c, startup/imbx8xx.c,
	startup/mmutlbtab.c, startup/start.S, vectors/vectors_init.c:
	Currently the MBX8xx BSP does not boot, because some logical errors
	are in the startup code. Additionally, the mpc8xx shared clock driver
	does not support the clocking scheme of some of the board variants,
	which are clocked from a 32768Hz (!) external crystal.

7 files changed, 104 insertions, 15 deletions

diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
index d9472f41a8..dcdbadf8c2 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
@@ -1,3 +1,13 @@
+2005-09-12	Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
+
+	PR 822/bsps
+	* console/console.c, startup/bspstart.c, startup/imbx8xx.c,
+	startup/mmutlbtab.c, startup/start.S, vectors/vectors_init.c:
+	Currently the MBX8xx BSP does not boot, because some logical errors
+	are in the startup code. Additionally, the mpc8xx shared clock driver
+	does not support the clocking scheme of some of the board variants,
+	which are clocked from a 32768Hz (!) external crystal.
+
 2003-12-29	Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
 	* startup/Makefile.am: start.S instead of start.s.
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c
index 126c7b073a..953e8e10f0 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c
@@ -542,6 +542,13 @@ serial_init()
 	unsigned int		dpaddr, memaddr;
 	bd_t	*bd;
 
+#if NVRAM_CONFIGURE == 1
+	if ( ((nvram->console_mode & 0x06) != 0x04 ) || 
+	     ((nvram->console_mode & 0x30) != 0x20 )) {
+	  /*
+	   * FIXME: refine this condition...
+	   */
+#endif
 	bd = eppcbugInfo;
 	
 	cp = cpmp;
@@ -647,7 +654,26 @@ serial_init()
 	/* Enable transmitter/receiver.
 	*/
 	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+#if NVRAM_CONFIGURE == 1
+	}
+	else {
+	  const char bootmsg_text[]= "using EPPC bug for console I/O\n";
+	  _EPPCBug_pollWrite((nvram->console_printk_port & 0x70) >> 4,
+			     bootmsg_text,
+			     sizeof(bootmsg_text)-1);
+	}
+#endif
+#if NVRAM_CONFIGURE == 1
+	if ((nvram->console_mode & 0x30) == 0x20 ) {
+	  BSP_output_char = _BSP_output_char;
+	}
+	else {
+	  BSP_output_char = serial_putchar;
+	}
+#else
+
 	BSP_output_char = serial_putchar;
+#endif
 }
 
 void
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
index ae4f983699..67225d1c4d 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
@@ -148,7 +148,7 @@ void bsp_start(void)
   myCpuRevision = get_ppc_cpu_revision();
 
   mmu_init();
-  
+
   /*
    * Enable instruction and data caches. Do not force writethrough mode.
    */
@@ -201,7 +201,22 @@ void bsp_start(void)
   if( Cpu_table.interrupt_stack_size < 4 * 1024 )
       Cpu_table.interrupt_stack_size = 4 * 1024;
 
-  Cpu_table.clicks_per_usec = 1;  /* for 4MHz extclk */
+#if ( defined(mbx821_001b) ||\ 
+      defined(mbx821_002b) ||\
+      defined(mbx821_003b) ||\
+      defined(mbx821_004b) ||\
+      defined(mbx821_005b) ||\
+      defined(mbx821_006b) ||\
+      defined(mbx860_001b) ||\
+      defined(mbx860_002b) ||\
+      defined(mbx860_003b) ||\
+      defined(mbx860_004b) ||\
+      defined(mbx860_005b) ||\
+      defined(mbx860_006b)) 
+  Cpu_table.clicks_per_usec = 0;  /* for 32768 Hz oscclk */
+#else
+  Cpu_table.clicks_per_usec = 1;  /* for 4MHz oscclk */
+#endif
   Cpu_table.serial_per_sec = 10000000;
   Cpu_table.serial_external_clock = 1;
   Cpu_table.serial_xon_xoff = 0;
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
index a5fbb2842c..4a6bb7cfca 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c
@@ -271,6 +271,7 @@ void _InitMBX8xx (void)
   m8xx.sccrk = M8xx_UNLOCK_KEY;		/* unlock SCCR */
   m8xx.sccr = 0x02800000;		/* for MBX860/MBX821 */
 
+#if 0 /* IMD hack: do not init PLL after EPPCbug load */
   /* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
   /* - set the clock speed and set normal power mode */
   m8xx.plprck = M8xx_UNLOCK_KEY;	/* unlock PLPRCR */
@@ -301,6 +302,7 @@ void _InitMBX8xx (void)
 #else
 #error "MBX board not defined"  
 #endif
+#endif
   /* Unlock the timebase and decrementer registers. */
   m8xx.tbk = M8xx_UNLOCK_KEY;
   /* 
@@ -316,6 +318,7 @@ void _InitMBX8xx (void)
   _mtspr( M8xx_TBU_WR, r1 );
   _mtspr( M8xx_TBL_WR, r1 );
 
+#if 0 /* IMD hack: do not init UPMs after EPPCbug load */
   /*
    * Memory Controller Initialization
    */
@@ -584,6 +587,7 @@ void _InitMBX8xx (void)
 #endif
   m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 |
 		M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
+#endif /* IMD hack */
   /*
    * PCMCIA initialization
    */
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
index a252f7d1ac..60377e7685 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c
@@ -31,19 +31,8 @@
  * location is equal to its real address.
  */
 MMU_TLB_table_t MMU_TLB_table[] = {
-#if ( defined(mbx860_001b) )
-  /*
-	 * DRAM: CS1, Start address 0x00000000, 2M, 
-	 *	ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, 
-	 *	R/W,X for all, no ASID comparison, not cache-inhibited.
-	 *	Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
-	 * EPN		TWC	RPN
-	 */
-  { 0x00000200,	0x05,	0x000009FD },	/* DRAM - PS=512K */
-  { 0x00080200,	0x05,	0x000809FD },	/* DRAM - PS=512K */
-  { 0x00100200,	0x05,	0x001009FD },	/* DRAM - PS=512K */
-  { 0x00180200,	0x05,	0x001809FF },	/* DRAM - PS=512K, cache-inhibited */
-#elif ( defined(mbx860_002b) || \
+#if    ( defined(mbx860_001b) || \
+         defined(mbx860_002b) || \
          defined(mbx860_003b) || \
          defined(mbx821_001b) || \
          defined(mbx821_002b) || \
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
index e009fe3d21..797205c038 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
@@ -244,6 +244,46 @@ spin:
 #define LOADED_BY_EPPCBUG
 #define EARLY_CONSOLE		
 /*
+ * test function:	 blink orange led once
+ */
+#define LEDBLINK_DELAY (5*1000*1000)	
+#define LEDPORT 0xFA100001
+#define LEDMASK 0xf0
+#define LEDON   0x00
+#define LEDOFF  0x08
+		
+	PUBLIC_VAR(ledblink)
+SYM(ledblink):
+	lis	r3,LEDBLINK_DELAY>>16
+ledblink1:	
+	subi	r3,r3,1
+	cmpi	0,1,r3,0
+	bne	ledblink1
+	/*
+	 * turn orange led off
+	 */
+	lis	r3,LEDPORT@ha
+	lbz	r0,LEDPORT@l(r3)
+	andi.	r0,r0,LEDMASK
+	ori	r0,r0,LEDOFF
+	stb	r0,LEDPORT@l(r3)
+	
+	lis	r3,LEDBLINK_DELAY>>16
+ledblink2:	
+	subi	r3,r3,1
+	cmpi	0,1,r3,0
+	bne	ledblink2
+	/*
+	 * turn orange led on
+	 */
+	lis	r3,LEDPORT@ha
+	lbz	r0,LEDPORT@l(r3)
+	andi.	r0,r0,LEDMASK
+	ori	r0,r0,LEDON
+	stb	r0,LEDPORT@l(r3)
+	
+	blr	
+/*
  * Initialization code 
  */
 .startup:	
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c
index 1aaae35f5e..b543ae30d6 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c
@@ -115,6 +115,11 @@ void initialize_exceptions()
     if (!mpc8xx_vector_is_valid (i)) {
       continue;
     }
+#if 0 /* FIXME: refine this condition, leave Syscall for EPPCBug console */
+    if (i == ASM_SYS_VECTOR) {
+      continue;
+    }
+#endif
     exception_table[i].exceptIndex	= i;
     exception_table[i].hdl		= exception_config.defaultRawEntry.hdl;
     exception_table[i].hdl.vector	= i;