diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 15:56:32 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 15:56:32 +0000 |
commit | c243c4923ee763f4ddd9a004ce65975a62152eeb (patch) | |
tree | 5234897399dc2bb69b91d70c17193b25628ec242 /c | |
parent | changed version to 4.5.0-beta3a (diff) | |
download | rtems-c243c4923ee763f4ddd9a004ce65975a62152eeb.tar.bz2 |
Added i960KA support in anticipation is i960 gdb simulator BSP.
Diffstat (limited to 'c')
-rw-r--r-- | c/src/exec/score/cpu/i960/cpu.c | 11 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i960/cpu_asm.S | 2 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i960/rtems/score/cpu.h | 8 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i960/rtems/score/i960.h | 31 |
4 files changed, 40 insertions, 12 deletions
diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c index b33d8e1b03..dba1f3ba56 100644 --- a/c/src/exec/score/cpu/i960/cpu.c +++ b/c/src/exec/score/cpu/i960/cpu.c @@ -17,6 +17,7 @@ #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) #elif defined(__i960RP__) +#elif defined(__i960KA__) #else #warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***" #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***" @@ -71,6 +72,8 @@ unsigned32 _CPU_ISR_Get_level( void ) #elif defined(__i960RP__) #define i960_vector_caching_enabled( _prcb ) \ ((*((unsigned int *) ICON_ADDR)) & 0x2000) +#elif defined(__i960KA__) +#define i960_vector_caching_enabled( _prcb ) 0 /* XXX fix me */ #endif void _CPU_ISR_install_raw_handler( @@ -143,8 +146,7 @@ void _CPU_ISR_install_vector( : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ } -#else -#if defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) +#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP) #define soft_reset( prcb ) \ { register i960_PRCB *_prcb = (prcb); \ register unsigned32 *_next=0; \ @@ -155,7 +157,8 @@ void _CPU_ISR_install_vector( : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ } -#endif +#elif defined(__i960KA__) +#define soft_reset( prcb ) /* XXX fix me */ #endif void _CPU_Install_interrupt_stack( void ) @@ -173,7 +176,9 @@ void _CPU_Install_interrupt_stack( void ) _CPU_ISR_Disable( level ); +#if !defined(__i960_KA__) prcb->intr_stack = _CPU_Interrupt_stack_low; +#endif #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) soft_reset( prcb ); diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S index e990b7a799..171f094bdc 100644 --- a/c/src/exec/score/cpu/i960/cpu_asm.S +++ b/c/src/exec/score/cpu/i960/cpu_asm.S @@ -226,6 +226,7 @@ __ISR_Dispatch: * which are clobbered by the reinit operation. (Not documented, but it happens). */ +#if !defined(__i960KA__) .globl __i960_soft_reset_asm __i960_soft_reset_asm: flushreg # flush register cache @@ -242,3 +243,4 @@ __i960_reset_done: mov r5, pfp mov r6, sp ret +#endif diff --git a/c/src/exec/score/cpu/i960/rtems/score/cpu.h b/c/src/exec/score/cpu/i960/rtems/score/cpu.h index ef7c3ad968..c1f1e7a1e6 100644 --- a/c/src/exec/score/cpu/i960/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/i960/rtems/score/cpu.h @@ -20,7 +20,9 @@ extern "C" { #endif +#if 0 #pragma align 4 /* for GNU C structure alignment */ +#endif #include <rtems/score/i960.h> /* pick up machine definitions */ #ifndef ASM @@ -351,6 +353,11 @@ unsigned32 _CPU_ISR_Get_level( void ); * + scan for the highest numbered (MSB) set in a 16 bit bitfield */ +#if defined(i960gdbsim) + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE +#else #define CPU_USE_GENERIC_BITFIELD_CODE FALSE #define CPU_USE_GENERIC_BITFIELD_DATA FALSE @@ -382,6 +389,7 @@ unsigned32 _CPU_ISR_Get_level( void ); ( 15 - (_priority) ) /* end of Priority handler macros */ +#endif /* functions */ diff --git a/c/src/exec/score/cpu/i960/rtems/score/i960.h b/c/src/exec/score/cpu/i960/rtems/score/i960.h index 644bd18a0b..b43a7df661 100644 --- a/c/src/exec/score/cpu/i960/rtems/score/i960.h +++ b/c/src/exec/score/cpu/i960/rtems/score/i960.h @@ -33,16 +33,15 @@ extern "C" { * NOTE: RTEMS defines a canonical name for each cpu model. */ -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ +#if defined(i960gdbsim) -#define CPU_MODEL_NAME "rtems_multilib" -#define I960_HAS_FPU 0 -#define I960_CPU_ALIGNMENT 4 -#define I960_SOFT_RESET_COMMAND 0x30000 +#define CPU_MODEL_NAME "i960gdbsim" +#define __RTEMS_I960KA__ + +#elif defined(__i960KA__) || defined(__i960_KA__) || defined(__i960KA) + +#define CPU_MODEL_NAME "i960ka" +#define __RTEMS_I960KA__ #elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) @@ -304,6 +303,20 @@ typedef struct { typedef i960rp_control_table i960_control_table; typedef i960rp_PRCB i960_PRCB; +#elif defined(__RTEMS_I960KA__) + +typedef struct { + int fixme; +} i960ka_control_table; + +typedef struct { + void **intr_tbl; /* interrupt table base address */ + unsigned int *intr_stack; /* interrupt stack pointer */ + int fixme; +} i960ka_PRCB; + +typedef i960ka_control_table i960_control_table; +typedef i960ka_PRCB i960_PRCB; #else #error "invalid processor selection!" #endif |