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authorJoel Sherrill <joel@rtems.org>2016-09-05 17:42:27 -0500
committerChris Johns <chrisj@rtems.org>2016-09-06 10:31:16 +1000
commit85910040d8bc7b2031656372042cf993caa90a86 (patch)
tree4bc105f890b1aea92509c19d10e1961fa24e2a8f /c
parentAdd autotools generated files (diff)
downloadrtems-85910040d8bc7b2031656372042cf993caa90a86.tar.bz2
Backport capability to exclude tests from building
Backported build infrastructure and .tcfg files from master.
Diffstat (limited to 'c')
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg10
-rw-r--r--c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg8
-rw-r--r--c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg7
-rw-r--r--c/src/lib/libbsp/m68k/mcf52235/make/custom/mcf52235-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/m68k/mcf5225x/make/custom/mcf5225x-testsuite.tcfg5
-rw-r--r--c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg11
-rw-r--r--c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg11
-rw-r--r--c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg10
-rw-r--r--c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg10
14 files changed, 102 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg
new file mode 100644
index 0000000000..70a1a311a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The GDB ARM Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg
new file mode 100644
index 0000000000..70a1a311a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The GDB ARM Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg
new file mode 100644
index 0000000000..70a1a311a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The GDB ARM Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg
new file mode 100644
index 0000000000..70a1a311a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The GDB ARM Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg
new file mode 100644
index 0000000000..70a1a311a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The GDB ARM Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg
new file mode 100644
index 0000000000..a0b12f04d5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc24xx/make/custom/lpc2362-testsuite.tcfg
@@ -0,0 +1,10 @@
+#
+# The LPC2362 does not have enough memory for some tests to link.
+#
+
+cdtest
+fileio
+flashdisk01
+psx07
+rtems++
+sp09
diff --git a/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg
new file mode 100644
index 0000000000..12ea6664f2
--- /dev/null
+++ b/c/src/lib/libbsp/h8300/h8sim/make/custom/h8sxsim-testsuite.tcfg
@@ -0,0 +1,8 @@
+#
+# Tests to skip for h8sxsim BSP
+#
+
+include: testdata/require-tick-isr.tcfg
+include: testdata/disable-intrcritical-tests.tcfg
+
+flashdisk01
diff --git a/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg b/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg
new file mode 100644
index 0000000000..949e1b1b62
--- /dev/null
+++ b/c/src/lib/libbsp/m32c/m32cbsp/make/custom/m32csim-testsuite.tcfg
@@ -0,0 +1,7 @@
+#
+# The GDB M32C Simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
+
+fileio
diff --git a/c/src/lib/libbsp/m68k/mcf52235/make/custom/mcf52235-testsuite.tcfg b/c/src/lib/libbsp/m68k/mcf52235/make/custom/mcf52235-testsuite.tcfg
new file mode 100644
index 0000000000..dc88198b66
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/mcf52235/make/custom/mcf52235-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# Tests to avoid for the mcf5235 BSP
+#
+
+flashdisk01
diff --git a/c/src/lib/libbsp/m68k/mcf5225x/make/custom/mcf5225x-testsuite.tcfg b/c/src/lib/libbsp/m68k/mcf5225x/make/custom/mcf5225x-testsuite.tcfg
new file mode 100644
index 0000000000..f77a96eb3e
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/mcf5225x/make/custom/mcf5225x-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# tests to avoid for the mcf5225x BSP
+#
+
+flashdisk01
diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg
new file mode 100644
index 0000000000..eb120d976a
--- /dev/null
+++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh1-testsuite.tcfg
@@ -0,0 +1,11 @@
+#
+# simsh1 RTEMS Test Database.
+#
+# Format is one line per test that is _NOT_ built.
+#
+
+include: testdata/require-tick-isr.tcfg
+include: testdata/disable-intrcritical-tests.tcfg
+
+fileio
+iostream
diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg
new file mode 100644
index 0000000000..c66569c3d5
--- /dev/null
+++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2-testsuite.tcfg
@@ -0,0 +1,11 @@
+#
+# simsh2 RTEMS Test Database.
+#
+# Format is one line per test that is _NOT_ built.
+#
+
+include: testdata/require-tick-isr.tcfg
+include: testdata/disable-intrcritical-tests.tcfg
+
+fileio
+iostream
diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg
new file mode 100644
index 0000000000..9d84af285a
--- /dev/null
+++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh2e-testsuite.tcfg
@@ -0,0 +1,10 @@
+#
+# The GDB SH Simulator does not have a tick interrupt
+# and the simsh2e configuration has limited memory.
+#
+
+include: testdata/require-tick-isr.tcfg
+include: testdata/disable-intrcritical-tests.tcfg
+
+fileio
+iostream
diff --git a/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg
new file mode 100644
index 0000000000..3aaf7f67e3
--- /dev/null
+++ b/c/src/lib/libbsp/sh/shsim/make/custom/simsh4-testsuite.tcfg
@@ -0,0 +1,10 @@
+#
+# The GDB SH Simulator does not have a tick interrupt
+# and the simsh4 configuration has limited memory.
+#
+
+include: testdata/require-tick-isr.tcfg
+include: testdata/disable-intrcritical-tests.tcfg
+
+fileio
+iostream