new file for MIPS port by Craig Lebakken (lebakken@minn.net) and

Derrick Ostertag (ostertag@transition.com).

56 files changed, 11603 insertions, 0 deletions

diff --git a/c/src/exec/score/cpu/mips/asm.h b/c/src/exec/score/cpu/mips/asm.h
new file mode 100644
index 0000000000..d5a5d69eaa
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/asm.h
@@ -0,0 +1,99 @@
+/*  asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ *
+ *
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  asm.h,v 1.4 1995/09/26 19:25:36 joel Exp
+ */
+/* @(#)asm.h       03/15/96     1.1 */
+
+#ifndef __NO_CPU_ASM_h
+#define __NO_CPU_ASM_h
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#define ASM
+#include <rtems/score/no_cpu.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+/* ANSI concatenation macros.  */
+
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a ## b
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA
+#define END_DATA
+#define BEGIN_BSS
+#define END_BSS
+#define END
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC(sym) .globl SYM (sym)
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/mips/cpu.c b/c/src/exec/score/cpu/mips/cpu.c
new file mode 100644
index 0000000000..ec8c73393e
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/cpu.c
@@ -0,0 +1,216 @@
+/*
+ *  Mips CPU Dependent Source
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu.c,v 1.7 1995/09/26 19:25:37 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+
+ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ */
+
+
+void null_handler( void )
+{
+}
+
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+   unsigned int i = ISR_NUMBER_OF_VECTORS;
+
+   while ( i-- )
+   {
+      _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler;
+   }
+
+  /*
+   *  The thread_dispatch argument is the address of the entry point
+   *  for the routine called at the end of an ISR once it has been
+   *  decided a context switch is necessary.  On some compilation
+   *  systems it is difficult to call a high-level language routine
+   *  from assembly.  This allows us to trick these systems.
+   *
+   *  If you encounter this problem save the entry point in a CPU
+   *  dependent variable.
+   */
+
+  _CPU_Thread_dispatch_pointer = thread_dispatch;
+
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+
+  _CPU_Table = *cpu_table;
+
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ */
+ 
+#if 0 /* located in cpu_asm.S */
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+}
+#endif
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+
+#if 0 /* not necessary */
+/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
+   add_ext_int_func( vector, new_handler );
+#endif
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ */
+
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+/* we don't support this yet */
+}
+
+/*PAGE
+ *
+ *  _CPU_Internal_threads_Idle_thread_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ */
+
+#if 0 /* located in cpu_asm.S */
+void _CPU_Thread_Idle_body( void )
+{
+
+  for( ; ; )
+    /* insert your "halt" instruction here */ ;
+}
+#endif
+
+extern void mips_break( int error );
+
+#include <stdio.h>
+
+void mips_fatal_error( int error )
+{
+   printf("fatal error 0x%x %d\n",error,error);
+   mips_break( error );
+}
diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S
new file mode 100644
index 0000000000..d9e38231bf
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/cpu_asm.S
@@ -0,0 +1,972 @@
+/*  cpu_asm.S 
+ *
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu_asm.c,v 1.5 1995/09/26 19:25:39 joel Exp
+ */
+/* @(#)cpu_asm.S       08/20/96     1.15 */
+
+#include "cpu_asm.h"
+
+#include "iregdef.h"
+#include "idtcpu.h"
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+        .globl  name;                           \
+        .ent    name;                           \
+name:;                                          \
+        .frame  frm_reg,offset,ret_reg
+#define ENDFRAME(name)                          \
+        .end name
+
+
+#define EXCP_STACK_SIZE (NREGS*R_SZ)
+
+#if __ghs__
+#define sd sw
+#define ld lw
+#define dmtc0 mtc0
+#define dsll sll
+#define dmfc0 mfc0
+#endif
+
+#if 1  /* 32 bit unsigned32 types */
+#define sint sw
+#define lint lw
+#define stackadd addiu
+#define intadd addu
+#define SZ_INT 4
+#define SZ_INT_POW2 2
+#else /* 64 bit unsigned32 types */
+#define sint dw
+#define lint dw
+#define stackadd daddiu
+#define intadd daddu
+#define SZ_INT 8
+#define SZ_INT_POW2 3
+#endif
+
+#ifdef __GNUC__
+#define EXTERN(x,size) .extern x,size
+#else
+#define EXTERN(x,size)
+#endif
+
+/* NOTE: these constants must match the Context_Control structure in cpu.h */
+#define S0_OFFSET 0
+#define S1_OFFSET 1
+#define S2_OFFSET 2
+#define S3_OFFSET 3
+#define S4_OFFSET 4
+#define S5_OFFSET 5
+#define S6_OFFSET 6
+#define S7_OFFSET 7
+#define SP_OFFSET 8
+#define FP_OFFSET 9
+#define RA_OFFSET 10
+#define C0_SR_OFFSET 11
+#define C0_EPC_OFFSET 12
+
+/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
+#define FP0_OFFSET  0 
+#define FP1_OFFSET  1 
+#define FP2_OFFSET  2 
+#define FP3_OFFSET  3 
+#define FP4_OFFSET  4 
+#define FP5_OFFSET  5 
+#define FP6_OFFSET  6 
+#define FP7_OFFSET  7 
+#define FP8_OFFSET  8 
+#define FP9_OFFSET  9 
+#define FP10_OFFSET 10 
+#define FP11_OFFSET 11 
+#define FP12_OFFSET 12 
+#define FP13_OFFSET 13 
+#define FP14_OFFSET 14 
+#define FP15_OFFSET 15 
+#define FP16_OFFSET 16 
+#define FP17_OFFSET 17 
+#define FP18_OFFSET 18 
+#define FP19_OFFSET 19 
+#define FP20_OFFSET 20 
+#define FP21_OFFSET 21 
+#define FP22_OFFSET 22 
+#define FP23_OFFSET 23 
+#define FP24_OFFSET 24 
+#define FP25_OFFSET 25 
+#define FP26_OFFSET 26 
+#define FP27_OFFSET 27 
+#define FP28_OFFSET 28 
+#define FP29_OFFSET 29 
+#define FP30_OFFSET 30 
+#define FP31_OFFSET 31 
+
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ */
+
+#if 0
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+}
+#endif
+/* return the current exception level for the 4650 */
+FRAME(_CPU_ISR_Get_level,sp,0,ra)
+	mfc0 v0,C0_SR
+	nop
+	andi v0,SR_EXL 
+	srl v0,1
+	j ra
+ENDFRAME(_CPU_ISR_Get_level)
+
+FRAME(_CPU_ISR_Set_level,sp,0,ra)
+	nop
+	mfc0 a0,C0_SR
+	nop
+	andi a0,SR_EXL 
+	beqz a0,_CPU_ISR_Set_1		/* normalize a0 */
+	nop
+	li a0,1         
+_CPU_ISR_Set_1:
+	beq v0,a0,_CPU_ISR_Set_exit	/* if (current_level != new_level ) */
+	nop
+	bnez a0,_CPU_ISR_Set_2
+	nop
+	nop
+	mfc0 t0,C0_SR
+	nop
+	li t1,~SR_EXL
+	and t0,t1
+	nop
+	mtc0 t0,C0_SR                   /* disable exception level */
+	nop
+	j ra 
+	nop
+_CPU_ISR_Set_2:
+	nop
+	mfc0 t0,C0_SR
+	nop
+	li t1,~SR_IE
+	and t0,t1
+	nop
+	mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
+	nop
+	ori t0,SR_EXL|SR_IE		/* enable exception level  */
+	nop
+	mtc0 t0,C0_SR         
+	nop
+_CPU_ISR_Set_exit:
+	j ra
+	nop
+ENDFRAME(_CPU_ISR_Set_level)
+
+/*
+ *  _CPU_Context_save_fp_context
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+/* void _CPU_Context_save_fp(
+ * void **fp_context_ptr
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_save_fp,sp,0,ra)
+	.set noat
+	ld a1,(a0)
+	swc1 $f0,FP0_OFFSET*4(a1)
+	swc1 $f1,FP1_OFFSET*4(a1)
+	swc1 $f2,FP2_OFFSET*4(a1)
+	swc1 $f3,FP3_OFFSET*4(a1)
+	swc1 $f4,FP4_OFFSET*4(a1)
+	swc1 $f5,FP5_OFFSET*4(a1)
+	swc1 $f6,FP6_OFFSET*4(a1)
+	swc1 $f7,FP7_OFFSET*4(a1)
+	swc1 $f8,FP8_OFFSET*4(a1)
+	swc1 $f9,FP9_OFFSET*4(a1)
+	swc1 $f10,FP10_OFFSET*4(a1)
+	swc1 $f11,FP11_OFFSET*4(a1)
+	swc1 $f12,FP12_OFFSET*4(a1)
+	swc1 $f13,FP13_OFFSET*4(a1)
+	swc1 $f14,FP14_OFFSET*4(a1)
+	swc1 $f15,FP15_OFFSET*4(a1)
+	swc1 $f16,FP16_OFFSET*4(a1)
+	swc1 $f17,FP17_OFFSET*4(a1)
+	swc1 $f18,FP18_OFFSET*4(a1)
+	swc1 $f19,FP19_OFFSET*4(a1)
+	swc1 $f20,FP20_OFFSET*4(a1)
+	swc1 $f21,FP21_OFFSET*4(a1)
+	swc1 $f22,FP22_OFFSET*4(a1)
+	swc1 $f23,FP23_OFFSET*4(a1)
+	swc1 $f24,FP24_OFFSET*4(a1)
+	swc1 $f25,FP25_OFFSET*4(a1)
+	swc1 $f26,FP26_OFFSET*4(a1)
+	swc1 $f27,FP27_OFFSET*4(a1)
+	swc1 $f28,FP28_OFFSET*4(a1)
+	swc1 $f29,FP29_OFFSET*4(a1)
+	swc1 $f30,FP30_OFFSET*4(a1)
+	swc1 $f31,FP31_OFFSET*4(a1)
+	j ra
+	nop
+	.set at
+ENDFRAME(_CPU_Context_save_fp)
+
+/*
+ *  _CPU_Context_restore_fp_context
+ *
+ *  This routine is responsible for restoring the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+/* void _CPU_Context_restore_fp(
+ * void **fp_context_ptr
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_restore_fp,sp,0,ra)
+	.set noat
+	ld a1,(a0)
+	lwc1 $f0,FP0_OFFSET*4(a1)
+	lwc1 $f1,FP1_OFFSET*4(a1)
+	lwc1 $f2,FP2_OFFSET*4(a1)
+	lwc1 $f3,FP3_OFFSET*4(a1)
+	lwc1 $f4,FP4_OFFSET*4(a1)
+	lwc1 $f5,FP5_OFFSET*4(a1)
+	lwc1 $f6,FP6_OFFSET*4(a1)
+	lwc1 $f7,FP7_OFFSET*4(a1)
+	lwc1 $f8,FP8_OFFSET*4(a1)
+	lwc1 $f9,FP9_OFFSET*4(a1)
+	lwc1 $f10,FP10_OFFSET*4(a1)
+	lwc1 $f11,FP11_OFFSET*4(a1)
+	lwc1 $f12,FP12_OFFSET*4(a1)
+	lwc1 $f13,FP13_OFFSET*4(a1)
+	lwc1 $f14,FP14_OFFSET*4(a1)
+	lwc1 $f15,FP15_OFFSET*4(a1)
+	lwc1 $f16,FP16_OFFSET*4(a1)
+	lwc1 $f17,FP17_OFFSET*4(a1)
+	lwc1 $f18,FP18_OFFSET*4(a1)
+	lwc1 $f19,FP19_OFFSET*4(a1)
+	lwc1 $f20,FP20_OFFSET*4(a1)
+	lwc1 $f21,FP21_OFFSET*4(a1)
+	lwc1 $f22,FP22_OFFSET*4(a1)
+	lwc1 $f23,FP23_OFFSET*4(a1)
+	lwc1 $f24,FP24_OFFSET*4(a1)
+	lwc1 $f25,FP25_OFFSET*4(a1)
+	lwc1 $f26,FP26_OFFSET*4(a1)
+	lwc1 $f27,FP27_OFFSET*4(a1)
+	lwc1 $f28,FP28_OFFSET*4(a1)
+	lwc1 $f29,FP29_OFFSET*4(a1)
+	lwc1 $f30,FP30_OFFSET*4(a1)
+	lwc1 $f31,FP31_OFFSET*4(a1)
+	j ra
+	nop
+	.set at
+ENDFRAME(_CPU_Context_restore_fp)
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ */
+
+/* void _CPU_Context_switch(
+ * Context_Control  *run,
+ * Context_Control  *heir
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_switch,sp,0,ra)
+
+	mfc0 t0,C0_SR
+	li t1,~SR_IE
+	sd t0,C0_SR_OFFSET*8(a0)	/* save status register */
+	and t0,t1
+	mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
+	ori t0,SR_EXL|SR_IE		/* enable exception level to disable interrupts */
+	mtc0 t0,C0_SR
+
+	sd ra,RA_OFFSET*8(a0)           /* save current context */
+	sd sp,SP_OFFSET*8(a0)
+	sd fp,FP_OFFSET*8(a0)
+	sd s0,S0_OFFSET*8(a0)
+	sd s1,S1_OFFSET*8(a0)
+	sd s2,S2_OFFSET*8(a0)
+	sd s3,S3_OFFSET*8(a0)
+	sd s4,S4_OFFSET*8(a0)
+	sd s5,S5_OFFSET*8(a0)
+	sd s6,S6_OFFSET*8(a0)
+	sd s7,S7_OFFSET*8(a0)
+	dmfc0 t0,C0_EPC
+	sd t0,C0_EPC_OFFSET*8(a0)
+
+_CPU_Context_switch_restore:
+	ld s0,S0_OFFSET*8(a1)		/* restore context */
+	ld s1,S1_OFFSET*8(a1)
+	ld s2,S2_OFFSET*8(a1)
+	ld s3,S3_OFFSET*8(a1)
+	ld s4,S4_OFFSET*8(a1)
+	ld s5,S5_OFFSET*8(a1)
+	ld s6,S6_OFFSET*8(a1)
+	ld s7,S7_OFFSET*8(a1)
+	ld fp,FP_OFFSET*8(a1) 
+	ld sp,SP_OFFSET*8(a1)
+	ld ra,RA_OFFSET*8(a1)
+	ld t0,C0_EPC_OFFSET*8(a1)
+	dmtc0 t0,C0_EPC
+	ld t0,C0_SR_OFFSET*8(a1)
+	andi t0,SR_EXL
+	bnez t0,_CPU_Context_1		/* set exception level from restore context */
+	li t0,~SR_EXL
+	mfc0 t1,C0_SR
+	nop
+	and t1,t0
+	mtc0 t1,C0_SR
+_CPU_Context_1:
+	j ra
+	nop
+ENDFRAME(_CPU_Context_switch)
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ */
+
+#if 0
+void _CPU_Context_restore(
+  Context_Control *new_context
+)
+{
+}
+#endif
+
+FRAME(_CPU_Context_restore,sp,0,ra)
+	dadd a1,a0,zero
+	j _CPU_Context_switch_restore
+	nop
+ENDFRAME(_CPU_Context_restore)
+
+EXTERN(_ISR_Nest_level, SZ_INT)
+EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
+EXTERN(_Context_Switch_necessary,SZ_INT)
+EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
+.extern _Thread_Dispatch
+.extern _ISR_Vector_table
+
+/*  void __ISR_Handler()
+ *
+ *  This routine provides the RTEMS interrupt management.
+ *
+ */
+
+#if 0
+void _ISR_Handler()
+{
+   /*
+    *  This discussion ignores a lot of the ugly details in a real
+    *  implementation such as saving enough registers/state to be
+    *  able to do something real.  Keep in mind that the goal is
+    *  to invoke a user's ISR handler which is written in C and
+    *  uses a certain set of registers.
+    *
+    *  Also note that the exact order is to a large extent flexible.
+    *  Hardware will dictate a sequence for a certain subset of
+    *  _ISR_Handler while requirements for setting
+    */
+
+  /*
+   *  At entry to "common" _ISR_Handler, the vector number must be
+   *  available.  On some CPUs the hardware puts either the vector
+   *  number or the offset into the vector table for this ISR in a
+   *  known place.  If the hardware does not give us this information,
+   *  then the assembly portion of RTEMS for this port will contain
+   *  a set of distinct interrupt entry points which somehow place
+   *  the vector number in a known place (which is safe if another
+   *  interrupt nests this one) and branches to _ISR_Handler.
+   *
+   */
+#endif
+FRAME(_ISR_Handler,sp,0,ra)
+.set noreorder
+#if USE_IDTKIT
+/* IDT/Kit incorrectly adds 4 to EPC before returning.  This compensates */
+	lreg    k0, R_EPC*R_SZ(sp)
+	daddiu    k0,k0,-4
+	sreg    k0, R_EPC*R_SZ(sp)
+	lreg    k0, R_CAUSE*R_SZ(sp)
+	li	k1, ~CAUSE_BD
+	and     k0, k1 
+	sreg    k0, R_CAUSE*R_SZ(sp)
+#endif
+	
+/* save registers not already saved by IDT/sim */
+	stackadd sp,sp,-EXCP_STACK_SIZE /* store ra on the stack */
+
+	sreg    ra, R_RA*R_SZ(sp)
+	sreg    v0, R_V0*R_SZ(sp)
+	sreg    v1, R_V1*R_SZ(sp)
+	sreg    a0, R_A0*R_SZ(sp)
+	sreg    a1, R_A1*R_SZ(sp)
+	sreg    a2, R_A2*R_SZ(sp)
+	sreg    a3, R_A3*R_SZ(sp)
+	sreg    t0, R_T0*R_SZ(sp)
+	sreg    t1, R_T1*R_SZ(sp)
+	sreg    t2, R_T2*R_SZ(sp)
+	sreg    t3, R_T3*R_SZ(sp)
+	sreg    t4, R_T4*R_SZ(sp)
+	sreg    t5, R_T5*R_SZ(sp)
+	sreg    t6, R_T6*R_SZ(sp)
+	sreg    t7, R_T7*R_SZ(sp)
+	mflo    k0
+	sreg    t8, R_T8*R_SZ(sp)
+	sreg    k0, R_MDLO*R_SZ(sp)
+	sreg    t9, R_T9*R_SZ(sp)
+	mfhi    k0
+	sreg    gp, R_GP*R_SZ(sp)
+	sreg    fp, R_FP*R_SZ(sp)
+	sreg    k0, R_MDHI*R_SZ(sp)
+	.set noat
+	sreg    AT, R_AT*R_SZ(sp)
+	.set at
+
+	stackadd sp,sp,-40		/* store ra on the stack */
+	sd ra,32(sp)
+
+/* determine if an interrupt generated this exception */
+	mfc0 k0,C0_CAUSE
+	and k1,k0,CAUSE_EXCMASK
+	bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */
+	mfc0 k1,C0_SR
+	and k0,k1
+	and k0,CAUSE_IPMASK
+	beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */
+	nop
+
+  /*
+   *  save some or all context on stack
+   *  may need to save some special interrupt information for exit
+   *
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if ( _ISR_Nest_level == 0 )
+   *      switch to software interrupt stack
+   *  #endif
+   */
+#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+	lint t0,_ISR_Nest_level
+	beq t0, zero,  _ISR_Handler_1
+	nop
+	/* switch stacks */	
+_ISR_Handler_1:
+#else
+	lint t0,_ISR_Nest_level
+#endif
+  /*
+   *  _ISR_Nest_level++;
+   */
+	addi t0,t0,1
+	sint t0,_ISR_Nest_level
+  /*
+   *  _Thread_Dispatch_disable_level++;
+   */
+	lint t1,_Thread_Dispatch_disable_level
+	addi t1,t1,1
+	sint t1,_Thread_Dispatch_disable_level
+#if 0
+	nop
+	j _ISR_Handler_4
+	nop
+  /*
+   *  while ( interrupts_pending(cause_reg) ) {
+   *     vector = BITFIELD_TO_INDEX(cause_reg);
+   *     (*_ISR_Vector_table[ vector ])( vector );
+   *  }
+   */
+_ISR_Handler_2:
+/* software interrupt priorities can be applied here */
+	li t1,-1
+/* convert bit field into interrupt index */
+_ISR_Handler_3:
+	andi t2,t0,1
+	addi t1,1
+	beql t2,zero,_ISR_Handler_3
+	dsrl t0,1
+	li t1,7
+	dsll t1,3			/* convert index to byte offset (*8) */
+	la t3,_ISR_Vector_table
+	intadd t1,t3
+	lint t1,(t1)
+	jalr t1
+	nop
+	j _ISR_Handler_5
+	nop
+_ISR_Handler_4:
+	mfc0 t0,C0_CAUSE
+	andi t0,CAUSE_IPMASK
+	bne t0,zero,_ISR_Handler_2
+	dsrl t0,t0,8
+_ISR_Handler_5:
+#else
+	nop
+	li t1,7
+	dsll t1,t1,SZ_INT_POW2
+	la t3,_ISR_Vector_table
+	intadd t1,t3
+	lint t1,(t1)
+	jalr t1
+	nop
+#endif
+  /*
+   *  --_ISR_Nest_level;
+   */
+        lint t2,_ISR_Nest_level
+	addi t2,t2,-1
+        sint t2,_ISR_Nest_level
+  /*
+   *  --_Thread_Dispatch_disable_level;
+   */
+	lint t1,_Thread_Dispatch_disable_level
+	addi t1,t1,-1
+	sint t1,_Thread_Dispatch_disable_level
+  /*
+   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
+   *    goto the label "exit interrupt (simple case)"
+   */
+	or t0,t2,t1
+	bne t0,zero,_ISR_Handler_exit
+	nop
+  /*
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    restore stack
+   *  #endif
+   *  
+   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
+   *    goto the label "exit interrupt (simple case)"
+   */
+	lint t0,_Context_Switch_necessary
+	lint t1,_ISR_Signals_to_thread_executing
+	or t0,t0,t1
+	beq t0,zero,_ISR_Handler_exit
+	nop
+
+  /*
+   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+   */
+	jal _Thread_Dispatch
+	nop
+  /*
+   *  prepare to get out of interrupt
+   *  return from interrupt  (maybe to _ISR_Dispatch)
+   *
+   *  LABEL "exit interrupt (simple case):
+   *  prepare to get out of interrupt
+   *  return from interrupt
+   */
+_ISR_Handler_exit:
+	ld ra,32(sp)
+	stackadd sp,sp,40
+
+/* restore interrupt context from stack */
+	lreg    k0, R_MDLO*R_SZ(sp)
+	mtlo    k0
+	lreg    k0, R_MDHI*R_SZ(sp)
+	lreg    a2, R_A2*R_SZ(sp)
+	mthi    k0
+	lreg    a3, R_A3*R_SZ(sp)
+	lreg    t0, R_T0*R_SZ(sp)
+	lreg    t1, R_T1*R_SZ(sp)
+	lreg    t2, R_T2*R_SZ(sp)
+	lreg    t3, R_T3*R_SZ(sp)
+	lreg    t4, R_T4*R_SZ(sp)
+	lreg    t5, R_T5*R_SZ(sp)
+	lreg    t6, R_T6*R_SZ(sp)
+	lreg    t7, R_T7*R_SZ(sp)
+	lreg    t8, R_T8*R_SZ(sp)
+	lreg    t9, R_T9*R_SZ(sp)
+	lreg    gp, R_GP*R_SZ(sp)
+	lreg    fp, R_FP*R_SZ(sp)
+	lreg    ra, R_RA*R_SZ(sp)
+	lreg    a0, R_A0*R_SZ(sp)
+	lreg    a1, R_A1*R_SZ(sp)
+	lreg    v1, R_V1*R_SZ(sp)
+	lreg    v0, R_V0*R_SZ(sp)
+	.set noat
+	lreg    AT, R_AT*R_SZ(sp)
+	.set at
+
+	stackadd sp,sp,EXCP_STACK_SIZE /* store ra on the stack */
+
+#if USE_IDTKIT
+/* we handled exception, so return non-zero value */
+	li v0,1
+#endif
+
+_ISR_Handler_quick_exit:
+#ifdef USE_IDTKIT
+	j ra
+#else
+	eret
+#endif
+	nop
+
+_ISR_Handler_prom_exit:
+#ifdef CPU_R3000
+	la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+	la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+	j       k0
+	nop
+
+       .set    reorder
+
+ENDFRAME(_ISR_Handler)
+
+
+FRAME(mips_enable_interrupts,sp,0,ra)
+	mfc0 t0,C0_SR		/* get status reg */
+	nop
+	or t0,t0,a0		 
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_enable_interrupts)
+
+FRAME(mips_disable_interrupts,sp,0,ra)
+	mfc0 v0,C0_SR		/* get status reg */
+	li t1,SR_IMASK		/* t1 = load interrupt mask word */
+	not t0,t1		/* t0 = ~t1 */
+	and t0,v0		/* clear imask bits */
+	mtc0 t0,C0_SR		/* save status reg */
+	and v0,t1		/* mask return value (only return imask bits) */
+	jr ra
+	nop
+ENDFRAME(mips_disable_interrupts)
+
+FRAME(mips_enable_global_interrupts,sp,0,ra)
+	mfc0 t0,C0_SR		/* get status reg */
+	nop
+	ori t0,SR_IE
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_enable_global_interrupts)
+
+FRAME(mips_disable_global_interrupts,sp,0,ra)
+	li t1,SR_IE
+	mfc0 t0,C0_SR		/* get status reg */
+	not t1
+	and t0,t1
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_disable_global_interrupts)
+
+/* return the value of the status register in v0.  Used for debugging */
+FRAME(mips_get_sr,sp,0,ra)
+	mfc0 v0,C0_SR
+	j ra
+	nop
+ENDFRAME(mips_get_sr)
+
+FRAME(mips_break,sp,0,ra)
+#if 1
+	break 0x0
+	j mips_break
+#else
+	j ra
+#endif
+	nop
+ENDFRAME(mips_break)
+
+/*PAGE
+ *
+ *  _CPU_Internal_threads_Idle_thread_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ */
+
+FRAME(_CPU_Thread_Idle_body,sp,0,ra)
+	wait			/* enter low power mode */
+	j _CPU_Thread_Idle_body
+	nop
+ENDFRAME(_CPU_Thread_Idle_body)
+
+#define VEC_CODE_LENGTH 10*4
+
+/**************************************************************************
+**
+**	init_exc_vecs() - moves the exception code into the addresses
+**			  reserved for exception vectors
+**
+**	UTLB Miss exception vector at address 0x80000000
+**
+**	General exception vector at address 0x80000080
+**
+**	RESET exception vector is at address 0xbfc00000
+**
+***************************************************************************/
+
+#define INITEXCFRM ((2*4)+4)		/* ra + 2 arguments */
+FRAME(init_exc_vecs,sp,0,ra)
+/* This code yanked from SIM */
+#if defined(CPU_R3000)
+	.set	noreorder
+	la	t1,exc_utlb_code
+	la	t2,exc_norm_code
+	li	t3,UT_VEC
+	li	t4,E_VEC
+	li	t5,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	lw	t7,0(t2)
+	sw	t6,0(t3)
+	sw	t7,0(t4)
+	addiu	t1,4
+	addiu	t3,4
+	addiu	t4,4
+	subu	t5,4
+	bne	t5,zero,1b
+	addiu	t2,4
+	move	t5,ra		# assumes clear_cache doesnt use t5
+	li	a0,UT_VEC
+	jal	clear_cache
+	li	a1,VEC_CODE_LENGTH
+	nop
+	li	a0,E_VEC
+	jal	clear_cache
+	li	a1,VEC_CODE_LENGTH
+	move	ra,t5		# restore ra
+	j	ra
+	nop
+	.set	reorder
+#endif
+#if defined(CPU_R4000)
+	.set reorder
+	move	t5,ra		# assumes clear_cache doesnt use t5
+
+	/* TLB exception vector */
+	la	t1,exc_tlb_code
+	li	t2,T_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,T_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	la	t1,exc_xtlb_code
+	li	t2,X_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	/* extended TLB exception vector */
+	li	a0,X_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	/* cache error exception vector */
+	la	t1,exc_cache_code
+	li	t2,C_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,C_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	/* normal exception vector */
+	la	t1,exc_norm_code
+	li	t2,E_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,E_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	move	ra,t5		# restore ra
+	j	ra
+#endif
+ENDFRAME(init_exc_vecs)
+
+
+#if defined(CPU_R4000)
+FRAME(exc_tlb_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_tlb_code)
+
+
+FRAME(exc_xtlb_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_xtlb_code)
+
+
+FRAME(exc_cache_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_cache_code)
+
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+	subu	sp, EXCP_STACK_SIZE		/* set up local stack frame */
+ENDFRAME(exc_norm_code)
+#endif
+
+/**************************************************************************
+**
+** enable_int(mask) - enables interrupts - mask is positioned so it only
+**                      needs to be or'ed into the status reg. This
+**                      also does some other things !!!! caution should
+**                      be used if invoking this while in the middle
+**                      of a debugging session where the client may have
+**                      nested interrupts.
+**
+****************************************************************************/
+FRAME(enable_int,sp,0,ra)
+        .set    noreorder
+        mfc0    t0,C0_SR
+        or      a0,1
+        or      t0,a0
+        mtc0    t0,C0_SR
+        j       ra
+        nop
+        .set    reorder
+ENDFRAME(enable_int)
+
+
+/***************************************************************************
+**
+**      disable_int(mask) - disable the interrupt - mask is the complement
+**                          of the bits to be cleared - i.e. to clear ext int
+**                          5 the mask would be - 0xffff7fff
+**
+****************************************************************************/
+FRAME(disable_int,sp,0,ra)
+        .set    noreorder
+        mfc0    t0,C0_SR
+        nop
+        and     t0,a0
+        mtc0    t0,C0_SR
+        j       ra
+        nop
+ENDFRAME(disable_int)
+
+
diff --git a/c/src/exec/score/cpu/mips/cpu_asm.h b/c/src/exec/score/cpu/mips/cpu_asm.h
new file mode 100644
index 0000000000..9696204962
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/cpu_asm.h
@@ -0,0 +1,115 @@
+/*
+ *  cpu_asm.h
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu_asm.h,v 1.4 1995/09/26 19:25:39 joel Exp
+ *
+ */
+/* @(#)cpu_asm.h       08/20/96     1.2 */
+
+#ifndef __CPU_ASM_h
+#define __CPU_ASM_h
+
+/* pull in the generated offsets */
+
+/* #include <rtems/score/offsets.h> */
+
+/*
+ * Hardware General Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Floating Point Registers
+ */
+
+#define R_FP0 	0
+#define R_FP1 	1
+#define R_FP2 	2
+#define R_FP3 	3
+#define R_FP4 	4
+#define R_FP5 	5
+#define R_FP6 	6
+#define R_FP7 	7
+#define R_FP8 	8
+#define R_FP9 	9
+#define R_FP10 	10
+#define R_FP11 	11
+#define R_FP12 	12
+#define R_FP13 	13
+#define R_FP14 	14
+#define R_FP15 	15
+#define R_FP16 	16
+#define R_FP17 	17
+#define R_FP18 	18
+#define R_FP19 	19
+#define R_FP20 	20
+#define R_FP21 	21
+#define R_FP22 	22
+#define R_FP23	23
+#define R_FP24 	24
+#define R_FP25 	25
+#define R_FP26 	26
+#define R_FP27 	27
+#define R_FP28 	28
+#define R_FP29 	29
+#define R_FP30 	30
+#define R_FP31 	31
+
+/*
+ * Hardware Control Registers
+ */
+
+/* put something here */
+
+/*
+ * Calling Convention
+ */
+
+/* put something here */
+
+/*
+ * Temporary registers
+ */
+
+/* put something here */
+
+/*
+ * Floating Point Registers - SW Conventions
+ */
+
+/* put something here */
+
+/*
+ * Temporary floating point registers
+ */
+
+/* put something here */
+
+#endif
+
+/* end of file */
diff --git a/c/src/exec/score/cpu/mips/idtcpu.h b/c/src/exec/score/cpu/mips/idtcpu.h
new file mode 100644
index 0000000000..833c5ebe02
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/idtcpu.h
@@ -0,0 +1,439 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+** idtcpu.h -- cpu related defines
+*/
+
+#ifndef _IDTCPU_H__
+#define _IDTCPU_H__
+
+/*
+ * 950313: Ketan added Register definition for XContext reg.
+ *               added define for WAIT instruction.
+ * 950421: Ketan added Register definition for Config reg (R3081)
+ */
+
+/*
+** memory configuration and mapping
+*/
+#define K0BASE	0x80000000
+#define K0SIZE	0x20000000
+#define K1BASE	0xa0000000
+#define K1SIZE	0x20000000
+#define K2BASE	0xc0000000
+#define K2SIZE	0x20000000
+#if defined(CPU_R4000)
+#define KSBASE	0xe0000000
+#define KSSIZE	0x20000000
+#endif
+
+#define KUBASE	0
+#define KUSIZE	0x80000000
+
+/*
+** Exception Vectors
+*/
+#if defined(CPU_R3000)
+#define	UT_VEC	K0BASE			/* utlbmiss vector */
+#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
+#endif
+#if defined(CPU_R4000)
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K0BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
+#endif
+#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define CAST(as) (as)
+#else
+#define CAST(as)
+#endif
+#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
+
+/*
+**	Cache size constants
+*/
+#define	MINCACHE	0x200		/* 512       For 3041. */
+#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+
+#if defined(CPU_R4000)
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00010000	/* 32 bit */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#ifndef WAIT
+#define WAIT .word 0x42000020
+#endif WAIT
+
+#ifndef wait 
+#define wait .word 0x42000020
+#endif wait
+
+#endif
+
+/*
+** TLB resource defines
+*/
+#if defined(CPU_R3000)
+#define	N_TLB_ENTRIES	64
+#define TLB_PGSIZE	0x1000
+#define RANDBASE	8
+#define	TLBLO_PFNMASK	0xfffff000
+#define	TLBLO_PFNSHIFT	12
+#define	TLBLO_N		0x800	/* non-cacheable */
+#define	TLBLO_D		0x400	/* writeable */
+#define	TLBLO_V		0x200	/* valid bit */
+#define	TLBLO_G		0x100	/* global access bit */
+
+#define	TLBHI_VPNMASK	0xfffff000
+#define	TLBHI_VPNSHIFT	12
+#define	TLBHI_PIDMASK	0xfc0
+#define	TLBHI_PIDSHIFT	6
+#define	TLBHI_NPID	64
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x00003f00
+#define	TLBINX_INXSHIFT	8
+
+#define	TLBRAND_RANDMASK	0x00003f00
+#define	TLBRAND_RANDSHIFT	8
+
+#define	TLBCTXT_BASEMASK	0xffe00000
+#define	TLBCTXT_BASESHIFT	21
+
+#define	TLBCTXT_VPNMASK		0x001ffffc
+#define	TLBCTXT_VPNSHIFT	2
+#endif
+#if defined(CPU_R4000)
+#define	N_TLB_ENTRIES	48
+
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define TLBLO_CSHIFT	3
+
+#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define TLBPGMASK_MASK		0x01ffe000
+#endif
+
+#if defined(CPU_R3000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_BEV		0x00400000	/* use boot exception vectors */
+
+/* Cache control bits */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_PE		0x00100000	/* cache parity error */
+#define	SR_CM		0x00080000	/* cache miss */
+#define	SR_PZ		0x00040000	/* cache parity zero */
+#define	SR_SWC		0x00020000	/* swap cache */
+#define	SR_ISC		0x00010000	/* Isolate data cache */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
+#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
+#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
+#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
+#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
+#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
+#endif
+
+#if defined(CPU_R4000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define SR_RP		0x08000000      /* Reduced power operation */
+#define SR_FR		0x04000000	/* Additional floating point registers */
+#define SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define SR_BEV		0x00400000	/* Use boot exception vectors */
+#define SR_TS		0x00200000	/* TLB shutdown */
+#define SR_SR		0x00100000	/* Soft reset */
+#define SR_CH		0x00040000	/* Cache hit */
+#define SR_CE		0x00020000	/* Use cache ECC  */
+#define SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define SR_KSUSER	0x00000010	/* User mode */
+#define SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define SR_ERL		0x00000004	/* Error level */
+#define SR_EXL		0x00000002	/* Exception level */
+#define SR_IE		0x00000001	/* Interrupts enabled */
+#endif
+
+
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD	0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT	28
+
+
+#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT	8
+
+#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+#define	C0_INX		$0		/* tlb index */
+#define	C0_RAND		$1		/* tlb random */
+#if defined(CPU_R3000)
+#define	C0_TLBLO	$2		/* tlb entry low */
+#endif
+#if defined(CPU_R4000)
+#define	C0_TLBLO0	$2		/* tlb entry low 0 */
+#define	C0_TLBLO1	$3		/* tlb entry low 1 */
+#endif
+
+#define	C0_CTXT		$4		/* tlb context */
+
+#if defined(CPU_R4000)
+#define C0_PAGEMASK	$5		/* tlb page mask */
+#define C0_WIRED	$6		/* number of wired tlb entries */
+#endif
+
+#define	C0_BADVADDR	$8		/* bad virtual address */
+
+#if defined(CPU_R4000)
+#define C0_COUNT	$9		/* cycle count */
+#endif
+
+#define	C0_TLBHI	$10		/* tlb entry hi */
+
+#if defined(CPU_R4000)
+#define C0_COMPARE	$11		/* cyccle count comparator  */
+#endif
+
+#define	C0_SR		$12		/* status register */
+#define	C0_CAUSE	$13		/* exception cause */
+#define	C0_EPC		$14		/* exception pc */
+#define	C0_PRID		$15		/* revision identifier */
+
+#if defined(CPU_R3000)
+#define C0_CONFIG   $3     /* configuration register R3081*/
+#endif
+
+#if defined(CPU_R4000)
+#define C0_CONFIG	$16		/* configuration register */
+#define C0_LLADDR	$17		/* linked load address */
+#define C0_WATCHLO	$18		/* watchpoint trap register */
+#define C0_WATCHHI	$19		/* watchpoint trap register */
+#define C0_XCTXT    $20     /* extended tlb context */
+#define C0_ECC		$26		/* secondary cache ECC control */
+#define C0_CACHEERR	$27		/* cache error status */
+#define C0_TAGLO	$28		/* cache tag lo */
+#define C0_TAGHI	$29		/* cache tag hi */
+#define C0_ERRPC	$30		/* cache error pc */
+#endif
+
+#endif XDS
+
+#ifdef R4650
+#define IWATCH $18
+#define DWATCH $19
+#define IBASE  $0
+#define IBOUND $1
+#define DBASE  $2
+#define DBOUND $3
+#define CALG	$17
+#endif
+
+#endif /* _IDTCPU_H__ */
+
diff --git a/c/src/exec/score/cpu/mips/idtmon.h b/c/src/exec/score/cpu/mips/idtmon.h
new file mode 100644
index 0000000000..1cddbcb2a3
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/idtmon.h
@@ -0,0 +1,170 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+**	idtmon.h - General header file for the IDT Prom Monitor
+**
+**	Copyright 1989  Integrated Device Technology, Inc.
+**	All Rights Reserved.
+**
+**	June 1989 - D.Cahoon
+*/
+#ifndef __IDTMON_H__
+#define __IDTMON_H__
+
+/*
+** P_STACKSIZE is the size of the Prom Stack. 
+** the prom stack grows downward 
+*/
+#define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
+
+/*
+** M_BUSWIDTH
+** Memory bus width (including bank interleaving) in bytes
+** used when doing memory sizing to prevent bus capacitance
+** reporting ghost memory locations
+*/
+#if defined(CPU_R3000)
+#define M_BUSWIDTH	8	/* 32bit memory bank interleaved */
+#endif
+#if defined(CPU_R4000)
+#define M_BUSWIDTH	16	/* 64 bit memory bank interleaved */
+#endif
+
+/*
+** this is the default value for the number of bytes to add in calculating
+** the checksums in the checksum command
+*/
+#define CHK_SUM_CNT	0x20000	     /* number of bytes to calc chksum for */
+
+/*
+** Monitor modes
+*/
+#define	MODE_MONITOR	5	/* IDT Prom Monitor is executing */
+#define	MODE_USER	0xa	/* USER is executing */
+
+/*
+** memory reference widths
+*/
+#define	SW_BYTE		1
+#define	SW_HALFWORD	2
+#define	SW_WORD		4
+#define SW_TRIBYTEL	12
+#define SW_TRIBYTER	20
+
+#ifdef CPU_R4000
+/*
+** definitions for select_cache call
+*/
+#define DCACHE		0
+#define ICACHE		1
+#define SCACHE		2
+
+#endif
+
+#if defined (CLANGUAGE) || defined(_LANGUAGE_C)
+typedef struct {
+	unsigned int	mem_size;
+	unsigned int	icache_size;
+	unsigned int	dcache_size;
+#ifdef CPU_R4000
+    unsigned int    scache_size;
+#endif
+
+	} mem_config;
+
+#endif CLANGUAGE || defined(_LANGUAGE_C)
+
+/*
+** general equates for diagnostics and boolean functions
+*/
+#define	PASS			0
+#define	FAIL			1
+
+#ifndef	TRUE
+#define	TRUE			1
+#endif	TRUE
+#ifndef	NULL
+#define	NULL			0
+#endif	NULL
+
+#ifndef	FALSE
+#define	FALSE			0
+#endif	FALSE
+
+
+/*
+**	portablility equates
+*/
+
+#ifndef	BOOL
+#define BOOL	unsigned int
+#endif	BOOL
+
+#ifndef GLOBAL
+#define GLOBAL	/**/
+#endif  GLOBAL
+
+#ifndef MLOCAL
+#define MLOCAL	static
+#endif  MLOCAL
+
+
+#ifdef XDS
+#define CONST const
+#else
+#define CONST
+#endif XDS 
+
+#define u_char	unsigned char
+#define u_short unsigned short
+#define u_int	unsigned int
+/*
+** assembly instructions for compatability between xds and mips
+*/
+#ifndef XDS
+#define sllv sll
+#define srlv srl
+#endif XDS
+/*
+**	debugger macros for assembly language routines. Allows the 
+**	programmer to set up the necessary stack frame info
+**	required by debuggers to do stack traces.
+*/
+
+#ifndef XDS 
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+#define ENDFRAME(name) 				\
+	.end name
+#else
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	_##name;\
+_##name:
+#define ENDFRAME(name)
+#endif  XDS
+#endif /* __IDTMON_H__ */
diff --git a/c/src/exec/score/cpu/mips/iregdef.h b/c/src/exec/score/cpu/mips/iregdef.h
new file mode 100644
index 0000000000..e7a4ba5ed1
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/iregdef.h
@@ -0,0 +1,324 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+**	iregdef.h - IDT R3000 register structure header file
+**
+**	Copyright 1989 Integrated Device Technology, Inc
+**	All Rights Reserved
+**
+*/
+#ifndef __IREGDEF_H__
+#define __IREGDEF_H__
+
+/*
+ * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
+ *         added Register definition for XContext reg.
+ *         Look towards end of this file.
+ */
+/*
+** register names 
+*/
+#define r0	$0
+#define r1	$1
+#define r2	$2
+#define r3	$3
+#define r4	$4
+#define r5	$5
+#define r6	$6
+#define r7	$7
+#define r8	$8
+#define r9	$9
+#define r10	$10
+#define r11	$11
+#define r12	$12
+#define r13	$13
+
+#define r14	$14
+#define r15	$15
+#define r16	$16
+#define r17	$17
+#define r18	$18
+#define r19	$19
+#define r20	$20
+#define r21	$21
+#define r22	$22
+#define r23	$23
+#define r24	$24
+#define r25	$25
+#define r26	$26
+#define r27	$27
+#define r28	$28
+#define r29	$29
+#define r30	$30
+#define r31	$31
+
+#define fp0	$f0
+#define fp1	$f1
+#define fp2	$f2
+#define fp3	$f3
+#define fp4	$f4
+#define fp5	$f5
+#define fp6	$f6
+#define fp7	$f7
+#define fp8	$f8
+#define fp9	$f9
+#define fp10	$f10
+#define fp11	$f11
+#define fp12	$f12
+#define fp13	$f13
+#define fp14	$f14
+#define fp15	$f15
+#define fp16	$f16
+#define fp17	$f17
+#define fp18	$f18
+#define fp19	$f19
+#define fp20	$f20
+#define fp21	$f21
+#define fp22	$f22
+#define fp23	$f23
+#define fp24	$f24
+#define fp25	$f25
+#define fp26	$f26
+#define fp27	$f27
+#define fp28	$f28
+#define fp29	$f29
+#define fp30	$f30
+#define fp31	$f31
+
+#define fcr0	$0
+#define fcr30	$30
+#define fcr31	$31
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers a0-a3 */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved  t0-t9 */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved s0-s8 */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel usage */
+#define k1	$27	/* kernel usage */
+#define gp	$28	/* sdata pointer */
+#define sp	$29	/* stack pointer */
+#define s8	$30	/* yet another saved reg for the callee */
+#define fp	$30	/* frame pointer - this is being phased out by MIPS */
+#define ra	$31	/* return address */
+
+
+/*
+** relative position of registers in save reg area
+*/
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define	R_F0		32
+#define	R_F1		33
+#define	R_F2		34
+#define	R_F3		35
+#define	R_F4		36
+#define	R_F5		37
+#define	R_F6		38
+#define	R_F7		39
+#define	R_F8		40
+#define	R_F9		41
+#define	R_F10		42
+#define	R_F11		43
+#define	R_F12		44
+#define	R_F13		45
+#define	R_F14		46
+#define	R_F15		47
+#define	R_F16		48
+#define	R_F17		49
+#define	R_F18		50
+#define	R_F19		51
+#define	R_F20		52
+#define	R_F21		53
+#define	R_F22		54
+#define	R_F23		55
+#define	R_F24		56
+#define	R_F25		57
+#define	R_F26		58
+#define	R_F27		59
+#define	R_F28		60
+#define	R_F29		61
+#define	R_F30		62
+#define	R_F31		63
+#define NCLIENTREGS	64
+#define	R_EPC		64
+#define	R_MDHI		65
+#define	R_MDLO		66
+#define	R_SR		67
+#define	R_CAUSE		68
+#define	R_TLBHI		69
+#if defined(CPU_R3000)
+#define	R_TLBLO		70
+#endif
+#if defined(CPU_R4000)
+#define	R_TLBLO0	70
+#endif
+#define	R_BADVADDR	71
+#define	R_INX		72
+#define	R_RAND		73
+#define	R_CTXT		74
+#define	R_EXCTYPE	75
+#define R_MODE		76
+#define	R_PRID		77
+#define R_FCSR		78
+#define R_FEIR		79
+#if defined(CPU_R3000)
+#define NREGS		80
+#endif
+#if defined(CPU_R4000)
+#define	R_TLBLO1	80
+#define R_PAGEMASK	81
+#define R_WIRED		82
+#define R_COUNT		83
+#define R_COMPARE	84
+#define R_CONFIG	85
+#define R_LLADDR	86
+#define R_WATCHLO	87
+#define R_WATCHHI	88
+#define R_ECC		89
+#define R_CACHEERR	90
+#define R_TAGLO		91
+#define R_TAGHI		92
+#define R_ERRPC		93
+#define R_XCTXT     94  /* Ketan added from SIM64bit */
+
+#define	NREGS		95
+#endif
+
+/*
+** For those who like to think in terms of the compiler names for the regs
+*/
+#define	R_ZERO		R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
+
+/* Ketan added the following */
+#ifdef CPU_R3000
+#define sreg	sw
+#define lreg	lw
+#define rmfc0	mfc0
+#define rmtc0	mtc0
+#define R_SZ	4
+#endif CPU_R3000
+
+#ifdef CPU_R4000
+#if __mips < 3
+#define sreg	sw
+#define lreg	lw
+#define rmfc0	mfc0
+#define rmtc0	mtc0
+#define R_SZ	4
+#else
+#define sreg	sd
+#define lreg	ld
+#define rmfc0	dmfc0
+#define rmtc0	dmtc0
+#define R_SZ	8
+#endif
+#endif CPU_R4000
+/* Ketan till here */
+
+#endif /* __IREGDEF_H__ */
+
diff --git a/c/src/exec/score/cpu/mips/rtems.c b/c/src/exec/score/cpu/mips/rtems.c
new file mode 100644
index 0000000000..3128ef3379
--- /dev/null
+++ b/c/src/exec/score/cpu/mips/rtems.c
@@ -0,0 +1,49 @@
+/*  rtems.c  ===> rtems.S or rtems.s
+ *
+ *  This file contains the single entry point code for
+ *  the XXX implementation of RTEMS.
+ *
+ *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  rtems.c,v 1.4 1995/09/26 19:25:41 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)rtems.c 03/15/96     1.1\n";
+#endif
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" rtems file.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+/* #include "asm.h> */
+
+/*
+ *  RTEMS
+ *
+ *  This routine jumps to the directive indicated in the
+ *  CPU defined register.  This routine is used when RTEMS is
+ *  linked by itself and placed in ROM.  This routine is the
+ *  first address in the ROM space for RTEMS.  The user "calls"
+ *  this address with the directive arguments in the normal place.
+ *  This routine then jumps indirectly to the correct directive
+ *  preserving the arguments.  The directive should not realize
+ *  it has been "wrapped" in this way.  The table "_Entry_points"
+ *  is used to look up the directive.
+ */
+
+void RTEMS()
+{
+}
+
diff --git a/c/src/exec/score/cpu/mips64orion/asm.h b/c/src/exec/score/cpu/mips64orion/asm.h
new file mode 100644
index 0000000000..d5a5d69eaa
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/asm.h
@@ -0,0 +1,99 @@
+/*  asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ *
+ *
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  asm.h,v 1.4 1995/09/26 19:25:36 joel Exp
+ */
+/* @(#)asm.h       03/15/96     1.1 */
+
+#ifndef __NO_CPU_ASM_h
+#define __NO_CPU_ASM_h
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#define ASM
+#include <rtems/score/no_cpu.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+/* ANSI concatenation macros.  */
+
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a ## b
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA
+#define END_DATA
+#define BEGIN_BSS
+#define END_BSS
+#define END
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC(sym) .globl SYM (sym)
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
+/* end of include file */
+
+
diff --git a/c/src/exec/score/cpu/mips64orion/cpu.c b/c/src/exec/score/cpu/mips64orion/cpu.c
new file mode 100644
index 0000000000..ec8c73393e
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/cpu.c
@@ -0,0 +1,216 @@
+/*
+ *  Mips CPU Dependent Source
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu.c,v 1.7 1995/09/26 19:25:37 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+
+ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ */
+
+
+void null_handler( void )
+{
+}
+
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+   unsigned int i = ISR_NUMBER_OF_VECTORS;
+
+   while ( i-- )
+   {
+      _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler;
+   }
+
+  /*
+   *  The thread_dispatch argument is the address of the entry point
+   *  for the routine called at the end of an ISR once it has been
+   *  decided a context switch is necessary.  On some compilation
+   *  systems it is difficult to call a high-level language routine
+   *  from assembly.  This allows us to trick these systems.
+   *
+   *  If you encounter this problem save the entry point in a CPU
+   *  dependent variable.
+   */
+
+  _CPU_Thread_dispatch_pointer = thread_dispatch;
+
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+
+  _CPU_Table = *cpu_table;
+
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ */
+ 
+#if 0 /* located in cpu_asm.S */
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+}
+#endif
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+
+#if 0 /* not necessary */
+/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
+   add_ext_int_func( vector, new_handler );
+#endif
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ */
+
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+/* we don't support this yet */
+}
+
+/*PAGE
+ *
+ *  _CPU_Internal_threads_Idle_thread_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ */
+
+#if 0 /* located in cpu_asm.S */
+void _CPU_Thread_Idle_body( void )
+{
+
+  for( ; ; )
+    /* insert your "halt" instruction here */ ;
+}
+#endif
+
+extern void mips_break( int error );
+
+#include <stdio.h>
+
+void mips_fatal_error( int error )
+{
+   printf("fatal error 0x%x %d\n",error,error);
+   mips_break( error );
+}
diff --git a/c/src/exec/score/cpu/mips64orion/cpu.h b/c/src/exec/score/cpu/mips64orion/cpu.h
new file mode 100644
index 0000000000..e9830e5713
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/cpu.h
@@ -0,0 +1,937 @@
+/*  cpu.h
+ *
+ *  This include file contains information pertaining to the IDT 4650
+ *  processor.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu.h,v 1.7 1995/12/05 21:41:21 joel Exp
+ */
+/* @(#)cpu.h       08/29/96     1.7 */
+
+#ifndef __CPU_h
+#define __CPU_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/mips64orion.h>               /* pick up machine definitions */
+#ifndef ASM
+#include <rtems/score/mipstypes.h>
+#endif
+
+extern int mips_disable_interrupts( void );
+extern void mips_enable_interrupts( int _level );
+extern int mips_disable_global_interrupts( void );
+extern void mips_enable_global_interrupts( void );
+extern void mips_fatal_error ( int error );
+
+/* conditional compilation parameters */
+
+/*
+ *  Should the calls to _Thread_Enable_dispatch be inlined?
+ *
+ *  If TRUE, then they are inlined.
+ *  If FALSE, then a subroutine call is made.
+ *
+ *  Basically this is an example of the classic trade-off of size
+ *  versus speed.  Inlining the call (TRUE) typically increases the
+ *  size of RTEMS while speeding up the enabling of dispatching.
+ *  [NOTE: In general, the _Thread_Dispatch_disable_level will
+ *  only be 0 or 1 unless you are in an interrupt handler and that
+ *  interrupt handler invokes the executive.]  When not inlined
+ *  something calls _Thread_Enable_dispatch which in turns calls
+ *  _Thread_Dispatch.  If the enable dispatch is inlined, then
+ *  one subroutine call is avoided entirely.]
+ */
+
+#define CPU_INLINE_ENABLE_DISPATCH       TRUE
+
+/*
+ *  Should the body of the search loops in _Thread_queue_Enqueue_priority
+ *  be unrolled one time?  In unrolled each iteration of the loop examines
+ *  two "nodes" on the chain being searched.  Otherwise, only one node
+ *  is examined per iteration.
+ *
+ *  If TRUE, then the loops are unrolled.
+ *  If FALSE, then the loops are not unrolled.
+ *
+ *  The primary factor in making this decision is the cost of disabling
+ *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ *  body of the loop.  On some CPUs, the flash is more expensive than
+ *  one iteration of the loop body.  In this case, it might be desirable
+ *  to unroll the loop.  It is important to note that on some CPUs, this
+ *  code is the longest interrupt disable period in RTEMS.  So it is
+ *  necessary to strike a balance when setting this parameter.
+ */
+
+#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
+
+/*
+ *  Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
+ *  If FALSE, nothing is done.
+ *
+ *  If the CPU supports a dedicated interrupt stack in hardware,
+ *  then it is generally the responsibility of the BSP to allocate it
+ *  and set it up.
+ *
+ *  If the CPU does not support a dedicated interrupt stack, then
+ *  the porter has two options: (1) execute interrupts on the
+ *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ *  interrupt stack.
+ *
+ *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ */
+
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
+
+/*
+ *  Does this CPU have hardware support for a dedicated interrupt stack?
+ *
+ *  If TRUE, then it must be installed during initialization.
+ *  If FALSE, then no installation is performed.
+ *
+ *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ */
+
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+
+/*
+ *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ *
+ *  If TRUE, then the memory is allocated during initialization.
+ *  If FALSE, then the memory is allocated during initialization.
+ *
+ *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
+ *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
+ */
+
+#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
+
+/*
+ *  Does the CPU have hardware floating point?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ *  If there is a FP coprocessor such as the i387 or mc68881, then
+ *  the answer is TRUE.
+ *
+ *  The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
+ *  It indicates whether or not this CPU model has FP support.  For
+ *  example, it would be possible to have an i386_nofp CPU model
+ *  which set this to false to indicate that you have an i386 without
+ *  an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+#if ( MIPS64ORION_HAS_FPU == 1 )
+#define CPU_HARDWARE_FP     TRUE
+#else
+#define CPU_HARDWARE_FP     FALSE
+#endif
+
+/*
+ *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ *  So far, the only CPU in which this option has been used is the
+ *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
+ *  floating point registers to perform integer multiplies.  If
+ *  a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
+ *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ */
+
+#define CPU_ALL_TASKS_ARE_FP    FALSE
+
+/*
+ *  Should the IDLE task have a floating point context?
+ *
+ *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ *  and it has a floating point context which is switched in and out.
+ *  If FALSE, then the IDLE task does not have a floating point context.
+ *
+ *  Setting this to TRUE negatively impacts the time required to preempt
+ *  the IDLE task from an interrupt because the floating point context
+ *  must be saved as part of the preemption.
+ */
+
+#define CPU_IDLE_TASK_IS_FP      FALSE
+
+/*
+ *  Should the saving of the floating point registers be deferred
+ *  until a context switch is made to another different floating point
+ *  task?
+ *
+ *  If TRUE, then the floating point context will not be stored until
+ *  necessary.  It will remain in the floating point registers and not
+ *  disturned until another floating point task is switched to.
+ *
+ *  If FALSE, then the floating point context is saved when a floating
+ *  point task is switched out and restored when the next floating point
+ *  task is restored.  The state of the floating point registers between
+ *  those two operations is not specified.
+ *
+ *  If the floating point context does NOT have to be saved as part of
+ *  interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ *  Setting this flag to TRUE results in using a different algorithm
+ *  for deciding when to save and restore the floating point context.
+ *  The deferred FP switch algorithm minimizes the number of times
+ *  the FP context is saved and restored.  The FP context is not saved
+ *  until a context switch is made to another, different FP task.
+ *  Thus in a system with only one FP task, the FP context will never
+ *  be saved or restored.
+ */
+
+#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
+
+/*
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  _Internal_threads_Idle_thread_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ *
+ *  This is intended to allow for supporting processors which have
+ *  a low power or idle mode.  When the IDLE thread is executed, then
+ *  the CPU can be powered down.
+ *
+ *  The order of precedence for selecting the IDLE thread body is:
+ *
+ *    1.  BSP provided
+ *    2.  CPU dependent (if provided)
+ *    3.  generic (if no BSP and no CPU dependent)
+ */
+
+/* we can use the low power wait instruction for the IDLE thread */
+#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE 
+
+/*
+ *  Does the stack grow up (toward higher addresses) or down
+ *  (toward lower addresses)?
+ *
+ *  If TRUE, then the grows upward.
+ *  If FALSE, then the grows toward smaller addresses.
+ */
+
+/* our stack grows down */
+#define CPU_STACK_GROWS_UP               FALSE
+
+/*
+ *  The following is the variable attribute used to force alignment
+ *  of critical RTEMS structures.  On some processors it may make
+ *  sense to have these aligned on tighter boundaries than
+ *  the minimum requirements of the compiler in order to have as
+ *  much of the critical data area as possible in a cache line.
+ *
+ *  The placement of this macro in the declaration of the variables
+ *  is based on the syntactically requirements of the GNU C
+ *  "__attribute__" extension.  For example with GNU C, use
+ *  the following to force a structures to a 32 byte boundary.
+ *
+ *      __attribute__ ((aligned (32)))
+ *
+ *  NOTE:  Currently only the Priority Bit Map table uses this feature.
+ *         To benefit from using this, the data must be heavily
+ *         used so it will stay in the cache and used frequently enough
+ *         in the executive to justify turning this on.
+ */
+
+/* our cache line size is 16 bytes */
+#if __GNUC__
+#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
+#else
+#define CPU_STRUCTURE_ALIGNMENT 
+#endif
+
+/*
+ *  The following defines the number of bits actually used in the
+ *  interrupt field of the task mode.  How those bits map to the
+ *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
+ */
+
+#define CPU_MODES_INTERRUPT_MASK   0x00000001
+
+/*
+ *  Processor defined structures
+ *
+ *  Examples structures include the descriptor tables from the i386
+ *  and the processor control structure on the i960ca.
+ */
+
+/* may need to put some structures here.  */
+
+/*
+ * Contexts
+ *
+ *  Generally there are 2 types of context to save.
+ *     1. Interrupt registers to save
+ *     2. Task level registers to save
+ *
+ *  This means we have the following 3 context items:
+ *     1. task level context stuff::  Context_Control
+ *     2. floating point task stuff:: Context_Control_fp
+ *     3. special interrupt level context :: Context_Control_interrupt
+ *
+ *  On some processors, it is cost-effective to save only the callee
+ *  preserved registers during a task context switch.  This means
+ *  that the ISR code needs to save those registers which do not
+ *  persist across function calls.  It is not mandatory to make this
+ *  distinctions between the caller/callee saves registers for the
+ *  purpose of minimizing context saved during task switch and on interrupts.
+ *  If the cost of saving extra registers is minimal, simplicity is the
+ *  choice.  Save the same context on interrupt entry as for tasks in
+ *  this case.
+ *
+ *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ *  care should be used in designing the context area.
+ *
+ *  On some CPUs with hardware floating point support, the Context_Control_fp
+ *  structure will not be used or it simply consist of an array of a
+ *  fixed number of bytes.   This is done when the floating point context
+ *  is dumped by a "FP save context" type instruction and the format
+ *  is not really defined by the CPU.  In this case, there is no need
+ *  to figure out the exact format -- only the size.  Of course, although
+ *  this is enough information for RTEMS, it is probably not enough for
+ *  a debugger such as gdb.  But that is another problem.
+ */
+
+/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
+typedef struct {
+    unsigned64 s0;
+    unsigned64 s1;
+    unsigned64 s2;
+    unsigned64 s3;
+    unsigned64 s4;
+    unsigned64 s5;
+    unsigned64 s6;
+    unsigned64 s7;
+    unsigned64 sp;
+    unsigned64 fp;
+    unsigned64 ra;
+    unsigned64 c0_sr;
+    unsigned64 c0_epc;
+} Context_Control;
+
+/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
+typedef struct {
+    unsigned32      fp0;
+    unsigned32      fp1;
+    unsigned32      fp2;
+    unsigned32      fp3;
+    unsigned32      fp4;
+    unsigned32      fp5;
+    unsigned32      fp6;
+    unsigned32      fp7;
+    unsigned32      fp8;
+    unsigned32      fp9;
+    unsigned32      fp10;
+    unsigned32      fp11;
+    unsigned32      fp12;
+    unsigned32      fp13;
+    unsigned32      fp14;
+    unsigned32      fp15;
+    unsigned32      fp16;
+    unsigned32      fp17;
+    unsigned32      fp18;
+    unsigned32      fp19;
+    unsigned32      fp20;
+    unsigned32      fp21;
+    unsigned32      fp22;
+    unsigned32      fp23;
+    unsigned32      fp24;
+    unsigned32      fp25;
+    unsigned32      fp26;
+    unsigned32      fp27;
+    unsigned32      fp28;
+    unsigned32      fp29;
+    unsigned32      fp30;
+    unsigned32      fp31;
+} Context_Control_fp;
+
+typedef struct {
+    unsigned32 special_interrupt_register;
+} CPU_Interrupt_frame;
+
+
+/*
+ *  The following table contains the information required to configure
+ *  the mips processor specific parameters.
+ */
+
+typedef struct {
+  void       (*pretasking_hook)( void );
+  void       (*predriver_hook)( void );
+  void       (*postdriver_hook)( void );
+  void       (*idle_task)( void );
+  boolean      do_zero_of_workspace;
+  unsigned32   interrupt_stack_size;
+  unsigned32   extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( unsigned32 );
+  void       (*stack_free_hook)( void* );
+  /* end of fields required on all CPUs */
+
+  unsigned32   some_other_cpu_dependent_info;
+}   rtems_cpu_table;
+
+/*
+ *  This variable is optional.  It is used on CPUs on which it is difficult
+ *  to generate an "uninitialized" FP context.  It is filled in by
+ *  _CPU_Initialize and copied into the task's FP context area during
+ *  _CPU_Context_Initialize.
+ */
+
+SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
+
+/*
+ *  On some CPUs, RTEMS supports a software managed interrupt stack.
+ *  This stack is allocated by the Interrupt Manager and the switch
+ *  is performed in _ISR_Handler.  These variables contain pointers
+ *  to the lowest and highest addresses in the chunk of memory allocated
+ *  for the interrupt stack.  Since it is unknown whether the stack
+ *  grows up or down (in general), this give the CPU dependent
+ *  code the option of picking the version it wants to use.
+ *
+ *  NOTE: These two variables are required if the macro
+ *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ */
+
+SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
+SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+
+/*
+ *  With some compilation systems, it is difficult if not impossible to
+ *  call a high-level language routine from assembly language.  This
+ *  is especially true of commercial Ada compilers and name mangling
+ *  C++ ones.  This variable can be optionally defined by the CPU porter
+ *  and contains the address of the routine _Thread_Dispatch.  This
+ *  can make it easier to invoke that routine at the end of the interrupt
+ *  sequence (if a dispatch is necessary).
+ */
+
+SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
+
+/*
+ *  Nothing prevents the porter from declaring more CPU specific variables.
+ */
+
+/* XXX: if needed, put more variables here */
+
+/*
+ *  The size of the floating point context area.  On some CPUs this
+ *  will not be a "sizeof" because the format of the floating point
+ *  area is not defined -- only the size is.  This is usually on
+ *  CPUs with a "floating point save context" instruction.
+ */
+
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/*
+ *  Amount of extra stack (above minimum stack size) required by
+ *  system initialization thread.  Remember that in a multiprocessor
+ *  system the system intialization thread becomes the MP server thread.
+ */
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/*
+ *  This defines the number of entries in the ISR_Vector_table managed
+ *  by RTEMS.
+ */
+
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/*
+ *  Should be large enough to run all RTEMS tests.  This insures
+ *  that a "reasonable" small application should not have any problems.
+ */
+
+#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))
+
+/*
+ *  CPU's worst alignment requirement for data types on a byte boundary.  This
+ *  alignment does not take into account the requirements for the stack.
+ */
+
+#define CPU_ALIGNMENT              8
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  heap handler.  This alignment requirement may be stricter than that
+ *  for the data types alignment specified by CPU_ALIGNMENT.  It is
+ *  common for the heap to follow the same alignment requirement as
+ *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
+ *  then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
+
+/*
+ *  This number corresponds to the byte alignment requirement for memory
+ *  buffers allocated by the partition manager.  This alignment requirement
+ *  may be stricter than that for the data types alignment specified by
+ *  CPU_ALIGNMENT.  It is common for the partition to follow the same
+ *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
+ *  enough for the partition, then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  stack.  This alignment requirement may be stricter than that for the
+ *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
+ *  is strict enough for the stack, then this should be set to 0.
+ *
+ *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
+ */
+
+#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
+
+/* ISR handler macros */
+
+/*
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in _level.
+ */
+
+#define _CPU_ISR_Disable( _int_level ) \
+  do{ \
+	_int_level = mips_disable_interrupts(); \
+  }while(0)
+
+/*
+ *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  _level is not modified.
+ */
+
+#define _CPU_ISR_Enable( _level )  \
+  do{ \
+	mips_enable_interrupts(_level); \
+  }while(0)
+
+/*
+ *  This temporarily restores the interrupt to _level before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter _level is not
+ * modified.
+ */
+
+#define _CPU_ISR_Flash( _xlevel ) \
+  do{ \
+	int _scratch; \
+	_CPU_ISR_Enable( _xlevel ); \
+	_CPU_ISR_Disable( _scratch ); \
+  }while(0)
+
+/*
+ *  Map interrupt level in task mode onto the hardware that the CPU
+ *  actually provides.  Currently, interrupt levels which do not
+ *  map onto the CPU in a generic fashion are undefined.  Someday,
+ *  it would be nice if these were "mapped" by the application
+ *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ *  8 - 255 would be available for bsp/application specific meaning.
+ *  This could be used to manage a programmable interrupt controller
+ *  via the rtems_task_mode directive.
+ */
+extern void _CPU_ISR_Set_level( unsigned32 _new_level );
+
+/* end of ISR handler macros */
+
+/* Context handler macros */
+
+/*
+ *  Initialize the context to a state suitable for starting a
+ *  task after a context restore operation.  Generally, this
+ *  involves:
+ *
+ *     - setting a starting address
+ *     - preparing the stack
+ *     - preparing the stack and frame pointers
+ *     - setting the proper interrupt level in the context
+ *     - initializing the floating point context
+ *
+ *  This routine generally does not set any unnecessary register
+ *  in the context.  The state of the "general data" registers is
+ *  undefined at task start time.
+ *
+ *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
+ *        point thread.  This is typically only used on CPUs where the
+ *        FPU may be easily disabled by software such as on the SPARC
+ *        where the PSR contains an enable FPU bit.
+ */
+
+#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
+                                 _isr, _entry_point, _is_fp ) \
+  { \
+ 	unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
+  	_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
+  	(_the_context)->sp = _stack_tmp; \
+  	(_the_context)->fp = _stack_tmp; \
+	(_the_context)->ra = (unsigned64)_entry_point; \
+	(_the_context)->c0_sr = 0; \
+  }
+
+/*
+ *  This routine is responsible for somehow restarting the currently
+ *  executing task.  If you are lucky, then all that is necessary
+ *  is restoring the context.  Otherwise, there will need to be
+ *  a special assembly routine which does something special in this
+ *  case.  Context_Restore should work most of the time.  It will
+ *  not work if restarting self conflicts with the stack frame
+ *  assumptions of restoring a context.
+ */
+
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+/*
+ *  The purpose of this macro is to allow the initial pointer into
+ *  A floating point context area (used to save the floating point
+ *  context) to be at an arbitrary place in the floating point
+ *  context area.
+ *
+ *  This is necessary because some FP units are designed to have
+ *  their context saved as a stack which grows into lower addresses.
+ *  Other FP units can be saved by simply moving registers into offsets
+ *  from the base of the context area.  Finally some FP units provide
+ *  a "dump context" instruction which could fill in from high to low
+ *  or low to high based on the whim of the CPU designers.
+ */
+
+#define _CPU_Context_Fp_start( _base, _offset ) \
+   ( (char *) (_base) + (_offset) )
+
+/*
+ *  This routine initializes the FP context area passed to it to.
+ *  There are a few standard ways in which to initialize the
+ *  floating point context.  The code included for this macro assumes
+ *  that this is a CPU in which a "initial" FP context was saved into
+ *  _CPU_Null_fp_context and it simply copies it to the destination
+ *  context passed to it.
+ *
+ *  Other models include (1) not doing anything, and (2) putting
+ *  a "null FP status word" in the correct place in the FP context.
+ */
+
+#define _CPU_Context_Initialize_fp( _destination ) \
+  { \
+   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
+  }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/*
+ *  This routine copies _error into a known place -- typically a stack
+ *  location or a register, optionally disables interrupts, and
+ *  halts/stops the CPU.
+ */
+
+#define _CPU_Fatal_halt( _error ) \
+  { \
+    mips_disable_global_interrupts(); \
+    mips_fatal_error(_error); \
+  }
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/*
+ *  This routine sets _output to the bit number of the first bit
+ *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
+ *  This type may be either 16 or 32 bits wide although only the 16
+ *  least significant bits will be used.
+ *
+ *  There are a number of variables in using a "find first bit" type
+ *  instruction.
+ *
+ *    (1) What happens when run on a value of zero?
+ *    (2) Bits may be numbered from MSB to LSB or vice-versa.
+ *    (3) The numbering may be zero or one based.
+ *    (4) The "find first bit" instruction may search from MSB or LSB.
+ *
+ *  RTEMS guarantees that (1) will never happen so it is not a concern.
+ *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
+ *  _CPU_Priority_bits_index().  These three form a set of routines
+ *  which must logically operate together.  Bits in the _value are
+ *  set and cleared based on masks built by _CPU_Priority_mask().
+ *  The basic major and minor values calculated by _Priority_Major()
+ *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
+ *  to properly range between the values returned by the "find first bit"
+ *  instruction.  This makes it possible for _Priority_Get_highest() to
+ *  calculate the major and directly index into the minor table.
+ *  This mapping is necessary to ensure that 0 (a high priority major/minor)
+ *  is the first bit found.
+ *
+ *  This entire "find first bit" and mapping process depends heavily
+ *  on the manner in which a priority is broken into a major and minor
+ *  components with the major being the 4 MSB of a priority and minor
+ *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ *  to the lowest priority.
+ *
+ *  If your CPU does not have a "find first bit" instruction, then
+ *  there are ways to make do without it.  Here are a handful of ways
+ *  to implement this in software:
+ *
+ *    - a series of 16 bit test instructions
+ *    - a "binary search using if's"
+ *    - _number = 0
+ *      if _value > 0x00ff
+ *        _value >>=8
+ *        _number = 8;
+ *
+ *      if _value > 0x0000f
+ *        _value >=8
+ *        _number += 4
+ *
+ *      _number += bit_set_table[ _value ]
+ *
+ *    where bit_set_table[ 16 ] has values which indicate the first
+ *      bit set
+ */
+
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+    (_output) = 0;   /* do something to prevent warnings */ \
+  }
+
+#endif
+
+/* end of Bitfield handler macros */
+
+/*
+ *  This routine builds the mask which corresponds to the bit fields
+ *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
+ *  for that routine.
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 1 << (_bit_number) )
+
+#endif
+
+/*
+ *  This routine translates the bit numbers returned by
+ *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
+ *  a major or minor component of a priority.  See the discussion
+ *  for that routine.
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+#endif
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/*
+ *  _CPU_Initialize
+ *
+ *  This routine performs CPU dependent initialization.
+ */
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)
+);
+
+/*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_ISR_install_vector
+ *
+ *  This routine installs an interrupt vector.
+ */
+
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_Install_interrupt_stack
+ *
+ *  This routine installs the hardware interrupt stack pointer.
+ *
+ *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *         is TRUE.
+ */
+
+void _CPU_Install_interrupt_stack( void );
+
+/*
+ *  _CPU_Internal_threads_Idle_thread_body
+ *
+ *  This routine is the CPU dependent IDLE thread body.
+ *
+ *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
+ *         is TRUE.
+ */
+
+void _CPU_Thread_Idle_body( void );
+
+/*
+ *  _CPU_Context_switch
+ *
+ *  This routine switches from the run context to the heir context.
+ */
+
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generallu used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ */
+
+void _CPU_Context_restore(
+  Context_Control *new_context
+);
+
+/*
+ *  _CPU_Context_save_fp
+ *
+ *  This routine saves the floating point context passed to it.
+ */
+
+void _CPU_Context_save_fp(
+  void **fp_context_ptr
+);
+
+/*
+ *  _CPU_Context_restore_fp
+ *
+ *  This routine restores the floating point context passed to it.
+ */
+
+void _CPU_Context_restore_fp(
+  void **fp_context_ptr
+);
+
+/*  The following routine swaps the endian format of an unsigned int.
+ *  It must be static because it is referenced indirectly.
+ *
+ *  This version will work on any processor, but if there is a better
+ *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ *
+ *     swap least significant two bytes with 16-bit rotate
+ *     swap upper and lower 16-bits
+ *     swap most significant two bytes with 16-bit rotate
+ *
+ *  Some CPUs have special instructions which swap a 32-bit quantity in
+ *  a single instruction (e.g. i486).  It is probably best to avoid
+ *  an "endian swapping control bit" in the CPU.  One good reason is
+ *  that interrupts would probably have to be disabled to insure that
+ *  an interrupt does not try to access the same "chunk" with the wrong
+ *  endian.  Another good reason is that on some CPUs, the endian bit
+ *  endianness for ALL fetches -- both code and data -- so the code
+ *  will be fetched incorrectly.
+ */
+ 
+static inline unsigned int CPU_swap_u32(
+  unsigned int value
+)
+{
+  unsigned32 byte1, byte2, byte3, byte4, swapped;
+ 
+  byte4 = (value >> 24) & 0xff;
+  byte3 = (value >> 16) & 0xff;
+  byte2 = (value >> 8)  & 0xff;
+  byte1 =  value        & 0xff;
+ 
+  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
+  return( swapped );
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/mips64orion/cpu_asm.S b/c/src/exec/score/cpu/mips64orion/cpu_asm.S
new file mode 100644
index 0000000000..d9e38231bf
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/cpu_asm.S
@@ -0,0 +1,972 @@
+/*  cpu_asm.S 
+ *
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu_asm.c,v 1.5 1995/09/26 19:25:39 joel Exp
+ */
+/* @(#)cpu_asm.S       08/20/96     1.15 */
+
+#include "cpu_asm.h"
+
+#include "iregdef.h"
+#include "idtcpu.h"
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+        .globl  name;                           \
+        .ent    name;                           \
+name:;                                          \
+        .frame  frm_reg,offset,ret_reg
+#define ENDFRAME(name)                          \
+        .end name
+
+
+#define EXCP_STACK_SIZE (NREGS*R_SZ)
+
+#if __ghs__
+#define sd sw
+#define ld lw
+#define dmtc0 mtc0
+#define dsll sll
+#define dmfc0 mfc0
+#endif
+
+#if 1  /* 32 bit unsigned32 types */
+#define sint sw
+#define lint lw
+#define stackadd addiu
+#define intadd addu
+#define SZ_INT 4
+#define SZ_INT_POW2 2
+#else /* 64 bit unsigned32 types */
+#define sint dw
+#define lint dw
+#define stackadd daddiu
+#define intadd daddu
+#define SZ_INT 8
+#define SZ_INT_POW2 3
+#endif
+
+#ifdef __GNUC__
+#define EXTERN(x,size) .extern x,size
+#else
+#define EXTERN(x,size)
+#endif
+
+/* NOTE: these constants must match the Context_Control structure in cpu.h */
+#define S0_OFFSET 0
+#define S1_OFFSET 1
+#define S2_OFFSET 2
+#define S3_OFFSET 3
+#define S4_OFFSET 4
+#define S5_OFFSET 5
+#define S6_OFFSET 6
+#define S7_OFFSET 7
+#define SP_OFFSET 8
+#define FP_OFFSET 9
+#define RA_OFFSET 10
+#define C0_SR_OFFSET 11
+#define C0_EPC_OFFSET 12
+
+/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
+#define FP0_OFFSET  0 
+#define FP1_OFFSET  1 
+#define FP2_OFFSET  2 
+#define FP3_OFFSET  3 
+#define FP4_OFFSET  4 
+#define FP5_OFFSET  5 
+#define FP6_OFFSET  6 
+#define FP7_OFFSET  7 
+#define FP8_OFFSET  8 
+#define FP9_OFFSET  9 
+#define FP10_OFFSET 10 
+#define FP11_OFFSET 11 
+#define FP12_OFFSET 12 
+#define FP13_OFFSET 13 
+#define FP14_OFFSET 14 
+#define FP15_OFFSET 15 
+#define FP16_OFFSET 16 
+#define FP17_OFFSET 17 
+#define FP18_OFFSET 18 
+#define FP19_OFFSET 19 
+#define FP20_OFFSET 20 
+#define FP21_OFFSET 21 
+#define FP22_OFFSET 22 
+#define FP23_OFFSET 23 
+#define FP24_OFFSET 24 
+#define FP25_OFFSET 25 
+#define FP26_OFFSET 26 
+#define FP27_OFFSET 27 
+#define FP28_OFFSET 28 
+#define FP29_OFFSET 29 
+#define FP30_OFFSET 30 
+#define FP31_OFFSET 31 
+
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ */
+
+#if 0
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+}
+#endif
+/* return the current exception level for the 4650 */
+FRAME(_CPU_ISR_Get_level,sp,0,ra)
+	mfc0 v0,C0_SR
+	nop
+	andi v0,SR_EXL 
+	srl v0,1
+	j ra
+ENDFRAME(_CPU_ISR_Get_level)
+
+FRAME(_CPU_ISR_Set_level,sp,0,ra)
+	nop
+	mfc0 a0,C0_SR
+	nop
+	andi a0,SR_EXL 
+	beqz a0,_CPU_ISR_Set_1		/* normalize a0 */
+	nop
+	li a0,1         
+_CPU_ISR_Set_1:
+	beq v0,a0,_CPU_ISR_Set_exit	/* if (current_level != new_level ) */
+	nop
+	bnez a0,_CPU_ISR_Set_2
+	nop
+	nop
+	mfc0 t0,C0_SR
+	nop
+	li t1,~SR_EXL
+	and t0,t1
+	nop
+	mtc0 t0,C0_SR                   /* disable exception level */
+	nop
+	j ra 
+	nop
+_CPU_ISR_Set_2:
+	nop
+	mfc0 t0,C0_SR
+	nop
+	li t1,~SR_IE
+	and t0,t1
+	nop
+	mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
+	nop
+	ori t0,SR_EXL|SR_IE		/* enable exception level  */
+	nop
+	mtc0 t0,C0_SR         
+	nop
+_CPU_ISR_Set_exit:
+	j ra
+	nop
+ENDFRAME(_CPU_ISR_Set_level)
+
+/*
+ *  _CPU_Context_save_fp_context
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+/* void _CPU_Context_save_fp(
+ * void **fp_context_ptr
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_save_fp,sp,0,ra)
+	.set noat
+	ld a1,(a0)
+	swc1 $f0,FP0_OFFSET*4(a1)
+	swc1 $f1,FP1_OFFSET*4(a1)
+	swc1 $f2,FP2_OFFSET*4(a1)
+	swc1 $f3,FP3_OFFSET*4(a1)
+	swc1 $f4,FP4_OFFSET*4(a1)
+	swc1 $f5,FP5_OFFSET*4(a1)
+	swc1 $f6,FP6_OFFSET*4(a1)
+	swc1 $f7,FP7_OFFSET*4(a1)
+	swc1 $f8,FP8_OFFSET*4(a1)
+	swc1 $f9,FP9_OFFSET*4(a1)
+	swc1 $f10,FP10_OFFSET*4(a1)
+	swc1 $f11,FP11_OFFSET*4(a1)
+	swc1 $f12,FP12_OFFSET*4(a1)
+	swc1 $f13,FP13_OFFSET*4(a1)
+	swc1 $f14,FP14_OFFSET*4(a1)
+	swc1 $f15,FP15_OFFSET*4(a1)
+	swc1 $f16,FP16_OFFSET*4(a1)
+	swc1 $f17,FP17_OFFSET*4(a1)
+	swc1 $f18,FP18_OFFSET*4(a1)
+	swc1 $f19,FP19_OFFSET*4(a1)
+	swc1 $f20,FP20_OFFSET*4(a1)
+	swc1 $f21,FP21_OFFSET*4(a1)
+	swc1 $f22,FP22_OFFSET*4(a1)
+	swc1 $f23,FP23_OFFSET*4(a1)
+	swc1 $f24,FP24_OFFSET*4(a1)
+	swc1 $f25,FP25_OFFSET*4(a1)
+	swc1 $f26,FP26_OFFSET*4(a1)
+	swc1 $f27,FP27_OFFSET*4(a1)
+	swc1 $f28,FP28_OFFSET*4(a1)
+	swc1 $f29,FP29_OFFSET*4(a1)
+	swc1 $f30,FP30_OFFSET*4(a1)
+	swc1 $f31,FP31_OFFSET*4(a1)
+	j ra
+	nop
+	.set at
+ENDFRAME(_CPU_Context_save_fp)
+
+/*
+ *  _CPU_Context_restore_fp_context
+ *
+ *  This routine is responsible for restoring the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ */
+
+/* void _CPU_Context_restore_fp(
+ * void **fp_context_ptr
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_restore_fp,sp,0,ra)
+	.set noat
+	ld a1,(a0)
+	lwc1 $f0,FP0_OFFSET*4(a1)
+	lwc1 $f1,FP1_OFFSET*4(a1)
+	lwc1 $f2,FP2_OFFSET*4(a1)
+	lwc1 $f3,FP3_OFFSET*4(a1)
+	lwc1 $f4,FP4_OFFSET*4(a1)
+	lwc1 $f5,FP5_OFFSET*4(a1)
+	lwc1 $f6,FP6_OFFSET*4(a1)
+	lwc1 $f7,FP7_OFFSET*4(a1)
+	lwc1 $f8,FP8_OFFSET*4(a1)
+	lwc1 $f9,FP9_OFFSET*4(a1)
+	lwc1 $f10,FP10_OFFSET*4(a1)
+	lwc1 $f11,FP11_OFFSET*4(a1)
+	lwc1 $f12,FP12_OFFSET*4(a1)
+	lwc1 $f13,FP13_OFFSET*4(a1)
+	lwc1 $f14,FP14_OFFSET*4(a1)
+	lwc1 $f15,FP15_OFFSET*4(a1)
+	lwc1 $f16,FP16_OFFSET*4(a1)
+	lwc1 $f17,FP17_OFFSET*4(a1)
+	lwc1 $f18,FP18_OFFSET*4(a1)
+	lwc1 $f19,FP19_OFFSET*4(a1)
+	lwc1 $f20,FP20_OFFSET*4(a1)
+	lwc1 $f21,FP21_OFFSET*4(a1)
+	lwc1 $f22,FP22_OFFSET*4(a1)
+	lwc1 $f23,FP23_OFFSET*4(a1)
+	lwc1 $f24,FP24_OFFSET*4(a1)
+	lwc1 $f25,FP25_OFFSET*4(a1)
+	lwc1 $f26,FP26_OFFSET*4(a1)
+	lwc1 $f27,FP27_OFFSET*4(a1)
+	lwc1 $f28,FP28_OFFSET*4(a1)
+	lwc1 $f29,FP29_OFFSET*4(a1)
+	lwc1 $f30,FP30_OFFSET*4(a1)
+	lwc1 $f31,FP31_OFFSET*4(a1)
+	j ra
+	nop
+	.set at
+ENDFRAME(_CPU_Context_restore_fp)
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ */
+
+/* void _CPU_Context_switch(
+ * Context_Control  *run,
+ * Context_Control  *heir
+ * )
+ * {
+ * }
+ */
+
+FRAME(_CPU_Context_switch,sp,0,ra)
+
+	mfc0 t0,C0_SR
+	li t1,~SR_IE
+	sd t0,C0_SR_OFFSET*8(a0)	/* save status register */
+	and t0,t1
+	mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
+	ori t0,SR_EXL|SR_IE		/* enable exception level to disable interrupts */
+	mtc0 t0,C0_SR
+
+	sd ra,RA_OFFSET*8(a0)           /* save current context */
+	sd sp,SP_OFFSET*8(a0)
+	sd fp,FP_OFFSET*8(a0)
+	sd s0,S0_OFFSET*8(a0)
+	sd s1,S1_OFFSET*8(a0)
+	sd s2,S2_OFFSET*8(a0)
+	sd s3,S3_OFFSET*8(a0)
+	sd s4,S4_OFFSET*8(a0)
+	sd s5,S5_OFFSET*8(a0)
+	sd s6,S6_OFFSET*8(a0)
+	sd s7,S7_OFFSET*8(a0)
+	dmfc0 t0,C0_EPC
+	sd t0,C0_EPC_OFFSET*8(a0)
+
+_CPU_Context_switch_restore:
+	ld s0,S0_OFFSET*8(a1)		/* restore context */
+	ld s1,S1_OFFSET*8(a1)
+	ld s2,S2_OFFSET*8(a1)
+	ld s3,S3_OFFSET*8(a1)
+	ld s4,S4_OFFSET*8(a1)
+	ld s5,S5_OFFSET*8(a1)
+	ld s6,S6_OFFSET*8(a1)
+	ld s7,S7_OFFSET*8(a1)
+	ld fp,FP_OFFSET*8(a1) 
+	ld sp,SP_OFFSET*8(a1)
+	ld ra,RA_OFFSET*8(a1)
+	ld t0,C0_EPC_OFFSET*8(a1)
+	dmtc0 t0,C0_EPC
+	ld t0,C0_SR_OFFSET*8(a1)
+	andi t0,SR_EXL
+	bnez t0,_CPU_Context_1		/* set exception level from restore context */
+	li t0,~SR_EXL
+	mfc0 t1,C0_SR
+	nop
+	and t1,t0
+	mtc0 t1,C0_SR
+_CPU_Context_1:
+	j ra
+	nop
+ENDFRAME(_CPU_Context_switch)
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ */
+
+#if 0
+void _CPU_Context_restore(
+  Context_Control *new_context
+)
+{
+}
+#endif
+
+FRAME(_CPU_Context_restore,sp,0,ra)
+	dadd a1,a0,zero
+	j _CPU_Context_switch_restore
+	nop
+ENDFRAME(_CPU_Context_restore)
+
+EXTERN(_ISR_Nest_level, SZ_INT)
+EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
+EXTERN(_Context_Switch_necessary,SZ_INT)
+EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
+.extern _Thread_Dispatch
+.extern _ISR_Vector_table
+
+/*  void __ISR_Handler()
+ *
+ *  This routine provides the RTEMS interrupt management.
+ *
+ */
+
+#if 0
+void _ISR_Handler()
+{
+   /*
+    *  This discussion ignores a lot of the ugly details in a real
+    *  implementation such as saving enough registers/state to be
+    *  able to do something real.  Keep in mind that the goal is
+    *  to invoke a user's ISR handler which is written in C and
+    *  uses a certain set of registers.
+    *
+    *  Also note that the exact order is to a large extent flexible.
+    *  Hardware will dictate a sequence for a certain subset of
+    *  _ISR_Handler while requirements for setting
+    */
+
+  /*
+   *  At entry to "common" _ISR_Handler, the vector number must be
+   *  available.  On some CPUs the hardware puts either the vector
+   *  number or the offset into the vector table for this ISR in a
+   *  known place.  If the hardware does not give us this information,
+   *  then the assembly portion of RTEMS for this port will contain
+   *  a set of distinct interrupt entry points which somehow place
+   *  the vector number in a known place (which is safe if another
+   *  interrupt nests this one) and branches to _ISR_Handler.
+   *
+   */
+#endif
+FRAME(_ISR_Handler,sp,0,ra)
+.set noreorder
+#if USE_IDTKIT
+/* IDT/Kit incorrectly adds 4 to EPC before returning.  This compensates */
+	lreg    k0, R_EPC*R_SZ(sp)
+	daddiu    k0,k0,-4
+	sreg    k0, R_EPC*R_SZ(sp)
+	lreg    k0, R_CAUSE*R_SZ(sp)
+	li	k1, ~CAUSE_BD
+	and     k0, k1 
+	sreg    k0, R_CAUSE*R_SZ(sp)
+#endif
+	
+/* save registers not already saved by IDT/sim */
+	stackadd sp,sp,-EXCP_STACK_SIZE /* store ra on the stack */
+
+	sreg    ra, R_RA*R_SZ(sp)
+	sreg    v0, R_V0*R_SZ(sp)
+	sreg    v1, R_V1*R_SZ(sp)
+	sreg    a0, R_A0*R_SZ(sp)
+	sreg    a1, R_A1*R_SZ(sp)
+	sreg    a2, R_A2*R_SZ(sp)
+	sreg    a3, R_A3*R_SZ(sp)
+	sreg    t0, R_T0*R_SZ(sp)
+	sreg    t1, R_T1*R_SZ(sp)
+	sreg    t2, R_T2*R_SZ(sp)
+	sreg    t3, R_T3*R_SZ(sp)
+	sreg    t4, R_T4*R_SZ(sp)
+	sreg    t5, R_T5*R_SZ(sp)
+	sreg    t6, R_T6*R_SZ(sp)
+	sreg    t7, R_T7*R_SZ(sp)
+	mflo    k0
+	sreg    t8, R_T8*R_SZ(sp)
+	sreg    k0, R_MDLO*R_SZ(sp)
+	sreg    t9, R_T9*R_SZ(sp)
+	mfhi    k0
+	sreg    gp, R_GP*R_SZ(sp)
+	sreg    fp, R_FP*R_SZ(sp)
+	sreg    k0, R_MDHI*R_SZ(sp)
+	.set noat
+	sreg    AT, R_AT*R_SZ(sp)
+	.set at
+
+	stackadd sp,sp,-40		/* store ra on the stack */
+	sd ra,32(sp)
+
+/* determine if an interrupt generated this exception */
+	mfc0 k0,C0_CAUSE
+	and k1,k0,CAUSE_EXCMASK
+	bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */
+	mfc0 k1,C0_SR
+	and k0,k1
+	and k0,CAUSE_IPMASK
+	beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */
+	nop
+
+  /*
+   *  save some or all context on stack
+   *  may need to save some special interrupt information for exit
+   *
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if ( _ISR_Nest_level == 0 )
+   *      switch to software interrupt stack
+   *  #endif
+   */
+#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+	lint t0,_ISR_Nest_level
+	beq t0, zero,  _ISR_Handler_1
+	nop
+	/* switch stacks */	
+_ISR_Handler_1:
+#else
+	lint t0,_ISR_Nest_level
+#endif
+  /*
+   *  _ISR_Nest_level++;
+   */
+	addi t0,t0,1
+	sint t0,_ISR_Nest_level
+  /*
+   *  _Thread_Dispatch_disable_level++;
+   */
+	lint t1,_Thread_Dispatch_disable_level
+	addi t1,t1,1
+	sint t1,_Thread_Dispatch_disable_level
+#if 0
+	nop
+	j _ISR_Handler_4
+	nop
+  /*
+   *  while ( interrupts_pending(cause_reg) ) {
+   *     vector = BITFIELD_TO_INDEX(cause_reg);
+   *     (*_ISR_Vector_table[ vector ])( vector );
+   *  }
+   */
+_ISR_Handler_2:
+/* software interrupt priorities can be applied here */
+	li t1,-1
+/* convert bit field into interrupt index */
+_ISR_Handler_3:
+	andi t2,t0,1
+	addi t1,1
+	beql t2,zero,_ISR_Handler_3
+	dsrl t0,1
+	li t1,7
+	dsll t1,3			/* convert index to byte offset (*8) */
+	la t3,_ISR_Vector_table
+	intadd t1,t3
+	lint t1,(t1)
+	jalr t1
+	nop
+	j _ISR_Handler_5
+	nop
+_ISR_Handler_4:
+	mfc0 t0,C0_CAUSE
+	andi t0,CAUSE_IPMASK
+	bne t0,zero,_ISR_Handler_2
+	dsrl t0,t0,8
+_ISR_Handler_5:
+#else
+	nop
+	li t1,7
+	dsll t1,t1,SZ_INT_POW2
+	la t3,_ISR_Vector_table
+	intadd t1,t3
+	lint t1,(t1)
+	jalr t1
+	nop
+#endif
+  /*
+   *  --_ISR_Nest_level;
+   */
+        lint t2,_ISR_Nest_level
+	addi t2,t2,-1
+        sint t2,_ISR_Nest_level
+  /*
+   *  --_Thread_Dispatch_disable_level;
+   */
+	lint t1,_Thread_Dispatch_disable_level
+	addi t1,t1,-1
+	sint t1,_Thread_Dispatch_disable_level
+  /*
+   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
+   *    goto the label "exit interrupt (simple case)"
+   */
+	or t0,t2,t1
+	bne t0,zero,_ISR_Handler_exit
+	nop
+  /*
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    restore stack
+   *  #endif
+   *  
+   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
+   *    goto the label "exit interrupt (simple case)"
+   */
+	lint t0,_Context_Switch_necessary
+	lint t1,_ISR_Signals_to_thread_executing
+	or t0,t0,t1
+	beq t0,zero,_ISR_Handler_exit
+	nop
+
+  /*
+   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+   */
+	jal _Thread_Dispatch
+	nop
+  /*
+   *  prepare to get out of interrupt
+   *  return from interrupt  (maybe to _ISR_Dispatch)
+   *
+   *  LABEL "exit interrupt (simple case):
+   *  prepare to get out of interrupt
+   *  return from interrupt
+   */
+_ISR_Handler_exit:
+	ld ra,32(sp)
+	stackadd sp,sp,40
+
+/* restore interrupt context from stack */
+	lreg    k0, R_MDLO*R_SZ(sp)
+	mtlo    k0
+	lreg    k0, R_MDHI*R_SZ(sp)
+	lreg    a2, R_A2*R_SZ(sp)
+	mthi    k0
+	lreg    a3, R_A3*R_SZ(sp)
+	lreg    t0, R_T0*R_SZ(sp)
+	lreg    t1, R_T1*R_SZ(sp)
+	lreg    t2, R_T2*R_SZ(sp)
+	lreg    t3, R_T3*R_SZ(sp)
+	lreg    t4, R_T4*R_SZ(sp)
+	lreg    t5, R_T5*R_SZ(sp)
+	lreg    t6, R_T6*R_SZ(sp)
+	lreg    t7, R_T7*R_SZ(sp)
+	lreg    t8, R_T8*R_SZ(sp)
+	lreg    t9, R_T9*R_SZ(sp)
+	lreg    gp, R_GP*R_SZ(sp)
+	lreg    fp, R_FP*R_SZ(sp)
+	lreg    ra, R_RA*R_SZ(sp)
+	lreg    a0, R_A0*R_SZ(sp)
+	lreg    a1, R_A1*R_SZ(sp)
+	lreg    v1, R_V1*R_SZ(sp)
+	lreg    v0, R_V0*R_SZ(sp)
+	.set noat
+	lreg    AT, R_AT*R_SZ(sp)
+	.set at
+
+	stackadd sp,sp,EXCP_STACK_SIZE /* store ra on the stack */
+
+#if USE_IDTKIT
+/* we handled exception, so return non-zero value */
+	li v0,1
+#endif
+
+_ISR_Handler_quick_exit:
+#ifdef USE_IDTKIT
+	j ra
+#else
+	eret
+#endif
+	nop
+
+_ISR_Handler_prom_exit:
+#ifdef CPU_R3000
+	la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+	la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+	j       k0
+	nop
+
+       .set    reorder
+
+ENDFRAME(_ISR_Handler)
+
+
+FRAME(mips_enable_interrupts,sp,0,ra)
+	mfc0 t0,C0_SR		/* get status reg */
+	nop
+	or t0,t0,a0		 
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_enable_interrupts)
+
+FRAME(mips_disable_interrupts,sp,0,ra)
+	mfc0 v0,C0_SR		/* get status reg */
+	li t1,SR_IMASK		/* t1 = load interrupt mask word */
+	not t0,t1		/* t0 = ~t1 */
+	and t0,v0		/* clear imask bits */
+	mtc0 t0,C0_SR		/* save status reg */
+	and v0,t1		/* mask return value (only return imask bits) */
+	jr ra
+	nop
+ENDFRAME(mips_disable_interrupts)
+
+FRAME(mips_enable_global_interrupts,sp,0,ra)
+	mfc0 t0,C0_SR		/* get status reg */
+	nop
+	ori t0,SR_IE
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_enable_global_interrupts)
+
+FRAME(mips_disable_global_interrupts,sp,0,ra)
+	li t1,SR_IE
+	mfc0 t0,C0_SR		/* get status reg */
+	not t1
+	and t0,t1
+	mtc0 t0,C0_SR		/* save updated status reg */
+	j ra
+	nop
+ENDFRAME(mips_disable_global_interrupts)
+
+/* return the value of the status register in v0.  Used for debugging */
+FRAME(mips_get_sr,sp,0,ra)
+	mfc0 v0,C0_SR
+	j ra
+	nop
+ENDFRAME(mips_get_sr)
+
+FRAME(mips_break,sp,0,ra)
+#if 1
+	break 0x0
+	j mips_break
+#else
+	j ra
+#endif
+	nop
+ENDFRAME(mips_break)
+
+/*PAGE
+ *
+ *  _CPU_Internal_threads_Idle_thread_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ */
+
+FRAME(_CPU_Thread_Idle_body,sp,0,ra)
+	wait			/* enter low power mode */
+	j _CPU_Thread_Idle_body
+	nop
+ENDFRAME(_CPU_Thread_Idle_body)
+
+#define VEC_CODE_LENGTH 10*4
+
+/**************************************************************************
+**
+**	init_exc_vecs() - moves the exception code into the addresses
+**			  reserved for exception vectors
+**
+**	UTLB Miss exception vector at address 0x80000000
+**
+**	General exception vector at address 0x80000080
+**
+**	RESET exception vector is at address 0xbfc00000
+**
+***************************************************************************/
+
+#define INITEXCFRM ((2*4)+4)		/* ra + 2 arguments */
+FRAME(init_exc_vecs,sp,0,ra)
+/* This code yanked from SIM */
+#if defined(CPU_R3000)
+	.set	noreorder
+	la	t1,exc_utlb_code
+	la	t2,exc_norm_code
+	li	t3,UT_VEC
+	li	t4,E_VEC
+	li	t5,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	lw	t7,0(t2)
+	sw	t6,0(t3)
+	sw	t7,0(t4)
+	addiu	t1,4
+	addiu	t3,4
+	addiu	t4,4
+	subu	t5,4
+	bne	t5,zero,1b
+	addiu	t2,4
+	move	t5,ra		# assumes clear_cache doesnt use t5
+	li	a0,UT_VEC
+	jal	clear_cache
+	li	a1,VEC_CODE_LENGTH
+	nop
+	li	a0,E_VEC
+	jal	clear_cache
+	li	a1,VEC_CODE_LENGTH
+	move	ra,t5		# restore ra
+	j	ra
+	nop
+	.set	reorder
+#endif
+#if defined(CPU_R4000)
+	.set reorder
+	move	t5,ra		# assumes clear_cache doesnt use t5
+
+	/* TLB exception vector */
+	la	t1,exc_tlb_code
+	li	t2,T_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,T_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	la	t1,exc_xtlb_code
+	li	t2,X_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	/* extended TLB exception vector */
+	li	a0,X_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	/* cache error exception vector */
+	la	t1,exc_cache_code
+	li	t2,C_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,C_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	/* normal exception vector */
+	la	t1,exc_norm_code
+	li	t2,E_VEC |K1BASE
+	li	t3,VEC_CODE_LENGTH
+1:
+	lw	t6,0(t1)
+	addiu	t1,4
+	subu	t3,4
+	sw	t6,0(t2)
+	addiu	t2,4
+	bne	t3,zero,1b
+
+	li	a0,E_VEC
+	li	a1,VEC_CODE_LENGTH
+	jal	clear_cache
+
+	move	ra,t5		# restore ra
+	j	ra
+#endif
+ENDFRAME(init_exc_vecs)
+
+
+#if defined(CPU_R4000)
+FRAME(exc_tlb_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_tlb_code)
+
+
+FRAME(exc_xtlb_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_xtlb_code)
+
+
+FRAME(exc_cache_code,sp,0,ra)
+#ifdef CPU_R3000
+        la      k0, (R_VEC+((48)*8))
+#endif
+
+#ifdef CPU_R4000
+        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
+#endif
+        j       k0
+	nop
+
+ENDFRAME(exc_cache_code)
+
+
+FRAME(exc_norm_code,sp,0,ra)
+	la	k0, _ISR_Handler /* generic external int hndlr */
+	j	k0
+	nop
+	subu	sp, EXCP_STACK_SIZE		/* set up local stack frame */
+ENDFRAME(exc_norm_code)
+#endif
+
+/**************************************************************************
+**
+** enable_int(mask) - enables interrupts - mask is positioned so it only
+**                      needs to be or'ed into the status reg. This
+**                      also does some other things !!!! caution should
+**                      be used if invoking this while in the middle
+**                      of a debugging session where the client may have
+**                      nested interrupts.
+**
+****************************************************************************/
+FRAME(enable_int,sp,0,ra)
+        .set    noreorder
+        mfc0    t0,C0_SR
+        or      a0,1
+        or      t0,a0
+        mtc0    t0,C0_SR
+        j       ra
+        nop
+        .set    reorder
+ENDFRAME(enable_int)
+
+
+/***************************************************************************
+**
+**      disable_int(mask) - disable the interrupt - mask is the complement
+**                          of the bits to be cleared - i.e. to clear ext int
+**                          5 the mask would be - 0xffff7fff
+**
+****************************************************************************/
+FRAME(disable_int,sp,0,ra)
+        .set    noreorder
+        mfc0    t0,C0_SR
+        nop
+        and     t0,a0
+        mtc0    t0,C0_SR
+        j       ra
+        nop
+ENDFRAME(disable_int)
+
+
diff --git a/c/src/exec/score/cpu/mips64orion/cpu_asm.h b/c/src/exec/score/cpu/mips64orion/cpu_asm.h
new file mode 100644
index 0000000000..9696204962
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/cpu_asm.h
@@ -0,0 +1,115 @@
+/*
+ *  cpu_asm.h
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  cpu_asm.h,v 1.4 1995/09/26 19:25:39 joel Exp
+ *
+ */
+/* @(#)cpu_asm.h       08/20/96     1.2 */
+
+#ifndef __CPU_ASM_h
+#define __CPU_ASM_h
+
+/* pull in the generated offsets */
+
+/* #include <rtems/score/offsets.h> */
+
+/*
+ * Hardware General Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Floating Point Registers
+ */
+
+#define R_FP0 	0
+#define R_FP1 	1
+#define R_FP2 	2
+#define R_FP3 	3
+#define R_FP4 	4
+#define R_FP5 	5
+#define R_FP6 	6
+#define R_FP7 	7
+#define R_FP8 	8
+#define R_FP9 	9
+#define R_FP10 	10
+#define R_FP11 	11
+#define R_FP12 	12
+#define R_FP13 	13
+#define R_FP14 	14
+#define R_FP15 	15
+#define R_FP16 	16
+#define R_FP17 	17
+#define R_FP18 	18
+#define R_FP19 	19
+#define R_FP20 	20
+#define R_FP21 	21
+#define R_FP22 	22
+#define R_FP23	23
+#define R_FP24 	24
+#define R_FP25 	25
+#define R_FP26 	26
+#define R_FP27 	27
+#define R_FP28 	28
+#define R_FP29 	29
+#define R_FP30 	30
+#define R_FP31 	31
+
+/*
+ * Hardware Control Registers
+ */
+
+/* put something here */
+
+/*
+ * Calling Convention
+ */
+
+/* put something here */
+
+/*
+ * Temporary registers
+ */
+
+/* put something here */
+
+/*
+ * Floating Point Registers - SW Conventions
+ */
+
+/* put something here */
+
+/*
+ * Temporary floating point registers
+ */
+
+/* put something here */
+
+#endif
+
+/* end of file */
diff --git a/c/src/exec/score/cpu/mips64orion/idtcpu.h b/c/src/exec/score/cpu/mips64orion/idtcpu.h
new file mode 100644
index 0000000000..833c5ebe02
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/idtcpu.h
@@ -0,0 +1,439 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+** idtcpu.h -- cpu related defines
+*/
+
+#ifndef _IDTCPU_H__
+#define _IDTCPU_H__
+
+/*
+ * 950313: Ketan added Register definition for XContext reg.
+ *               added define for WAIT instruction.
+ * 950421: Ketan added Register definition for Config reg (R3081)
+ */
+
+/*
+** memory configuration and mapping
+*/
+#define K0BASE	0x80000000
+#define K0SIZE	0x20000000
+#define K1BASE	0xa0000000
+#define K1SIZE	0x20000000
+#define K2BASE	0xc0000000
+#define K2SIZE	0x20000000
+#if defined(CPU_R4000)
+#define KSBASE	0xe0000000
+#define KSSIZE	0x20000000
+#endif
+
+#define KUBASE	0
+#define KUSIZE	0x80000000
+
+/*
+** Exception Vectors
+*/
+#if defined(CPU_R3000)
+#define	UT_VEC	K0BASE			/* utlbmiss vector */
+#define E_VEC	(K0BASE+0x80)		/* exception vevtor */
+#endif
+#if defined(CPU_R4000)
+#define	T_VEC	(K0BASE+0x000)		/* tlbmiss vector */
+#define X_VEC	(K0BASE+0x080)		/* xtlbmiss vector */
+#define C_VEC	(K0BASE+0x100)		/* cache error vector */
+#define E_VEC	(K0BASE+0x180)		/* exception vector */
+#endif
+#define	R_VEC	(K1BASE+0x1fc00000)	/* reset vector */
+
+/*
+** Address conversion macros
+*/
+#ifdef CLANGUAGE
+#define CAST(as) (as)
+#else
+#define CAST(as)
+#endif
+#define	K0_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* kseg0 to kseg1 */
+#define	K1_TO_K0(x)	(CAST(unsigned)(x)&0x9FFFFFFF)	/* kseg1 to kseg0 */
+#define	K0_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg0 to physical */
+#define	K1_TO_PHYS(x)	(CAST(unsigned)(x)&0x1FFFFFFF)	/* kseg1 to physical */
+#define	PHYS_TO_K0(x)	(CAST(unsigned)(x)|0x80000000)	/* physical to kseg0 */
+#define	PHYS_TO_K1(x)	(CAST(unsigned)(x)|0xA0000000)	/* physical to kseg1 */
+
+/*
+**	Cache size constants
+*/
+#define	MINCACHE	0x200		/* 512       For 3041. */
+#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+
+#if defined(CPU_R4000)
+/* R4000 configuration register definitions */
+#define CFG_CM		0x80000000	/* Master-Checker mode */
+#define CFG_ECMASK	0x70000000	/* System Clock Ratio */
+#define CFG_ECBY2	0x00000000 	/* divide by 2 */
+#define CFG_ECBY3	0x10000000 	/* divide by 3 */
+#define CFG_ECBY4	0x20000000 	/* divide by 4 */
+#define CFG_EPMASK	0x0f000000	/* Transmit data pattern */
+#define CFG_EPD		0x00000000	/* D */
+#define CFG_EPDDX	0x01000000	/* DDX */
+#define CFG_EPDDXX	0x02000000	/* DDXX */
+#define CFG_EPDXDX	0x03000000	/* DXDX */
+#define CFG_EPDDXXX	0x04000000	/* DDXXX */
+#define CFG_EPDDXXXX	0x05000000	/* DDXXXX */
+#define CFG_EPDXXDXX	0x06000000	/* DXXDXX */
+#define CFG_EPDDXXXXX	0x07000000	/* DDXXXXX */
+#define CFG_EPDXXXDXXX	0x08000000	/* DXXXDXXX */
+#define CFG_SBMASK	0x00c00000	/* Secondary cache block size */
+#define CFG_SBSHIFT	22
+#define CFG_SB4		0x00000000	/* 4 words */
+#define CFG_SB8		0x00400000	/* 8 words */
+#define CFG_SB16	0x00800000	/* 16 words */
+#define CFG_SB32	0x00c00000	/* 32 words */
+#define CFG_SS		0x00200000	/* Split secondary cache */
+#define CFG_SW		0x00100000	/* Secondary cache port width */
+#define CFG_EWMASK	0x000c0000	/* System port width */
+#define CFG_EWSHIFT	18
+#define CFG_EW64	0x00000000	/* 64 bit */
+#define CFG_EW32	0x00010000	/* 32 bit */
+#define CFG_SC		0x00020000	/* Secondary cache absent */
+#define CFG_SM		0x00010000	/* Dirty Shared mode disabled */
+#define CFG_BE		0x00008000	/* Big Endian */
+#define CFG_EM		0x00004000	/* ECC mode enable */
+#define CFG_EB		0x00002000	/* Block ordering */
+#define CFG_ICMASK	0x00000e00	/* Instruction cache size */
+#define CFG_ICSHIFT	9
+#define CFG_DCMASK	0x000001c0	/* Data cache size */
+#define CFG_DCSHIFT	6
+#define CFG_IB		0x00000020	/* Instruction cache block size */
+#define CFG_DB		0x00000010	/* Data cache block size */
+#define CFG_CU		0x00000008	/* Update on Store Conditional */
+#define CFG_K0MASK	0x00000007	/* KSEG0 coherency algorithm */
+
+/*
+ * R4000 primary cache mode
+ */
+#define CFG_C_UNCACHED		2
+#define CFG_C_NONCOHERENT	3
+#define CFG_C_COHERENTXCL	4
+#define CFG_C_COHERENTXCLW	5
+#define CFG_C_COHERENTUPD	6
+
+/*
+ * R4000 cache operations (should be in assembler...?)
+ */
+#define Index_Invalidate_I               0x0         /* 0       0 */
+#define Index_Writeback_Inv_D            0x1         /* 0       1 */
+#define Index_Invalidate_SI              0x2         /* 0       2 */
+#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
+#define Index_Load_Tag_I                 0x4         /* 1       0 */
+#define Index_Load_Tag_D                 0x5         /* 1       1 */
+#define Index_Load_Tag_SI                0x6         /* 1       2 */
+#define Index_Load_Tag_SD                0x7         /* 1       3 */
+#define Index_Store_Tag_I                0x8         /* 2       0 */
+#define Index_Store_Tag_D                0x9         /* 2       1 */
+#define Index_Store_Tag_SI               0xA         /* 2       2 */
+#define Index_Store_Tag_SD               0xB         /* 2       3 */
+#define Create_Dirty_Exc_D               0xD         /* 3       1 */
+#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
+#define Hit_Invalidate_I                 0x10        /* 4       0 */
+#define Hit_Invalidate_D                 0x11        /* 4       1 */
+#define Hit_Invalidate_SI                0x12        /* 4       2 */
+#define Hit_Invalidate_SD                0x13        /* 4       3 */
+#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
+#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
+#define Fill_I                           0x14        /* 5       0 */
+#define Hit_Writeback_D                  0x19        /* 6       1 */
+#define Hit_Writeback_SD                 0x1B        /* 6       3 */
+#define Hit_Writeback_I                  0x18        /* 6       0 */
+#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
+#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
+
+#ifndef WAIT
+#define WAIT .word 0x42000020
+#endif WAIT
+
+#ifndef wait 
+#define wait .word 0x42000020
+#endif wait
+
+#endif
+
+/*
+** TLB resource defines
+*/
+#if defined(CPU_R3000)
+#define	N_TLB_ENTRIES	64
+#define TLB_PGSIZE	0x1000
+#define RANDBASE	8
+#define	TLBLO_PFNMASK	0xfffff000
+#define	TLBLO_PFNSHIFT	12
+#define	TLBLO_N		0x800	/* non-cacheable */
+#define	TLBLO_D		0x400	/* writeable */
+#define	TLBLO_V		0x200	/* valid bit */
+#define	TLBLO_G		0x100	/* global access bit */
+
+#define	TLBHI_VPNMASK	0xfffff000
+#define	TLBHI_VPNSHIFT	12
+#define	TLBHI_PIDMASK	0xfc0
+#define	TLBHI_PIDSHIFT	6
+#define	TLBHI_NPID	64
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x00003f00
+#define	TLBINX_INXSHIFT	8
+
+#define	TLBRAND_RANDMASK	0x00003f00
+#define	TLBRAND_RANDSHIFT	8
+
+#define	TLBCTXT_BASEMASK	0xffe00000
+#define	TLBCTXT_BASESHIFT	21
+
+#define	TLBCTXT_VPNMASK		0x001ffffc
+#define	TLBCTXT_VPNSHIFT	2
+#endif
+#if defined(CPU_R4000)
+#define	N_TLB_ENTRIES	48
+
+#define	TLBHI_VPN2MASK	0xffffe000
+#define	TLBHI_PIDMASK	0x000000ff
+#define	TLBHI_NPID	256
+
+#define	TLBLO_PFNMASK	0x3fffffc0
+#define TLBLO_PFNSHIFT	6
+#define	TLBLO_D		0x00000004	/* writeable */
+#define	TLBLO_V		0x00000002	/* valid bit */
+#define	TLBLO_G		0x00000001	/* global access bit */
+#define TLBLO_CMASK	0x00000038	/* cache algorithm mask */
+#define TLBLO_CSHIFT	3
+
+#define TLBLO_UNCACHED		(CFG_C_UNCACHED<<TLBLO_CSHIFT)
+#define TLBLO_NONCOHERENT	(CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCL	(CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTXCLW	(CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
+#define TLBLO_COHERENTUPD	(CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
+
+#define	TLBINX_PROBE	0x80000000
+#define	TLBINX_INXMASK	0x0000003f
+
+#define	TLBRAND_RANDMASK	0x0000003f
+
+#define	TLBCTXT_BASEMASK	0xff800000
+#define	TLBCTXT_BASESHIFT	23
+
+#define	TLBCTXT_VPN2MASK	0x007ffff0
+#define	TLBCTXT_VPN2SHIFT	4
+
+#define TLBPGMASK_MASK		0x01ffe000
+#endif
+
+#if defined(CPU_R3000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define	SR_BEV		0x00400000	/* use boot exception vectors */
+
+/* Cache control bits */
+#define	SR_TS		0x00200000	/* TLB shutdown */
+#define	SR_PE		0x00100000	/* cache parity error */
+#define	SR_CM		0x00080000	/* cache miss */
+#define	SR_PZ		0x00040000	/* cache parity zero */
+#define	SR_SWC		0x00020000	/* swap cache */
+#define	SR_ISC		0x00010000	/* Isolate data cache */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
+#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
+#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
+#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
+#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
+#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
+#endif
+
+#if defined(CPU_R4000)
+#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
+#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
+#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
+#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
+#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */
+
+#define SR_RP		0x08000000      /* Reduced power operation */
+#define SR_FR		0x04000000	/* Additional floating point registers */
+#define SR_RE		0x02000000	/* Reverse endian in user mode */
+
+#define SR_BEV		0x00400000	/* Use boot exception vectors */
+#define SR_TS		0x00200000	/* TLB shutdown */
+#define SR_SR		0x00100000	/* Soft reset */
+#define SR_CH		0x00040000	/* Cache hit */
+#define SR_CE		0x00020000	/* Use cache ECC  */
+#define SR_DE		0x00010000	/* Disable cache exceptions */
+
+/*
+**	status register interrupt masks and bits
+*/
+
+#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
+#define	SR_IMASK8	0x00000000	/* mask level 8 */
+#define	SR_IMASK7	0x00008000	/* mask level 7 */
+#define	SR_IMASK6	0x0000c000	/* mask level 6 */
+#define	SR_IMASK5	0x0000e000	/* mask level 5 */
+#define	SR_IMASK4	0x0000f000	/* mask level 4 */
+#define	SR_IMASK3	0x0000f800	/* mask level 3 */
+#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
+#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
+#define	SR_IMASK0	0x0000ff00	/* mask level 0 */
+
+#define	SR_IMASKSHIFT	8
+
+#define	SR_IBIT8	0x00008000	/* bit level 8 */
+#define	SR_IBIT7	0x00004000	/* bit level 7 */
+#define	SR_IBIT6	0x00002000	/* bit level 6 */
+#define	SR_IBIT5	0x00001000	/* bit level 5 */
+#define	SR_IBIT4	0x00000800	/* bit level 4 */
+#define	SR_IBIT3	0x00000400	/* bit level 3 */
+#define	SR_IBIT2	0x00000200	/* bit level 2 */
+#define	SR_IBIT1	0x00000100	/* bit level 1 */
+
+#define SR_KSMASK	0x00000018	/* Kernel mode mask */
+#define SR_KSUSER	0x00000010	/* User mode */
+#define SR_KSSUPER	0x00000008	/* Supervisor mode */
+#define SR_KSKERNEL	0x00000000	/* Kernel mode */
+#define SR_ERL		0x00000004	/* Error level */
+#define SR_EXL		0x00000002	/* Exception level */
+#define SR_IE		0x00000001	/* Interrupts enabled */
+#endif
+
+
+
+/*
+ * Cause Register
+ */
+#define	CAUSE_BD	0x80000000	/* Branch delay slot */
+#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
+#define	CAUSE_CESHIFT	28
+
+
+#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
+#define	CAUSE_IPSHIFT	8
+
+#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
+#define	CAUSE_EXCSHIFT	2
+
+#ifndef XDS
+/*
+**  Coprocessor 0 registers
+*/
+#define	C0_INX		$0		/* tlb index */
+#define	C0_RAND		$1		/* tlb random */
+#if defined(CPU_R3000)
+#define	C0_TLBLO	$2		/* tlb entry low */
+#endif
+#if defined(CPU_R4000)
+#define	C0_TLBLO0	$2		/* tlb entry low 0 */
+#define	C0_TLBLO1	$3		/* tlb entry low 1 */
+#endif
+
+#define	C0_CTXT		$4		/* tlb context */
+
+#if defined(CPU_R4000)
+#define C0_PAGEMASK	$5		/* tlb page mask */
+#define C0_WIRED	$6		/* number of wired tlb entries */
+#endif
+
+#define	C0_BADVADDR	$8		/* bad virtual address */
+
+#if defined(CPU_R4000)
+#define C0_COUNT	$9		/* cycle count */
+#endif
+
+#define	C0_TLBHI	$10		/* tlb entry hi */
+
+#if defined(CPU_R4000)
+#define C0_COMPARE	$11		/* cyccle count comparator  */
+#endif
+
+#define	C0_SR		$12		/* status register */
+#define	C0_CAUSE	$13		/* exception cause */
+#define	C0_EPC		$14		/* exception pc */
+#define	C0_PRID		$15		/* revision identifier */
+
+#if defined(CPU_R3000)
+#define C0_CONFIG   $3     /* configuration register R3081*/
+#endif
+
+#if defined(CPU_R4000)
+#define C0_CONFIG	$16		/* configuration register */
+#define C0_LLADDR	$17		/* linked load address */
+#define C0_WATCHLO	$18		/* watchpoint trap register */
+#define C0_WATCHHI	$19		/* watchpoint trap register */
+#define C0_XCTXT    $20     /* extended tlb context */
+#define C0_ECC		$26		/* secondary cache ECC control */
+#define C0_CACHEERR	$27		/* cache error status */
+#define C0_TAGLO	$28		/* cache tag lo */
+#define C0_TAGHI	$29		/* cache tag hi */
+#define C0_ERRPC	$30		/* cache error pc */
+#endif
+
+#endif XDS
+
+#ifdef R4650
+#define IWATCH $18
+#define DWATCH $19
+#define IBASE  $0
+#define IBOUND $1
+#define DBASE  $2
+#define DBOUND $3
+#define CALG	$17
+#endif
+
+#endif /* _IDTCPU_H__ */
+
diff --git a/c/src/exec/score/cpu/mips64orion/idtmon.h b/c/src/exec/score/cpu/mips64orion/idtmon.h
new file mode 100644
index 0000000000..1cddbcb2a3
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/idtmon.h
@@ -0,0 +1,170 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+**	idtmon.h - General header file for the IDT Prom Monitor
+**
+**	Copyright 1989  Integrated Device Technology, Inc.
+**	All Rights Reserved.
+**
+**	June 1989 - D.Cahoon
+*/
+#ifndef __IDTMON_H__
+#define __IDTMON_H__
+
+/*
+** P_STACKSIZE is the size of the Prom Stack. 
+** the prom stack grows downward 
+*/
+#define	P_STACKSIZE	0x2000   /* sets stack size to 8k */
+
+/*
+** M_BUSWIDTH
+** Memory bus width (including bank interleaving) in bytes
+** used when doing memory sizing to prevent bus capacitance
+** reporting ghost memory locations
+*/
+#if defined(CPU_R3000)
+#define M_BUSWIDTH	8	/* 32bit memory bank interleaved */
+#endif
+#if defined(CPU_R4000)
+#define M_BUSWIDTH	16	/* 64 bit memory bank interleaved */
+#endif
+
+/*
+** this is the default value for the number of bytes to add in calculating
+** the checksums in the checksum command
+*/
+#define CHK_SUM_CNT	0x20000	     /* number of bytes to calc chksum for */
+
+/*
+** Monitor modes
+*/
+#define	MODE_MONITOR	5	/* IDT Prom Monitor is executing */
+#define	MODE_USER	0xa	/* USER is executing */
+
+/*
+** memory reference widths
+*/
+#define	SW_BYTE		1
+#define	SW_HALFWORD	2
+#define	SW_WORD		4
+#define SW_TRIBYTEL	12
+#define SW_TRIBYTER	20
+
+#ifdef CPU_R4000
+/*
+** definitions for select_cache call
+*/
+#define DCACHE		0
+#define ICACHE		1
+#define SCACHE		2
+
+#endif
+
+#if defined (CLANGUAGE) || defined(_LANGUAGE_C)
+typedef struct {
+	unsigned int	mem_size;
+	unsigned int	icache_size;
+	unsigned int	dcache_size;
+#ifdef CPU_R4000
+    unsigned int    scache_size;
+#endif
+
+	} mem_config;
+
+#endif CLANGUAGE || defined(_LANGUAGE_C)
+
+/*
+** general equates for diagnostics and boolean functions
+*/
+#define	PASS			0
+#define	FAIL			1
+
+#ifndef	TRUE
+#define	TRUE			1
+#endif	TRUE
+#ifndef	NULL
+#define	NULL			0
+#endif	NULL
+
+#ifndef	FALSE
+#define	FALSE			0
+#endif	FALSE
+
+
+/*
+**	portablility equates
+*/
+
+#ifndef	BOOL
+#define BOOL	unsigned int
+#endif	BOOL
+
+#ifndef GLOBAL
+#define GLOBAL	/**/
+#endif  GLOBAL
+
+#ifndef MLOCAL
+#define MLOCAL	static
+#endif  MLOCAL
+
+
+#ifdef XDS
+#define CONST const
+#else
+#define CONST
+#endif XDS 
+
+#define u_char	unsigned char
+#define u_short unsigned short
+#define u_int	unsigned int
+/*
+** assembly instructions for compatability between xds and mips
+*/
+#ifndef XDS
+#define sllv sll
+#define srlv srl
+#endif XDS
+/*
+**	debugger macros for assembly language routines. Allows the 
+**	programmer to set up the necessary stack frame info
+**	required by debuggers to do stack traces.
+*/
+
+#ifndef XDS 
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	name;				\
+	.ent	name;				\
+name:;						\
+	.frame	frm_reg,offset,ret_reg
+#define ENDFRAME(name) 				\
+	.end name
+#else
+#define	FRAME(name,frm_reg,offset,ret_reg)	\
+	.globl	_##name;\
+_##name:
+#define ENDFRAME(name)
+#endif  XDS
+#endif /* __IDTMON_H__ */
diff --git a/c/src/exec/score/cpu/mips64orion/iregdef.h b/c/src/exec/score/cpu/mips64orion/iregdef.h
new file mode 100644
index 0000000000..e7a4ba5ed1
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/iregdef.h
@@ -0,0 +1,324 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*
+**	iregdef.h - IDT R3000 register structure header file
+**
+**	Copyright 1989 Integrated Device Technology, Inc
+**	All Rights Reserved
+**
+*/
+#ifndef __IREGDEF_H__
+#define __IREGDEF_H__
+
+/*
+ * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
+ *         added Register definition for XContext reg.
+ *         Look towards end of this file.
+ */
+/*
+** register names 
+*/
+#define r0	$0
+#define r1	$1
+#define r2	$2
+#define r3	$3
+#define r4	$4
+#define r5	$5
+#define r6	$6
+#define r7	$7
+#define r8	$8
+#define r9	$9
+#define r10	$10
+#define r11	$11
+#define r12	$12
+#define r13	$13
+
+#define r14	$14
+#define r15	$15
+#define r16	$16
+#define r17	$17
+#define r18	$18
+#define r19	$19
+#define r20	$20
+#define r21	$21
+#define r22	$22
+#define r23	$23
+#define r24	$24
+#define r25	$25
+#define r26	$26
+#define r27	$27
+#define r28	$28
+#define r29	$29
+#define r30	$30
+#define r31	$31
+
+#define fp0	$f0
+#define fp1	$f1
+#define fp2	$f2
+#define fp3	$f3
+#define fp4	$f4
+#define fp5	$f5
+#define fp6	$f6
+#define fp7	$f7
+#define fp8	$f8
+#define fp9	$f9
+#define fp10	$f10
+#define fp11	$f11
+#define fp12	$f12
+#define fp13	$f13
+#define fp14	$f14
+#define fp15	$f15
+#define fp16	$f16
+#define fp17	$f17
+#define fp18	$f18
+#define fp19	$f19
+#define fp20	$f20
+#define fp21	$f21
+#define fp22	$f22
+#define fp23	$f23
+#define fp24	$f24
+#define fp25	$f25
+#define fp26	$f26
+#define fp27	$f27
+#define fp28	$f28
+#define fp29	$f29
+#define fp30	$f30
+#define fp31	$f31
+
+#define fcr0	$0
+#define fcr30	$30
+#define fcr31	$31
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers a0-a3 */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved  t0-t9 */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16	/* callee saved s0-s8 */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel usage */
+#define k1	$27	/* kernel usage */
+#define gp	$28	/* sdata pointer */
+#define sp	$29	/* stack pointer */
+#define s8	$30	/* yet another saved reg for the callee */
+#define fp	$30	/* frame pointer - this is being phased out by MIPS */
+#define ra	$31	/* return address */
+
+
+/*
+** relative position of registers in save reg area
+*/
+#define	R_R0		0
+#define	R_R1		1
+#define	R_R2		2
+#define	R_R3		3
+#define	R_R4		4
+#define	R_R5		5
+#define	R_R6		6
+#define	R_R7		7
+#define	R_R8		8
+#define	R_R9		9
+#define	R_R10		10
+#define	R_R11		11
+#define	R_R12		12
+#define	R_R13		13
+#define	R_R14		14
+#define	R_R15		15
+#define	R_R16		16
+#define	R_R17		17
+#define	R_R18		18
+#define	R_R19		19
+#define	R_R20		20
+#define	R_R21		21
+#define	R_R22		22
+#define	R_R23		23
+#define	R_R24		24
+#define	R_R25		25
+#define	R_R26		26
+#define	R_R27		27
+#define	R_R28		28
+#define	R_R29		29
+#define	R_R30		30
+#define	R_R31		31
+#define	R_F0		32
+#define	R_F1		33
+#define	R_F2		34
+#define	R_F3		35
+#define	R_F4		36
+#define	R_F5		37
+#define	R_F6		38
+#define	R_F7		39
+#define	R_F8		40
+#define	R_F9		41
+#define	R_F10		42
+#define	R_F11		43
+#define	R_F12		44
+#define	R_F13		45
+#define	R_F14		46
+#define	R_F15		47
+#define	R_F16		48
+#define	R_F17		49
+#define	R_F18		50
+#define	R_F19		51
+#define	R_F20		52
+#define	R_F21		53
+#define	R_F22		54
+#define	R_F23		55
+#define	R_F24		56
+#define	R_F25		57
+#define	R_F26		58
+#define	R_F27		59
+#define	R_F28		60
+#define	R_F29		61
+#define	R_F30		62
+#define	R_F31		63
+#define NCLIENTREGS	64
+#define	R_EPC		64
+#define	R_MDHI		65
+#define	R_MDLO		66
+#define	R_SR		67
+#define	R_CAUSE		68
+#define	R_TLBHI		69
+#if defined(CPU_R3000)
+#define	R_TLBLO		70
+#endif
+#if defined(CPU_R4000)
+#define	R_TLBLO0	70
+#endif
+#define	R_BADVADDR	71
+#define	R_INX		72
+#define	R_RAND		73
+#define	R_CTXT		74
+#define	R_EXCTYPE	75
+#define R_MODE		76
+#define	R_PRID		77
+#define R_FCSR		78
+#define R_FEIR		79
+#if defined(CPU_R3000)
+#define NREGS		80
+#endif
+#if defined(CPU_R4000)
+#define	R_TLBLO1	80
+#define R_PAGEMASK	81
+#define R_WIRED		82
+#define R_COUNT		83
+#define R_COMPARE	84
+#define R_CONFIG	85
+#define R_LLADDR	86
+#define R_WATCHLO	87
+#define R_WATCHHI	88
+#define R_ECC		89
+#define R_CACHEERR	90
+#define R_TAGLO		91
+#define R_TAGHI		92
+#define R_ERRPC		93
+#define R_XCTXT     94  /* Ketan added from SIM64bit */
+
+#define	NREGS		95
+#endif
+
+/*
+** For those who like to think in terms of the compiler names for the regs
+*/
+#define	R_ZERO		R_R0
+#define	R_AT		R_R1
+#define	R_V0		R_R2
+#define	R_V1		R_R3
+#define	R_A0		R_R4
+#define	R_A1		R_R5
+#define	R_A2		R_R6
+#define	R_A3		R_R7
+#define	R_T0		R_R8
+#define	R_T1		R_R9
+#define	R_T2		R_R10
+#define	R_T3		R_R11
+#define	R_T4		R_R12
+#define	R_T5		R_R13
+#define	R_T6		R_R14
+#define	R_T7		R_R15
+#define	R_S0		R_R16
+#define	R_S1		R_R17
+#define	R_S2		R_R18
+#define	R_S3		R_R19
+#define	R_S4		R_R20
+#define	R_S5		R_R21
+#define	R_S6		R_R22
+#define	R_S7		R_R23
+#define	R_T8		R_R24
+#define	R_T9		R_R25
+#define	R_K0		R_R26
+#define	R_K1		R_R27
+#define	R_GP		R_R28
+#define	R_SP		R_R29
+#define	R_FP		R_R30
+#define	R_RA		R_R31
+
+/* Ketan added the following */
+#ifdef CPU_R3000
+#define sreg	sw
+#define lreg	lw
+#define rmfc0	mfc0
+#define rmtc0	mtc0
+#define R_SZ	4
+#endif CPU_R3000
+
+#ifdef CPU_R4000
+#if __mips < 3
+#define sreg	sw
+#define lreg	lw
+#define rmfc0	mfc0
+#define rmtc0	mtc0
+#define R_SZ	4
+#else
+#define sreg	sd
+#define lreg	ld
+#define rmfc0	dmfc0
+#define rmtc0	dmtc0
+#define R_SZ	8
+#endif
+#endif CPU_R4000
+/* Ketan till here */
+
+#endif /* __IREGDEF_H__ */
+
diff --git a/c/src/exec/score/cpu/mips64orion/mips64orion.h b/c/src/exec/score/cpu/mips64orion/mips64orion.h
new file mode 100644
index 0000000000..20c81af95a
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/mips64orion.h
@@ -0,0 +1,97 @@
+/*  mips64orion.h
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  mips64orion.h,v 1.3 1995/09/26 19:25:40 joel Exp
+ *
+ */
+/* @(#)mips64orion.h       08/29/96     1.3 */
+
+#ifndef _INCLUDE_MIPS64ORION_h
+#define _INCLUDE_MIPS64ORION_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  The following define the CPU Family and Model within the family
+ *
+ *  NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
+ *        with the name of the appropriate macro for this target CPU.
+ */
+ 
+#ifdef mips64orion
+#undef mips64orion
+#endif
+#define mips64orion
+
+#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
+#undef REPLACE_THIS_WITH_THE_CPU_MODEL
+#endif
+#define REPLACE_THIS_WITH_THE_CPU_MODEL
+ 
+#ifdef REPLACE_THIS_WITH_THE_BSP
+#undef REPLACE_THIS_WITH_THE_BSP
+#endif
+#define REPLACE_THIS_WITH_THE_BSP
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the "no cpu"
+ *  family when executing in protected mode.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
+ */
+ 
+#if defined(R4650)
+ 
+#define CPU_MODEL_NAME  "R4650"
+#define MIPS64ORION_HAS_FPU     1
+ 
+#elif defined(R4600)
+ 
+#define CPU_MODEL_NAME  "R4600"
+#define MIPS64ORION_HAS_FPU     1
+
+#else
+ 
+#error "Unsupported CPU Model"
+ 
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "MIPS R46xxx"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! _INCLUDE_MIPS64ORION_h */
+/* end of include file */
diff --git a/c/src/exec/score/cpu/mips64orion/mipstypes.h b/c/src/exec/score/cpu/mips64orion/mipstypes.h
new file mode 100644
index 0000000000..2c6efb4867
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/mipstypes.h
@@ -0,0 +1,73 @@
+/*  mipstypes.h
+ *
+ *  This include file contains type definitions pertaining to the IDT 4650
+ *  processor family.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  mipstypes.h,v 1.3 1995/05/31 14:57:15 joel Exp
+ */
+/* @(#)mipstypes.h       08/20/96     1.4 */
+
+#ifndef __MIPS_TYPES_h
+#define __MIPS_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char      unsigned8;  /* unsigned 8-bit  integer */
+typedef unsigned short     unsigned16; /* unsigned 16-bit integer */
+typedef unsigned int       unsigned32; /* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
+
+typedef unsigned16     Priority_Bit_map_control;
+
+typedef signed char      signed8;      /* 8-bit  signed integer */
+typedef signed short     signed16;     /* 16-bit signed integer */
+typedef signed int       signed32;     /* 32-bit signed integer */
+typedef signed long long signed64;     /* 64 bit signed integer */
+
+typedef unsigned32 boolean;     /* Boolean value   */
+
+typedef float          single_precision;     /* single precision float */
+typedef double         double_precision;     /* double precision float */
+
+typedef void mips_isr;
+typedef void ( *mips_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+/* end of include file */
diff --git a/c/src/exec/score/cpu/mips64orion/rtems.c b/c/src/exec/score/cpu/mips64orion/rtems.c
new file mode 100644
index 0000000000..3128ef3379
--- /dev/null
+++ b/c/src/exec/score/cpu/mips64orion/rtems.c
@@ -0,0 +1,49 @@
+/*  rtems.c  ===> rtems.S or rtems.s
+ *
+ *  This file contains the single entry point code for
+ *  the XXX implementation of RTEMS.
+ *
+ *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  rtems.c,v 1.4 1995/09/26 19:25:41 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)rtems.c 03/15/96     1.1\n";
+#endif
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" rtems file.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+/* #include "asm.h> */
+
+/*
+ *  RTEMS
+ *
+ *  This routine jumps to the directive indicated in the
+ *  CPU defined register.  This routine is used when RTEMS is
+ *  linked by itself and placed in ROM.  This routine is the
+ *  first address in the ROM space for RTEMS.  The user "calls"
+ *  this address with the directive arguments in the normal place.
+ *  This routine then jumps indirectly to the correct directive
+ *  preserving the arguments.  The directive should not realize
+ *  it has been "wrapped" in this way.  The table "_Entry_points"
+ *  is used to look up the directive.
+ */
+
+void RTEMS()
+{
+}
+
diff --git a/c/src/lib/libbsp/mips/p4000/README b/c/src/lib/libbsp/mips/p4000/README
new file mode 100644
index 0000000000..31152f15ec
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/README
@@ -0,0 +1,47 @@
+#
+#  README,v 1.2 1995/05/31 16:56:03 joel Exp
+#
+# @(#)README        08/20/96     1.2
+#
+
+BSP NAME:           p4000
+BOARD:              Algorithmics P4000 SBC
+BUS:                N/A
+CPU FAMILY:         mips
+CPU:                IDT 4650 
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+
+DEBUG MONITOR:      IDT/SIM
+
+PERIPHERALS
+===========
+TIMERS:             4650 internal
+  RESOLUTION:         half of internal clock frequency
+SERIAL PORTS:       IDT/SIM controlled
+REAL-TIME CLOCK:    none
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       4650 internal
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A 
+TIMER DRIVER:       4650 internal
+TTY DRIVER:         uses IDT/SIM
+
+STDIO
+=====
+PORT:               Console port 0
+ELECTRICAL:         RS-232
+BAUD:               9600
+BITS PER CHARACTER: 8
+PARITY:             None
+STOP BITS:          1
+
+NOTES
+=====
+
diff --git a/c/src/lib/libbsp/mips/p4000/console/console.c b/c/src/lib/libbsp/mips/p4000/console/console.c
new file mode 100644
index 0000000000..cc52dc3c7c
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/console/console.c
@@ -0,0 +1,270 @@
+/*
+ *  This file contains the IDT 4650 console IO package.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  console.c,v 1.4 1995/12/05 19:23:02 joel Exp
+ */
+
+
+#ifndef lint
+static char _sccsid[] = "@(#)console.c 08/20/96     1.6\n";
+#endif
+
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <ctype.h>
+
+char idtsim_getchar( void );
+void idtsim_putchar( char c );
+void mips_leddisplay( char a, char b, char c, char d );
+
+
+/*  console_initialize
+ *
+ *  This routine initializes the console IO driver.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ */
+
+rtems_device_driver console_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  minor,
+  void                      *arg
+)
+{
+  rtems_status_code status;
+ 
+  status = rtems_io_register_name(
+    "/dev/console",
+    major,
+    (rtems_device_minor_number) 0
+  );
+ 
+  if (status != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred(status);
+ 
+  return RTEMS_SUCCESSFUL;
+}
+
+
+/*  is_character_ready
+ *
+ *  This routine returns TRUE if a character is available.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ */
+
+rtems_boolean is_character_ready(
+  char *ch
+)
+{
+  *ch = '\0';   /* return NULL for no particular reason */
+  return(TRUE);
+}
+
+/*  inbyte
+ *
+ *  This routine reads a character from the SOURCE.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    character read from SOURCE
+ */
+
+char inbyte( void )
+{
+  /*
+   *  If polling, wait until a character is available.
+   */
+
+   return idtsim_getchar();
+}
+
+/*  outbyte
+ *
+ *  This routine transmits a character out the SOURCE.  It may support
+ *  XON/XOFF flow control.
+ *
+ *  Input parameters:
+ *    ch  - character to be transmitted
+ *
+ *  Output parameters:  NONE
+ */
+
+void outbyte(
+  char ch
+)
+{
+#define NUM_LEDS 4
+   static unsigned int cur_led = 0;
+   static unsigned char led_chars[NUM_LEDS];
+
+  /*
+   *  If polling, wait for the transmitter to be ready.
+   *  Check for flow control requests and process.
+   *  Then output the character.
+   */
+
+  idtsim_putchar( ch );
+
+  /* print out first four alpha numeric characters in a line */
+  if ( ch == '\n' )
+  {
+    mips_leddisplay( led_chars[0], led_chars[1], led_chars[2], led_chars[3] );
+    cur_led = 0;
+  }
+  else if ( isalnum( ch ) && cur_led < NUM_LEDS )
+  {
+    led_chars[cur_led++] = ch;
+  }
+
+}
+
+
+static int console_fd = -1;
+
+/*
+ *  Open entry point
+ */
+
+rtems_device_driver console_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+#if 0
+  int console_fd = open("tty0", 2); /* open for read/write */
+#endif
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  Close entry point
+ */
+
+rtems_device_driver console_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+#if 0
+  if ( console_fd )
+    close( console_fd );
+#endif
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ * read bytes from the serial port. We only have stdin.
+ */
+
+rtems_device_driver console_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+  int maximum;
+  int count = 0;
+ 
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    buffer[ count ] = inbyte();
+    if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
+      buffer[ count++ ]  = '\n';
+      buffer[ count ]  = 0;
+      break;
+    }
+  }
+
+  rw_args->bytes_moved = count;
+  return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
+}
+
+/*
+ * write bytes to the serial port. Stdout and stderr are the same. 
+ */
+
+rtems_device_driver console_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  int count;
+  int maximum;
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    if ( buffer[ count ] == '\n') {
+      outbyte('\r');
+    }
+    outbyte( buffer[ count ] );
+  }
+
+  rw_args->bytes_moved = maximum;
+  return 0;
+}
+
+/*
+ *  IO Control entry point
+ */
+
+rtems_device_driver console_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/mips/p4000/console/led.S b/c/src/lib/libbsp/mips/p4000/console/led.S
new file mode 100644
index 0000000000..b9b7b7e294
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/console/led.S
@@ -0,0 +1,20 @@
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtmon.h>
+#include <rtems/score/idtcpu.h>
+
+
+FRAME(mips_leddisplay,sp,0,ra)
+	j ra
+	nop
+ENDFRAME(mips_leddisplay)
+
+FRAME(sbddisplay,sp,0,ra)
+	j	ra
+ENDFRAME(sbddisplay)
+
+
+FRAME(sbdblank,sp,0,ra)
+	j	ra
+ENDFRAME(sbdblank)
+
diff --git a/c/src/lib/libbsp/mips/p4000/include/bsp.h b/c/src/lib/libbsp/mips/p4000/include/bsp.h
new file mode 100644
index 0000000000..1a9f6a5653
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/include/bsp.h
@@ -0,0 +1,120 @@
+/*  bsp.h
+ *
+ *  This include file contains all board IO definitions.
+ *
+ *  XXX : put yours in here
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  bsp.h,v 1.4 1995/09/11 19:29:04 joel Exp
+ */
+/* @(#)bsp.h       03/15/96     1.1 */
+
+#ifndef __NO_BSP_h
+#define __NO_BSP_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems.h>
+#include <console.h>
+#include <clockdrv.h>
+
+extern void WriteDisplay( char * string );
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
+
+#define Cause_tm27_intr()
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+
+extern unsigned32 mips_get_timer( void );
+
+#define CPU_CLOCK_RATE_MHZ     (50)
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+#define delay( microseconds ) \
+  { \
+     unsigned32 _end_clock = mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
+     _end_clock %= 0x100000000;  /* make sure result is 32 bits */ \
+     \
+     /* handle timer overflow, if necessary */ \
+     while ( _end_clock < mips_get_timer() );  \
+     \
+     while ( _end_clock > mips_get_timer() ); \
+  }
+
+/* Constants */
+
+#define RAM_START 0
+#define RAM_END   0x100000
+
+/* miscellaneous stuff assumed to exist */
+
+extern rtems_configuration_table BSP_Configuration;
+
+/*
+ *  Device Driver Table Entries
+ */
+
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+
+/*
+ * How many libio files we want
+ */
+
+#define BSP_LIBIO_MAX_FDS       20
+
+/* functions */
+
+void bsp_cleanup( void );
+
+mips_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/mips/p4000/include/coverhd.h b/c/src/lib/libbsp/mips/p4000/include/coverhd.h
new file mode 100644
index 0000000000..716faef06b
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/include/coverhd.h
@@ -0,0 +1,116 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C.  These are used in the
+ *  Timing Test Suite to ignore the overhead required to pass arguments
+ *  to directives.  On some CPUs and/or target boards, this overhead
+ *  is significant and makes it difficult to distinguish internal
+ *  RTEMS execution time from that used to call the directive.
+ *  This file should be updated after running the C overhead timing
+ *  test.  Once this update has been performed, the RTEMS Time Test
+ *  Suite should be rebuilt to account for these overhead times in the
+ *  timing results.
+ *
+ *  NOTE:  If these are all zero, then the times reported include all
+ *         all calling overhead including passing of arguments.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  coverhd.h,v 1.2 1995/05/31 16:56:15 joel Exp
+ */
+/* @(#)coverhd.h       04/08/96     1.3 */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      5
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        4
+#define CALLING_OVERHEAD_TASK_CREATE               6
+#define CALLING_OVERHEAD_TASK_IDENT                4
+#define CALLING_OVERHEAD_TASK_START                5
+#define CALLING_OVERHEAD_TASK_RESTART              4
+#define CALLING_OVERHEAD_TASK_DELETE               4
+#define CALLING_OVERHEAD_TASK_SUSPEND              4
+#define CALLING_OVERHEAD_TASK_RESUME               4
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         5
+#define CALLING_OVERHEAD_TASK_MODE                 4
+#define CALLING_OVERHEAD_TASK_GET_NOTE             5
+#define CALLING_OVERHEAD_TASK_SET_NOTE             5
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            9
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           4
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           5
+#define CALLING_OVERHEAD_CLOCK_GET                 9
+#define CALLING_OVERHEAD_CLOCK_SET                 8
+#define CALLING_OVERHEAD_CLOCK_TICK                3
+
+#define CALLING_OVERHEAD_TIMER_CREATE              4
+#define CALLING_OVERHEAD_TIMER_IDENT               4
+#define CALLING_OVERHEAD_TIMER_DELETE              4
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          6
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           10
+#define CALLING_OVERHEAD_TIMER_RESET               4
+#define CALLING_OVERHEAD_TIMER_CANCEL              4
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          5
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           4
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          4
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          5
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       4
+
+#define CALLING_OVERHEAD_EVENT_SEND                4
+#define CALLING_OVERHEAD_EVENT_RECEIVE             5
+#define CALLING_OVERHEAD_SIGNAL_CATCH              5
+#define CALLING_OVERHEAD_SIGNAL_SEND               4
+#define CALLING_OVERHEAD_PARTITION_CREATE          6
+#define CALLING_OVERHEAD_PARTITION_IDENT           4
+#define CALLING_OVERHEAD_PARTITION_DELETE          4
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      4
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   4
+#define CALLING_OVERHEAD_REGION_CREATE             6
+#define CALLING_OVERHEAD_REGION_IDENT              4
+#define CALLING_OVERHEAD_REGION_DELETE             4
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        5
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     4
+#define CALLING_OVERHEAD_PORT_CREATE               6
+#define CALLING_OVERHEAD_PORT_IDENT                4
+#define CALLING_OVERHEAD_PORT_DELETE               4
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             5
+#define CALLING_OVERHEAD_IO_OPEN                   5
+#define CALLING_OVERHEAD_IO_CLOSE                  5
+#define CALLING_OVERHEAD_IO_READ                   5
+#define CALLING_OVERHEAD_IO_WRITE                  5
+#define CALLING_OVERHEAD_IO_CONTROL                5
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     4
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S b/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S
new file mode 100644
index 0000000000..fb8f28edbc
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S
@@ -0,0 +1,58 @@
+#include "iregdef.h"
+#include "idtcpu.h"
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+        .globl  name;                           \
+        .ent    name;                           \
+name:;                                          \
+        .frame  frm_reg,offset,ret_reg
+
+#define ENDFRAME(name)                          \
+        .end name
+
+#define PROM_LINK(name,entry)           \
+        .globl  name;                   \
+        .ent    name;                   \
+name:   la      $2,+entry;              \
+        j       $2;                     \
+        .end name
+
+#define	PROM_ENTRY(x)	(0xbfc00000+((x)*8))
+
+#define PROM_RESET	PROM_ENTRY(0)
+#define PROM_NOT_IMP	PROM_ENTRY(1)
+#define PROM_RESTART	PROM_ENTRY(2)
+#define PROM_REINIT	PROM_ENTRY(3)
+#define	PROM_GETCHAR	PROM_ENTRY(11)
+#define	PROM_PUTCHAR	PROM_ENTRY(12)
+#define	PROM_SHOWCHAR	PROM_ENTRY(13)
+#define	PROM_PRINTF	PROM_ENTRY(16)
+#define	PROM_RETURN	PROM_ENTRY(17)
+
+#define	PROM_RGETS	PROM_ENTRY(25)
+#define PROM_FLUSHCACHE	PROM_ENTRY(28)
+#define PROM_CLEARCACHE	PROM_ENTRY(29)
+#define PROM_SETJMP	PROM_ENTRY(30)
+#define PROM_LONGJMP	PROM_ENTRY(31)
+
+	.text
+
+PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
+PROM_LINK(idtsim_getchar, PROM_GETCHAR)
+PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
+PROM_LINK(idtsim__exit, PROM_RETURN)
+PROM_LINK(idtsim_reinit, PROM_REINIT)
+PROM_LINK(idtsim_restart, PROM_RESTART)
+PROM_LINK(idtsim_reset, PROM_RESET)
+PROM_LINK(idtsim_promexit, PROM_RETURN)
+PROM_LINK(idtsim_setjmp, PROM_SETJMP)
+PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
+
+FRAME(idtsim_init_sbrk,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_sbrk)
+
+FRAME(idtsim_init_file,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_file)
+
diff --git a/c/src/lib/libbsp/mips/p4000/start/start.S b/c/src/lib/libbsp/mips/p4000/start/start.S
new file mode 100644
index 0000000000..bbedf0c5dd
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/start/start.S
@@ -0,0 +1,298 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*************************************************************************
+**
+** Copyright 1991-95 Integrated Device Technology, Inc.
+**	All Rights Reserved
+**
+** idt_csu.S -- IDT stand alone startup code
+**
+**************************************************************************/
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+
+.extern _fbss,4		  /* this is defined by the linker */
+.extern end,4		  /* this is defined by the linker */
+
+.lcomm sim_mem_cfg_struct,12
+
+	.text
+
+
+#define TMP_STKSIZE  1024 
+
+/**************************************************************************
+**
+**  start - Typicl standalone start up code required for R3000/R4000
+**
+**
+**	1)  Initialize the STATUS Register
+**		a) Clear parity error bit
+**		b) Set co_processor 1 usable bit ON
+**		c) Clear all IntMask Enables
+**		d) Set kernel/disabled mode
+**	2)  Initialize Cause Register
+**		a)  clear software interrupt bits       
+**	3)  Determine FPU installed or not
+**		if not, clear CoProcessor 1 usable bit
+**	4)  Clear bss area
+**	5)  MUST allocate temporary stack until memory size determined
+**	    It MUST be uncached to prevent overwriting when caches are cleared
+**	6)  Install exception handlers
+**	7)  Determine memory and cache sizes
+**	8)  Establish permanent stack (cached or uncached as defined by bss)
+**	9)  Flush Instruction and Data caches
+** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
+** 	11)  Execute initialization code if the IDT/c library is to be used
+** 
+** 	12)  Jump to user's "main()"
+** 	13)  Jump to promexit
+**
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	This is used to mark code specific to R3xxx or R4xxx processors.
+**	IDT/C 6.x defines __mips to be the ISA level for which we're 
+**	generating code. This is used to make sure the stack etc. is 
+**	double word aligned, when using -mips3 (default) or -mips2, 
+**	when compiling with IDT/C6.x
+**
+***************************************************************************/
+
+FRAME(start,sp,0,ra)
+
+	.set	noreorder
+#ifdef _R3000
+	li	v0,SR_PE|SR_CU1        /* reset parity error and set */
+					/* cp1 usable */
+#endif
+#ifdef _R4000
+#if __mips==3 || defined(R4650)
+	li	v0,SR_CU1|SR_DE|SR_FR 	/* initally clear ERL, enable FPA 64bit regs*/
+	                                /* 4650: Need fr to be set anyway */
+#else
+	li	v0,SR_CU1|SR_DE 	/* initally clear ERL, enable FPA 32bit regs*/
+#endif mips3
+#endif
+
+	mtc0	v0,C0_SR		/* clr IntMsks/ kernel/disabled mode */
+	nop
+	mtc0	zero,C0_CAUSE		/* clear software interrupts */
+	nop
+
+#ifdef _R4000
+	li	v0,CFG_C_NONCOHERENT	# initialise default cache mode
+	mtc0	v0,C0_CONFIG
+#endif
+
+/*
+**	check to see if an fpu is really plugged in 
+*/
+	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
+	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	zero,fp1		/* try to write zero in fp	*/
+	mfc1	t0,fp0
+	mfc1	t1,fp1
+	nop
+	bne	t0,t3,1f		/* branch if no match  */
+	nop
+	bne	t1,zero,1f		/* double check for positive id   */
+	nop
+	/* We have a FPU. clear fcsr */
+	ctc1	zero, fcr31
+	j	2f			/* status register already correct  */
+	nop
+1:
+#ifdef _R3000
+	li	v0, SR_PE		/* reset parity error/NO cp1 usable */
+#endif
+
+#ifdef _R4000
+        li      v0,SR_DE 		/* clear ERL and disable FPA */
+#endif
+
+	mtc0	v0, C0_SR		/* reset status register */
+2:
+	la  	gp, _gp			
+
+	la	v0,_fbss 		/* clear bss before using it */
+	la	v1,end 			/* end of bss */
+3:	sw	zero,0(v0)
+	bltu	v0,v1,3b
+	add	v0,4 
+
+
+/************************************************************************
+**
+** 	Temporary Stack - needed to  handle stack saves until
+**			  memory size is determined and permanent stack set
+**
+**			  MUST be uncached to avoid confusion at cache
+**			       switching during memory sizing
+**
+*************************************************************************/
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack is aligned on a
+	 * double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 11f   /* Last three bits Zero, already aligned */
+	nop
+	add	v0, 4
+11:
+#endif
+
+	or	v0, K1BASE		/* switch to uncached */
+	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
+	sub	v1, v1, (4*4)		/* overhead */
+	move	sp, v1			/* set sp to top of stack */
+4:	sw	zero, 0(v0)  
+	bltu	v0, v1, 4b		/* clear out temp stack */
+	add	v0, 4 
+	
+	jal	init_exc_vecs		/* install exception handlers */ 
+	nop				/* MUST do before memory probes */
+
+	la	v0, 5f
+	li	v1, K1BASE		/* force into uncached space */
+	or	v0, v1			/* during memory/cache probes */
+	j	v0
+	nop
+5:
+	la	a0, sim_mem_cfg_struct
+	jal	sim_mem_cfg		/* Make SIM call to get mem size */
+	nop
+	la	a0, sim_mem_cfg_struct
+	lw	a0, 0(a0)		/* Get memory size from struct */
+#ifdef _R3000
+	jal	config_Icache
+	nop
+	jal	config_Dcache		/* determine size of D & I caches */
+	nop	
+#endif
+#ifdef _R4000
+	jal	config_cache		/* determine size of D & I caches */
+	nop
+#endif
+
+	move	v0, a0			/* mem_size */
+
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack (and hence v0
+	 * here) is aligned on a double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 12f   /* Last three bits Zero, already aligned */
+	nop
+	subu	v0, 4	/* mem_size was not aligned on doubleword bdry????*/
+12:
+#endif
+
+
+
+/**************************************************************************
+**
+**  Permanent Stack - now know top of memory, put permanent stack there	
+**
+***************************************************************************/ 
+
+	la	t2, _fbss		/* cache mode as linked */
+	and	t2, 0xF0000000		/* isolate segment */
+	la	t1, 6f
+	j	t1			/* back to original cache mode */
+	nop
+6:
+	or 	v0, t2			/* stack back to original cache mode */
+	addiu   v0,v0,-16		/* overhead */
+	move	sp, v0			/* now replace count w top of memory */
+	move	v1, v0
+	subu	v1, P_STACKSIZE 	/* clear requested stack size */
+
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+	bltu	v1,v0,7b
+	add	v1, 4 
+	.set	reorder
+
+#ifdef _R3000 
+	jal	flush_Icache	
+	jal	flush_Dcache		/* flush Data & Instruction caches */
+#endif
+#ifdef _R4000 
+	jal	flush_cache_nowrite	/* flush Data & Instruction caches */
+#endif
+
+
+
+/**************************************************************************
+**
+**	If this chip supports a Translation Lookaside Buffer, clear it
+**
+***************************************************************************/ 
+
+	.set	noreorder
+	mfc0	t1,  C0_SR		/* look at Status Register */
+	nop
+	.set 	reorder
+#ifdef _R3000
+	li	t2, SR_TS		/* TLB Shutdown bit */
+	and 	t1,t2      		/* TLB Shutdown if 1 */
+	bnez	t1, 8f			/* skip clearing if no TLB */	
+#endif
+
+#ifndef R4650
+	jal	init_tlb		/* clear the tlb */
+#endif
+
+
+/************************************************************************
+**
+**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**
+**  can SKIP if not necessary for application
+**
+************************************************************************/
+8:
+
+	jal	idtsim_init_sbrk
+	jal	idtsim_init_file
+/***********************  END I/O initialization **********************/
+
+
+	jal	main
+
+	jal	idtsim_promexit
+
+ENDFRAME(start)
+
+
+	.globl	sim_mem_cfg
+sim_mem_cfg:
+	.set noat
+	.set noreorder
+	li	AT, (0xbfc00000+((55)*8))
+	jr	AT
+	nop
+	.set at
+	.set reorder
diff --git a/c/src/lib/libbsp/mips/p4000/startup/bspclean.c b/c/src/lib/libbsp/mips/p4000/startup/bspclean.c
new file mode 100644
index 0000000000..ecaff11004
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/startup/bspclean.c
@@ -0,0 +1,30 @@
+/*  bsp_cleanup()
+ *
+ *  This routine normally is part of start.s and usually returns
+ *  control to a monitor.
+ *
+ *  INPUT:  NONE
+ *
+ *  OUTPUT: NONE
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  bspclean.c,v 1.2 1995/05/31 16:56:27 joel Exp
+ */
+#ifndef lint
+static char _sccsid[] = "@(#)bspclean.c 03/15/96     1.1\n";
+#endif
+
+
+#include <rtems.h>
+#include <bsp.h>
+
+void bsp_cleanup( void )
+{
+}
diff --git a/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds b/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds
new file mode 100644
index 0000000000..cf2a80bf8d
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds
@@ -0,0 +1,15 @@
+-map
+-sec
+{
+  .text 0x80010000  :
+  .data  align(16)  :
+  .rodata :
+  .fini :
+#  .sdata :
+  .symtab :
+  .strtab :
+  .debug :
+#  .sbss :
+  .bss     align(8)  :
+  .init 0xbfc00000 :
+}
diff --git a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
new file mode 100644
index 0000000000..66c1a4ecbc
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
@@ -0,0 +1,938 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/
+
+/************************************************************************
+**
+**	idtmem.s - memory and cache functions
+**
+**	Copyright 1991 Integrated Device Technology, Inc.
+**	All Rights Reserved
+**
+**************************************************************************/
+
+/*
+ * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack 
+ * to set mem_size. 
+ */
+
+#include "iregdef.h"
+#include "idtcpu.h"  
+#include "idtmon.h"  
+#include "saunder.h"
+
+
+	.data
+mem_size:
+	.word	0	
+dcache_size:
+	.word 	0		
+icache_size:
+#if defined(CPU_R3000)
+	.word	MINCACHE	
+#endif
+#if defined(CPU_R4000)
+	.word	0
+#endif
+
+#if defined(CPU_R4000)
+	.data
+scache_size:
+	.word 	0
+icache_linesize:
+	.word	0
+dcache_linesize:
+	.word	0
+scache_linesize:
+	.word	0
+#endif
+
+
+		.text
+
+#if defined (CPU_R3000)
+#define CONFIGFRM ((2*4)+4)	
+
+/*************************************************************************
+**
+** Config_Dcache() -- determine size of Data cache 
+**
+**************************************************************************/
+
+FRAME(config_Dcache,sp, CONFIGFRM, ra)
+	.set	noreorder
+	subu	sp,CONFIGFRM
+	sw	ra,CONFIGFRM-4(sp)	/* save return address */
+	sw	s0,4*4(sp)		/* save s0 in first regsave slot */
+	mfc0	s0,C0_SR		/* save SR */
+	nop
+	mtc0	zero,C0_SR		/* disable interrupts */
+	.set	reorder
+	jal	_size_cache		/* returns Data cache size in v0 */
+	sw	v0, dcache_size		/* save it */
+	and 	s0, ~SR_PE		/* do not clear PE */
+	.set	noreorder
+	mtc0	s0,C0_SR		/* restore SR */
+	nop
+	.set	reorder
+	lw	s0, 4*4(sp)		/* restore s0 */
+	lw	ra,CONFIGFRM-4(sp)	/* restore ra */
+	addu	sp,CONFIGFRM		/* pop stack */
+	j	ra
+ENDFRAME(config_Dcache)
+ 
+
+/*************************************************************************
+**
+** Config_Icache() -- determine size of Instruction cache
+**		      MUST be run in uncached mode/handled in idt_csu.s
+**
+**************************************************************************/
+
+FRAME(config_Icache,sp, CONFIGFRM, ra)
+	.set	noreorder
+	subu	sp,CONFIGFRM
+	sw	ra,CONFIGFRM-4(sp)	/* save return address */
+	sw	s0,4*4(sp)		/* save s0 in first regsave slot */
+	mfc0	s0,C0_SR		/* save SR */
+	nop
+ 	mtc0	zero, C0_SR		/* disable interrupts */
+	li	v0,SR_SWC		/* swap caches/disable ints  */
+	mtc0	v0,C0_SR
+	nop
+	.set	reorder
+	jal	_size_cache		/* returns instruction cache size */
+	.set	noreorder
+	mtc0	zero,C0_SR		/* swap back caches */  
+	nop
+	and	s0,~SR_PE		/* do not inadvertantly clear PE */
+	mtc0	s0,C0_SR		/* restore SR */
+	nop
+	.set	reorder
+	sw	v0, icache_size		/* save it AFTER caches back */
+	lw	s0,4*4(sp)		/* restore s0 */
+	lw	ra,CONFIGFRM-4(sp)	/* restore ra */
+	addu	sp,CONFIGFRM		/* pop stack */
+	j	ra
+ENDFRAME(config_Icache)
+
+/************************************************************************
+**
+** _size_cache()
+** returns cache size in v0
+**
+************************************************************************/
+
+FRAME(_size_cache,sp,0,ra)
+	.set	noreorder
+	mfc0	t0,C0_SR		/* save current sr */
+	nop
+	and	t0,~SR_PE		/* do not inadvertently clear PE */
+	or	v0,t0,SR_ISC		/* isolate cache */
+	mtc0	v0,C0_SR
+	/*
+	 * First check if there is a cache there at all
+	 */
+	move	v0,zero
+	li	v1,0xa5a5a5a5		/* distinctive pattern */
+	sw	v1,K0BASE		/* try to write into cache */
+	lw	t1,K0BASE		/* try to read from cache */
+	nop
+	mfc0	t2,C0_SR
+	nop
+	.set	reorder
+	and	t2,SR_CM
+	bne	t2,zero,3f		/* cache miss, must be no cache */
+	bne	v1,t1,3f		/* data not equal -> no cache */
+	/*
+	 * Clear cache size boundries to known state.
+	 */
+	li	v0,MINCACHE
+1:
+	sw	zero,K0BASE(v0)
+	sll	v0,1
+	ble	v0,MAXCACHE,1b
+
+	li	v0,-1
+	sw	v0,K0BASE(zero)		/* store marker in cache */
+	li	v0,MINCACHE		/* MIN cache size */
+
+2:	lw	v1,K0BASE(v0)		/* Look for marker */
+	bne	v1,zero,3f		/* found marker */
+	sll	v0,1			/* cache size * 2 */
+	ble	v0,MAXCACHE,2b		/* keep looking */
+	move	v0,zero			/* must be no cache */
+	.set	noreorder
+3:	mtc0	t0,C0_SR		/* restore sr */
+	j	ra
+	nop
+ENDFRAME(_size_cache)
+	.set	reorder
+
+
+#define FLUSHFRM (2*4)
+
+/***************************************************************************
+**
+** flush_Dcache() -  flush entire Data cache
+**
+****************************************************************************/
+FRAME(flush_Dcache,sp,FLUSHFRM,ra)
+	lw      t2, dcache_size		
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	beq	t2,zero,_Dflush_done	/* no D cache, get out! */
+	nop
+	li	v0, SR_ISC		/* isolate cache */
+	mtc0	v0, C0_SR
+	nop
+	.set	reorder
+	li	t0,K0BASE		/* set loop registers  */
+	or	t1,t0,t2
+
+2:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bne	t0,t1,2b
+
+	.set	noreorder
+_Dflush_done:
+	mtc0	t3,C0_SR		/* restore Status Register */
+	.set	reorder
+	j	ra
+ENDFRAME(flush_Dcache)
+
+
+/***************************************************************************
+**
+** flush_Icache() -  flush entire Instruction cache
+**
+**	NOTE: Icache can only be flushed/cleared when uncached
+**	      Code forces into uncached memory regardless of calling mode
+**
+****************************************************************************/
+FRAME(flush_Icache,sp,FLUSHFRM,ra)
+	lw	t1,icache_size 
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	la	v0,1f
+	li	v1,K1BASE
+	or	v0,v1
+	j	v0			/* force into non-cached space */
+	nop
+1:
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	beq	t1,zero,_Iflush_done	/* no i-cache get out */
+	nop
+	li	v0,SR_ISC|SR_SWC	/* disable intr, isolate and swap */
+	mtc0	v0,C0_SR
+	li	t0,K0BASE
+	.set	reorder
+	or	t1,t0,t1
+
+1:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bne	t0,t1,1b
+	.set	noreorder
+_Iflush_done:
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	.set	reorder
+	j	ra
+ENDFRAME(flush_Icache)
+
+/**************************************************************************
+**
+** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
+**
+**      a0 = base address of portion to be cleared
+**      a1 = byte count of length
+**
+***************************************************************************/
+FRAME(clear_Dcache,sp,0,ra)
+
+	lw  	t2, dcache_size		/* Data cache size */
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	nop
+	nop
+	.set	reorder
+	/*
+	 * flush data cache
+	 */
+
+	.set	noreorder
+	nop
+	li	v0,SR_ISC		/* isolate data cache */
+	mtc0	v0,C0_SR
+	.set	reorder
+	bltu	t2,a1,1f		/* cache is smaller than region */
+	move	t2,a1
+1:	addu	t2,a0			/* ending address + 1 */
+	move	t0,a0
+
+1:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bltu	t0,t2,1b
+
+	.set	noreorder
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	nop
+	.set	reorder
+	j	ra
+ENDFRAME(clear_Dcache)
+
+
+/**************************************************************************
+**
+** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
+**
+**      a0 = base address of portion to be cleared
+**      a1 = byte count of length
+**
+**	NOTE: Icache can only be flushed/cleared when uncached
+**	      Code forces into uncached memory regardless of calling mode
+**
+***************************************************************************/
+FRAME(clear_Icache,sp,0,ra)
+
+	lw      t1, icache_size		/* Instruction cache size */
+	/*
+	 * flush text cache
+	 */
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop 
+	la	v0,1f
+	li	v1,K1BASE
+	or	v0,v1
+	j	v0			/* force into non-cached space */
+	nop
+1:
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	nop
+	nop
+	li	v0,SR_ISC|SR_SWC	/* disable intr, isolate and swap */
+	mtc0	v0,C0_SR
+	.set	reorder
+	bltu	t1,a1,1f		/* cache is smaller than region */
+	move	t1,a1
+1:	addu	t1,a0			/* ending address + 1 */
+	move	t0,a0
+
+	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bltu	t0,t1,1b
+	.set	noreorder
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	nop
+	nop
+	nop				/* allow time for caches to swap */
+	.set	reorder
+	j	ra
+ENDFRAME(clear_Icache)
+
+
+/**************************************************************************
+**
+**  get_mem_conf - get memory configuration 
+**
+***************************************************************************/
+
+
+FRAME(get_mem_conf,sp,0,ra)
+
+	lw	t6, mem_size
+	sw	t6, 0(a0)
+	lw	t7, icache_size
+	sw	t7, 4(a0)
+	lw	t8, dcache_size
+	sw	t8, 8(a0) 
+	j	ra
+
+ENDFRAME(get_mem_conf)
+#endif /* defined CPU_R3000 */
+
+#if defined(CPU_R4000)
+#define LEAF(label)	FRAME(label,sp,0,ra)
+#define XLEAF(label) \
+	.globl label ; \
+label:
+#define END(label)	ENDFRAME(label)
+
+/*
+ * cacheop macro to automate cache operations
+ * first some helpers...
+ */
+#define _mincache(size, maxsize) \
+	bltu	size,maxsize,8f ;	\
+	move	size,maxsize ;		\
+8:
+
+#define _align(tmp, minaddr, maxaddr, linesize) \
+	subu	tmp,linesize,1 ;	\
+	not	tmp ;			\
+	and	minaddr,tmp ;		\
+	addu	maxaddr,-1 ;		\
+	and	maxaddr,tmp
+
+/* This is a bit of a hack really because it relies on minaddr=a0 */
+#define _doop1(op1) \
+	cache	op1,0(a0) 
+
+#define _doop2(op1, op2) \
+	cache	op1,0(a0) ;		\
+	cache	op2,0(a0) 
+
+/* specials for cache initialisation */
+#define _doop1lw1(op1) \
+	cache	op1,0(a0) ;		\
+	lw	zero,0(a0) ;		\
+	cache	op1,0(a0) 
+
+#define _doop121(op1,op2) \
+	cache	op1,0(a0) ;		\
+	nop;				\
+	cache	op2,0(a0) ;		\
+	nop;				\
+	cache	op1,0(a0) 
+
+#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
+	.set	noreorder ;		\
+7: 	_doop##tag##ops ;	 	\
+	bne     minaddr,maxaddr,7b ;	\
+	addu   	minaddr,linesize ;	\
+	.set	reorder
+
+/* finally the cache operation macros */
+#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
+	_mincache(n, cache_size);	\
+ 	blez	n,9f ;			\
+	addu	n,kva ;			\
+	_align(t1, kva, n, cache_linesize) ; \
+	_oploopn(kva, n, cache_linesize, tag, ops) ; \
+9:
+
+#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
+ 	blez	n,9f ;			\
+	addu	n,kva ;			\
+	_align(t1, kva, n, cache_linesize) ; \
+	_oploopn(kva, n, cache_linesize, tag, ops) ; \
+9:
+
+#define icacheop(kva, n, cache_size, cache_linesize, op) \
+	icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
+
+#define vcacheop(kva, n, cache_size, cache_linesize, op) \
+	vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
+
+	.text
+
+/*
+ * static void _size_cache()    R4000
+ * 
+ * Internal routine to determine cache sizes by looking at R4000 config
+ * register.  Sizes are returned in registers, as follows:
+ *	t2	icache size
+ *	t3	dcache size
+ *	t6	scache size
+ *	t4	icache line size
+ *	t5	dcache line size
+ *	t7	scache line size
+ */
+LEAF(_size_cache)
+	mfc0	t0,C0_CONFIG
+
+	and	t1,t0,CFG_ICMASK
+	srl	t1,CFG_ICSHIFT
+	li	t2,0x1000
+	sll	t2,t1
+
+	and	t1,t0,CFG_DCMASK
+	srl	t1,CFG_DCSHIFT
+	li	t3,0x1000
+	sll	t3,t1
+
+	li	t4,32
+	and	t1,t0,CFG_IB
+	bnez	t1,1f
+	li	t4,16
+1:	
+
+	li	t5,32
+	and	t1,t0,CFG_DB
+	bnez	t1,1f
+	li	t5,16
+1:	
+
+	move	t6,zero			# default to no scache
+	move	t7,zero			#
+
+	and	t1,t0,CFG_C_UNCACHED	# test config register
+	bnez	t1,1f			# no scache if uncached/non-coherent
+	
+	li	t6,0x100000		# assume 1Mb scache <<-NOTE
+	and	t1,t0,CFG_SBMASK
+	srl	t1,CFG_SBSHIFT
+	li	t7,16
+	sll	t7,t1
+1:	j	ra
+END(_size_cache)
+
+
+/*
+ * void config_cache()   R4000
+ * 
+ * Work out size of I, D & S caches, assuming they are already initialised.
+ */
+LEAF(config_cache)
+	lw	t0,icache_size
+	bgtz	t0,8f			# already known?
+	move	v0,ra
+	bal	_size_cache
+	move	ra,v0
+
+	sw	t2,icache_size
+	sw	t3,dcache_size
+	sw	t6,scache_size
+	sw	t4,icache_linesize
+	sw	t5,dcache_linesize
+	sw	t7,scache_linesize
+8:	j	ra
+END(config_cache)
+
+
+/*
+ * void _init_cache()   R4000
+ */
+LEAF(_init_cache)
+	/*
+ 	 * First work out the sizes
+	 */
+	move	v0,ra
+	bal	_size_cache
+	move	ra,v0
+	
+	/*
+	 * The caches may be in an indeterminate state,
+	 * so we force good parity into them by doing an
+	 * invalidate, load/fill, invalidate for each line.
+	 */
+
+	/* disable all i/u and cache exceptions */
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	or	v1,SR_DE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	/* assume bottom of RAM will generate good parity for the cache */
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t2		# icache_size
+	move	a3,t4		# icache_linesize
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
+
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t3		# dcache_size
+	move	a3,t5		# dcache_linesize
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
+
+	/* assume unified I & D in scache <<-NOTE */
+	blez	t6,1f
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t6
+	move	a3,t7
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
+
+1:	mtc0	v0,C0_SR
+	j	ra
+END(_init_cache)
+	
+
+/*
+ * void flush_cache (void)   R4000
+ *
+ * Flush and invalidate all caches
+ */
+LEAF(flush_cache)
+	/* secondary cacheops do all the work if present */
+	lw	a2,scache_size
+	blez	a2,1f
+	lw	a3,scache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
+	b	2f
+
+1:	
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+2:	j	ra
+END(flush_cache)
+	
+/*
+ * void flush_cache_nowrite (void)   R4000
+ *
+ * Invalidate all caches
+ */
+LEAF(flush_cache_nowrite)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(flush_cache_nowrite)
+	
+/*
+ * void clean_cache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in all caches
+ */
+LEAF(clean_cache)
+XLEAF(clear_cache)
+
+	/* secondary cacheops do all the work (if fitted) */
+	lw	a2,scache_size
+	blez	a2,1f
+	lw	a3,scache_linesize
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
+	b	2f
+
+1:	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	/* save kva & n for subsequent loop */
+	move	t8,a0
+	move	t9,a1
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	/* restore kva & n */
+	move	a0,t8
+	move	a1,t9
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_cache)
+	
+/*
+ * void clean_dcache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in primary data cache
+ */
+LEAF(clean_dcache)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_dcache)
+	
+/*
+ * void clean_dcache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate indexed range in primary data cache
+ */
+LEAF(clean_dcache_indexed)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_dcache_indexed)
+	
+/*
+ * void clean_dcache_nowrite (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate an address range in primary data cache
+ */
+LEAF(clean_dcache_nowrite)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
+
+2:	j	ra
+END(clean_dcache_nowrite)
+	
+/*
+ * void clean_dcache_nowrite_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in primary data cache
+ */
+LEAF(clean_dcache_nowrite_indexed)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(clean_dcache_nowrite_indexed)
+	
+/*
+ * void clean_icache (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate address range in primary instruction cache
+ */
+LEAF(clean_icache)
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
+
+2:	j	ra
+END(clean_icache)
+	
+/*
+ * void clean_icache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in primary instruction cache
+ */
+LEAF(clean_icache_indexed)
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+2:	j	ra
+END(clean_icache_indexed)
+	
+
+
+/*
+ * void clean_scache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in secondary cache
+ */
+LEAF(clean_scache)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
+
+2:	j	ra
+END(clean_scache)
+	
+/*
+ * void clean_scache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate indexed range in secondary cache
+ */
+LEAF(clean_scache_indexed)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
+
+2:	j	ra
+END(clean_scache_indexed)
+	
+/*
+ * void clean_scache_nowrite (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate an address range in secondary cache
+ */
+LEAF(clean_scache_nowrite)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
+
+2:	j	ra
+END(clean_scache_nowrite)
+	
+/*
+ * void clean_scache_nowrite_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in secondary cache
+ */
+LEAF(clean_scache_nowrite_indexed)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(clean_scache_nowrite_indexed)
+	
+/**************************************************************************
+**
+**  get_mem_conf - get memory configuration  R4000
+**
+***************************************************************************/
+
+
+FRAME(get_mem_conf,sp,0,ra)
+
+	lw	t6, mem_size
+	sw	t6, 0(a0)
+	lw	t7, icache_size
+	sw	t7, 4(a0)
+	lw	t8, dcache_size
+	sw	t8, 8(a0) 
+	lw	t7, scache_size
+	sw	t7, 12(a0) 
+	j	ra
+
+ENDFRAME(get_mem_conf)
+
+#endif /* defined(CPU_R4000) */
+
+/*
+ * void set_mem_size (mem_size) 
+ *
+ * config_memory()'s memory size gets written into mem_size here.
+ * Now we don't need to call config_cache() with memory size - New to IDTC6.0
+ */
+FRAME(set_memory_size,sp,0,ra)
+	sw	a0, mem_size
+	j	ra
+ENDFRAME(set_memory_size)
+
+
diff --git a/c/src/lib/libbsp/mips/p4000/startup/linkcmds b/c/src/lib/libbsp/mips/p4000/startup/linkcmds
new file mode 100644
index 0000000000..e9d0566a12
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/startup/linkcmds
@@ -0,0 +1,69 @@
+/* @(#)linkcmds       04/08/96     1.2 */
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+_DYNAMIC_LINK = 0;
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text 0x80030000  :				/* */
+/*  .text 0xa0020000  :				/* */
+/*  .text 0x00020000  :				/* */
+  {
+    _ftext = . ;
+    *(.text)
+    CREATE_OBJECT_SYMBOLS
+    _etext = .;
+  }
+  .init    ALIGN(8)  : { *(.init)    } =0
+  .fini    ALIGN(8)  : { *(.fini)    } =0
+  .ctors   ALIGN(8)  : { *(.ctors)   }
+  .dtors   ALIGN(8)  : { *(.dtors)   }
+  .rodata  ALIGN(8)  : { *(.rodata)  }
+  .rodata1 ALIGN(8)  :
+    {
+      *(.rodata1)
+      . = ALIGN(8);
+    }
+  .reginfo . : { *(.reginfo) }
+  /* also: .hash .dynsym .dynstr .plt(if r/o) .rel.got */
+  /* Read-write section, merged into data segment: */
+  .data  ALIGN(16)  :
+  {
+    _fdata = . ;
+    *(.data)
+    CONSTRUCTORS
+  }
+  .data1 ALIGN(8)  : { *(.data1) }
+  _gp = . + 0x8000;
+  .lit8 . : { *(.lit8) }
+  .lit4 . : { *(.lit4) }
+  /* also (before uninitialized portion): .dynamic .got .plt(if r/w)
+     (or does .dynamic go into its own segment?) */
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   ALIGN(8)  : { *(.sdata) }
+  _edata  =  .;
+  __bss_start = ALIGN(8);
+  _fbss = .;
+  .sbss    ALIGN(8)  : { *(.sbss) *(.scommon) }
+  .bss     ALIGN(8)  :
+  {
+   *(.bss)
+   *(COMMON)
+   _end = . ;
+   end = . ;
+  }
+  /* Debug sections.  These should never be loadable, but they must have
+     zero addresses for the debuggers to work correctly.  */
+  .line			0 : { *(.line)			}
+  .debug		0 : { *(.debug)			}
+  .debug_sfnames	0 : { *(.debug_sfnames)		}
+  .debug_srcinfo	0 : { *(.debug_srcinfo)		}
+  .debug_macinfo	0 : { *(.debug_macinfo)		}
+  .debug_pubnames	0 : { *(.debug_pubnames)	}
+  .debug_aranges	0 : { *(.debug_aranges)		}
+}
+
diff --git a/c/src/lib/libbsp/mips/p4000/startup/setvec.c b/c/src/lib/libbsp/mips/p4000/startup/setvec.c
new file mode 100644
index 0000000000..1c6b581296
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/startup/setvec.c
@@ -0,0 +1,51 @@
+/*  set_vector
+ *
+ *  This routine installs an interrupt vector on the target Board/CPU.
+ *  This routine is allowed to be as board dependent as necessary.
+ *
+ *  INPUT:
+ *    handler - interrupt handler entry point
+ *    vector  - vector number
+ *    type    - 0 indicates raw hardware connect
+ *              1 indicates RTEMS interrupt connect
+ *
+ *  RETURNS:
+ *    address of previous interrupt handler
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  setvec.c,v 1.2 1995/05/31 16:56:35 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)setvec.c 04/25/96     1.2\n";
+#endif
+
+#include <rtems.h>
+#include <bsp.h>
+
+#include <excepthdr.h>
+
+mips_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+)
+{
+  mips_isr_entry previous_isr;
+
+  if ( type )
+    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
+  else {
+    /* XXX: install non-RTEMS ISR as "raw" interupt */
+    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
+  }
+  return previous_isr;
+}
+
diff --git a/c/src/lib/libbsp/mips/p4000/times b/c/src/lib/libbsp/mips/p4000/times
new file mode 100644
index 0000000000..6a3dbfe1fb
--- /dev/null
+++ b/c/src/lib/libbsp/mips/p4000/times
@@ -0,0 +1,200 @@
+#
+#  Timing Test Suite Results for the NO_BSP
+#
+#  NOTE: This is just a template.  The times are irrelevant since this BSP
+#        can only be compiled -- not executed.
+#
+#  times,v 1.2 1995/12/07 15:44:23 joel Exp
+#
+# @(#)times        08/01/96     1.4
+
+NOTE:  To obtain the execution time in microseconds, divide the number of
+       cycles by the clock speed.  For example, if rtems_semaphore create
+       is reported to be 1164 cycles, then at 66 Mhz it takes 17.64
+       microseconds or 8.75 microseconds at 133 Mhz.
+
+Board: Algorithmics P4000i 
+CPU: IDT 4650
+Clock Speed: 100MHz
+Memory Configuration: SRAM, DRAM, cache, etc
+Wait States:
+
+Times Reported in: cycles
+Timer Source: on-CPU cycle counter
+
+Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types
+Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types
+
+#                          DESCRIPTION                                 A    B
+== =================================================================  ==== ====
+ 1 rtems_semaphore_create                                              788  759
+   rtems_semaphore_delete                                              903  945
+   rtems_semaphore_obtain: available                                   119  119
+   rtems_semaphore_obtain: not available -- NO_WAIT                    118  118
+   rtems_semaphore_release: no waiting tasks                           127  127
+
+ 2 rtems_semaphore_obtain: not available -- caller blocks              842  840
+
+ 3 rtems_semaphore_release: task readied -- preempts caller            777  751
+
+ 4 rtems_task_restart: blocked task -- preempts caller                1611 1595
+   rtems_task_restart: ready task -- preempts caller                  1253 1395
+   rtems_semaphore_release: task readied -- returns to caller          365  345
+   rtems_task_create                                                   798  797
+   rtems_task_start                                                    464  460
+   rtems_task_restart: suspended task -- returns to caller             517  517
+   rtems_task_delete: suspended task                                   529  595
+   rtems_task_restart: ready task -- returns to caller                 527  525
+   rtems_task_restart: blocked task -- returns to caller               707  684
+   rtems_task_delete: blocked task                                     609  675
+
+ 5 rtems_task_suspend: calling task                                    549  549
+   rtems_task_resume: task readied -- preempts caller                  702  699
+
+ 6 rtems_task_restart: calling task                                    291  291
+   rtems_task_suspend: returns to caller                               195  194
+   rtems_task_resume: task readied -- returns to caller                198  198
+   rtems_task_delete: ready task                                       734  736
+
+ 7 rtems_task_restart: suspended task -- preempts caller              1049  990
+
+ 8 rtems_task_set_priority: obtain current priority                     94   94
+   rtems_task_set_priority: returns to caller                          418  355
+   rtems_task_mode: obtain current mode                                 44   43
+   rtems_task_mode: no reschedule                                        0   49
+   rtems_task_mode: reschedule -- returns to caller                      0  232 
+   rtems_task_mode: reschedule -- preempts caller                        0  687
+   rtems_task_set_note                                                   0  101
+   rtems_task_get_note                                                   0  103
+   rtems_clock_set                                                       0  237
+   rtems_clock_get                                                       0   16
+
+ 9 rtems_message_queue_create                                         3583 3432
+   rtems_message_queue_send: no waiting tasks                          252  252
+   rtems_message_queue_urgent: no waiting tasks                        252  252
+   rtems_message_queue_receive: available                              207  207
+   rtems_message_queue_flush: no messages flushed                       95   96
+   rtems_message_queue_flush: messages flushed                         110  110
+   rtems_message_queue_delete                                         1044 1111
+
+10 rtems_message_queue_receive: not available -- NO_WAIT               132  131
+   rtems_message_queue_receive: not available -- caller blocks         884  892
+
+11 rtems_message_queue_send: task readied -- preempts caller           397  817 
+
+12 rtems_message_queue_send: task readied -- returns to caller         397  397
+
+13 rtems_message_queue_urgent: task readied -- preempts caller         816  817
+
+14 rtems_message_queue_urgent: task readied -- returns to caller       397  398
+
+15 rtems_event_receive: obtain current events                            5    5
+   rtems_event_receive: not available -- NO_WAIT                        99   99
+   rtems_event_receive: not available -- caller blocks                 689  689
+   rtems_event_send: no task readied                                   123  123
+   rtems_event_receive: available                                      326  349
+   rtems_event_send: task readied -- returns to caller                 333  429
+
+16 rtems_event_send: task readied -- preempts caller                   843  838
+
+17 rtems_task_set_priority: preempts caller                           1002  991
+
+18 rtems_task_delete: calling task                                    1171 1157
+
+19 rtems_signal_catch                                                    0 1306
+   rtems_signal_send: returns to caller                                  0 1019
+   rtems_signal_send: signal to self                                     0  496
+   exit ASR overhead: returns to calling task                            0  120
+   exit ASR overhead: returns to preempting task                         0   73
+
+20 rtems_partition_create                                             1293 1306
+   rtems_region_create                                                1010 1019
+   rtems_partition_get_buffer: available                               481  496
+   rtems_partition_get_buffer: not available                           120  120
+   rtems_partition_return_buffer                                       587  460
+   rtems_partition_delete                                              379  320
+   rtems_region_get_segment: available                                 179  179
+   rtems_region_get_segment: not available -- NO_WAIT                  349  293
+   rtems_region_return_segment: no waiting tasks                       335  322
+   rtems_region_get_segment: not available -- caller blocks           1603 1496
+   rtems_region_return_segment: task readied -- preempts caller       1616 1533
+   rtems_region_return_segment: task readied -- returns to caller      940  939
+   rtems_region_delete                                                 301  348
+   rtems_io_initialize                                                   9   10
+   rtems_io_open                                                         6    6
+   rtems_io_close                                                        6    6
+   rtems_io_read                                                         6    6
+   rtems_io_write                                                        6    5
+   rtems_io_control                                                      6    6
+
+21 rtems_task_ident                                                   1057 1058
+   rtems_message_queue_ident                                           963  963
+   rtems_semaphore_ident                                              1137 1136
+   rtems_partition_ident                                               962  961
+   rtems_region_ident                                                  923  924
+   rtems_port_ident                                                    918  917
+   rtems_timer_ident                                                   942  941
+   rtems_rate_monotonic_ident                                          924  925
+
+22 rtems_message_queue_broadcast: task readied -- returns to caller   1084 1095
+   rtems_message_queue_broadcast: no waiting tasks                     147  148
+   rtems_message_queue_broadcast: task readied -- preempts caller     1305 1268
+
+23 rtems_timer_create                                                  202  201
+   rtems_timer_fire_after: inactive                                    261  261
+   rtems_timer_fire_after: active                                      271  269
+   rtems_timer_cancel: active                                          142  141
+   rtems_timer_cancel: inactive                                        122  124
+   rtems_timer_reset: inactive                                         222  222
+   rtems_timer_reset: active                                           246  245
+   rtems_timer_fire_when: inactive                                     312  311
+   rtems_timer_fire_when: active                                       358  358
+   rtems_timer_delete: active                                          263  263
+   rtems_timer_delete: inactive                                        247  247
+   rtems_task_wake_when                                                833  831
+
+24 rtems_task_wake_after: yield -- returns to caller                    99   98
+   rtems_task_wake_after: yields -- preempts caller                    479  478
+
+25 rtems_clock_tick                                                    313  318
+
+26 _ISR_Disable                                                         64   57
+   _ISR_Flash                                                           51   36
+   _ISR_Enable                                                          31   18
+   _Thread_Disable_dispatch                                             53   37
+   _Thread_Enable_dispatch                                             260  233
+   _Thread_Set_state                                                   446  463
+   _Thread_Disptach (NO FP)                                            839  801
+   context switch: no floating point contexts                          673  653
+   context switch: self                                                156  162
+   context switch: to another task                                      84   70
+   context switch: restore 1st FP task                                1030 1013
+   fp context switch: save idle, restore idle                          969  948
+   fp context switch: save idle, restore initialized                   275  267
+   fp context switch: save initialized, restore initialized            319  292
+   _Thread_Resume                                                      512  480
+   _Thread_Unblock                                                     121  139
+   _Thread_Ready                                                       199  203
+   _Thread_Get                                                          27   27
+   _Semaphore_Get                                                       20   21
+   _Thread_Get: invalid id                                               5    5
+
+27 interrupt entry overhead: returns to interrupted task                 0    0
+   interrupt exit overhead: returns to interrupted task                 27   41
+   interrupt entry overhead: returns to nested interrupt                 0    0
+   interrupt exit overhead: returns to nested interrupt                  0    0
+   interrupt entry overhead: returns to preempting task                  0    0
+   interrupt exit overhead: returns to preempting task                   0    0
+
+28 rtems_port_create                                                   574  560
+   rtems_port_external_to_internal                                      87   87
+   rtems_port_internal_to_external                                      86   86
+   rtems_port_delete                                                   395  353
+
+29 rtems_rate_monotonic_create                                         621  633
+   rtems_rate_monotonic_period: initiate period -- returns to caller   773  694
+   rtems_rate_monotonic_period: obtain status                          295  284
+   rtems_rate_monotonic_cancel                                         408  451
+   rtems_rate_monotonic_delete: inactive                               453  471
+   rtems_rate_monotonic_delete: active                                 332  336
+   rtems_rate_monotonic_period: conclude periods -- caller blocks      664  686
diff --git a/c/src/lib/libbsp/mips64orion/p4000/README b/c/src/lib/libbsp/mips64orion/p4000/README
new file mode 100644
index 0000000000..31152f15ec
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/README
@@ -0,0 +1,47 @@
+#
+#  README,v 1.2 1995/05/31 16:56:03 joel Exp
+#
+# @(#)README        08/20/96     1.2
+#
+
+BSP NAME:           p4000
+BOARD:              Algorithmics P4000 SBC
+BUS:                N/A
+CPU FAMILY:         mips
+CPU:                IDT 4650 
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+
+DEBUG MONITOR:      IDT/SIM
+
+PERIPHERALS
+===========
+TIMERS:             4650 internal
+  RESOLUTION:         half of internal clock frequency
+SERIAL PORTS:       IDT/SIM controlled
+REAL-TIME CLOCK:    none
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       4650 internal
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A 
+TIMER DRIVER:       4650 internal
+TTY DRIVER:         uses IDT/SIM
+
+STDIO
+=====
+PORT:               Console port 0
+ELECTRICAL:         RS-232
+BAUD:               9600
+BITS PER CHARACTER: 8
+PARITY:             None
+STOP BITS:          1
+
+NOTES
+=====
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/console/console.c b/c/src/lib/libbsp/mips64orion/p4000/console/console.c
new file mode 100644
index 0000000000..cc52dc3c7c
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/console/console.c
@@ -0,0 +1,270 @@
+/*
+ *  This file contains the IDT 4650 console IO package.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  console.c,v 1.4 1995/12/05 19:23:02 joel Exp
+ */
+
+
+#ifndef lint
+static char _sccsid[] = "@(#)console.c 08/20/96     1.6\n";
+#endif
+
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <ctype.h>
+
+char idtsim_getchar( void );
+void idtsim_putchar( char c );
+void mips_leddisplay( char a, char b, char c, char d );
+
+
+/*  console_initialize
+ *
+ *  This routine initializes the console IO driver.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ */
+
+rtems_device_driver console_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  minor,
+  void                      *arg
+)
+{
+  rtems_status_code status;
+ 
+  status = rtems_io_register_name(
+    "/dev/console",
+    major,
+    (rtems_device_minor_number) 0
+  );
+ 
+  if (status != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred(status);
+ 
+  return RTEMS_SUCCESSFUL;
+}
+
+
+/*  is_character_ready
+ *
+ *  This routine returns TRUE if a character is available.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ */
+
+rtems_boolean is_character_ready(
+  char *ch
+)
+{
+  *ch = '\0';   /* return NULL for no particular reason */
+  return(TRUE);
+}
+
+/*  inbyte
+ *
+ *  This routine reads a character from the SOURCE.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    character read from SOURCE
+ */
+
+char inbyte( void )
+{
+  /*
+   *  If polling, wait until a character is available.
+   */
+
+   return idtsim_getchar();
+}
+
+/*  outbyte
+ *
+ *  This routine transmits a character out the SOURCE.  It may support
+ *  XON/XOFF flow control.
+ *
+ *  Input parameters:
+ *    ch  - character to be transmitted
+ *
+ *  Output parameters:  NONE
+ */
+
+void outbyte(
+  char ch
+)
+{
+#define NUM_LEDS 4
+   static unsigned int cur_led = 0;
+   static unsigned char led_chars[NUM_LEDS];
+
+  /*
+   *  If polling, wait for the transmitter to be ready.
+   *  Check for flow control requests and process.
+   *  Then output the character.
+   */
+
+  idtsim_putchar( ch );
+
+  /* print out first four alpha numeric characters in a line */
+  if ( ch == '\n' )
+  {
+    mips_leddisplay( led_chars[0], led_chars[1], led_chars[2], led_chars[3] );
+    cur_led = 0;
+  }
+  else if ( isalnum( ch ) && cur_led < NUM_LEDS )
+  {
+    led_chars[cur_led++] = ch;
+  }
+
+}
+
+
+static int console_fd = -1;
+
+/*
+ *  Open entry point
+ */
+
+rtems_device_driver console_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+#if 0
+  int console_fd = open("tty0", 2); /* open for read/write */
+#endif
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  Close entry point
+ */
+
+rtems_device_driver console_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+#if 0
+  if ( console_fd )
+    close( console_fd );
+#endif
+  return RTEMS_SUCCESSFUL;
+}
+
+/*
+ * read bytes from the serial port. We only have stdin.
+ */
+
+rtems_device_driver console_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+  int maximum;
+  int count = 0;
+ 
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    buffer[ count ] = inbyte();
+    if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
+      buffer[ count++ ]  = '\n';
+      buffer[ count ]  = 0;
+      break;
+    }
+  }
+
+  rw_args->bytes_moved = count;
+  return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
+}
+
+/*
+ * write bytes to the serial port. Stdout and stderr are the same. 
+ */
+
+rtems_device_driver console_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  int count;
+  int maximum;
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+
+  rw_args = (rtems_libio_rw_args_t *) arg;
+
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+
+  for (count = 0; count < maximum; count++) {
+    if ( buffer[ count ] == '\n') {
+      outbyte('\r');
+    }
+    outbyte( buffer[ count ] );
+  }
+
+  rw_args->bytes_moved = maximum;
+  return 0;
+}
+
+/*
+ *  IO Control entry point
+ */
+
+rtems_device_driver console_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/mips64orion/p4000/console/led.S b/c/src/lib/libbsp/mips64orion/p4000/console/led.S
new file mode 100644
index 0000000000..b9b7b7e294
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/console/led.S
@@ -0,0 +1,20 @@
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtmon.h>
+#include <rtems/score/idtcpu.h>
+
+
+FRAME(mips_leddisplay,sp,0,ra)
+	j ra
+	nop
+ENDFRAME(mips_leddisplay)
+
+FRAME(sbddisplay,sp,0,ra)
+	j	ra
+ENDFRAME(sbddisplay)
+
+
+FRAME(sbdblank,sp,0,ra)
+	j	ra
+ENDFRAME(sbdblank)
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h b/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h
new file mode 100644
index 0000000000..1a9f6a5653
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h
@@ -0,0 +1,120 @@
+/*  bsp.h
+ *
+ *  This include file contains all board IO definitions.
+ *
+ *  XXX : put yours in here
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  bsp.h,v 1.4 1995/09/11 19:29:04 joel Exp
+ */
+/* @(#)bsp.h       03/15/96     1.1 */
+
+#ifndef __NO_BSP_h
+#define __NO_BSP_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems.h>
+#include <console.h>
+#include <clockdrv.h>
+
+extern void WriteDisplay( char * string );
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
+
+#define Cause_tm27_intr()
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+
+extern unsigned32 mips_get_timer( void );
+
+#define CPU_CLOCK_RATE_MHZ     (50)
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+#define delay( microseconds ) \
+  { \
+     unsigned32 _end_clock = mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
+     _end_clock %= 0x100000000;  /* make sure result is 32 bits */ \
+     \
+     /* handle timer overflow, if necessary */ \
+     while ( _end_clock < mips_get_timer() );  \
+     \
+     while ( _end_clock > mips_get_timer() ); \
+  }
+
+/* Constants */
+
+#define RAM_START 0
+#define RAM_END   0x100000
+
+/* miscellaneous stuff assumed to exist */
+
+extern rtems_configuration_table BSP_Configuration;
+
+/*
+ *  Device Driver Table Entries
+ */
+
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+
+/*
+ * How many libio files we want
+ */
+
+#define BSP_LIBIO_MAX_FDS       20
+
+/* functions */
+
+void bsp_cleanup( void );
+
+mips_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h b/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h
new file mode 100644
index 0000000000..716faef06b
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h
@@ -0,0 +1,116 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C.  These are used in the
+ *  Timing Test Suite to ignore the overhead required to pass arguments
+ *  to directives.  On some CPUs and/or target boards, this overhead
+ *  is significant and makes it difficult to distinguish internal
+ *  RTEMS execution time from that used to call the directive.
+ *  This file should be updated after running the C overhead timing
+ *  test.  Once this update has been performed, the RTEMS Time Test
+ *  Suite should be rebuilt to account for these overhead times in the
+ *  timing results.
+ *
+ *  NOTE:  If these are all zero, then the times reported include all
+ *         all calling overhead including passing of arguments.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  coverhd.h,v 1.2 1995/05/31 16:56:15 joel Exp
+ */
+/* @(#)coverhd.h       04/08/96     1.3 */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      5
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        4
+#define CALLING_OVERHEAD_TASK_CREATE               6
+#define CALLING_OVERHEAD_TASK_IDENT                4
+#define CALLING_OVERHEAD_TASK_START                5
+#define CALLING_OVERHEAD_TASK_RESTART              4
+#define CALLING_OVERHEAD_TASK_DELETE               4
+#define CALLING_OVERHEAD_TASK_SUSPEND              4
+#define CALLING_OVERHEAD_TASK_RESUME               4
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         5
+#define CALLING_OVERHEAD_TASK_MODE                 4
+#define CALLING_OVERHEAD_TASK_GET_NOTE             5
+#define CALLING_OVERHEAD_TASK_SET_NOTE             5
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            9
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           4
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           5
+#define CALLING_OVERHEAD_CLOCK_GET                 9
+#define CALLING_OVERHEAD_CLOCK_SET                 8
+#define CALLING_OVERHEAD_CLOCK_TICK                3
+
+#define CALLING_OVERHEAD_TIMER_CREATE              4
+#define CALLING_OVERHEAD_TIMER_IDENT               4
+#define CALLING_OVERHEAD_TIMER_DELETE              4
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          6
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           10
+#define CALLING_OVERHEAD_TIMER_RESET               4
+#define CALLING_OVERHEAD_TIMER_CANCEL              4
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          5
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           4
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          4
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          5
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     5
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       4
+
+#define CALLING_OVERHEAD_EVENT_SEND                4
+#define CALLING_OVERHEAD_EVENT_RECEIVE             5
+#define CALLING_OVERHEAD_SIGNAL_CATCH              5
+#define CALLING_OVERHEAD_SIGNAL_SEND               4
+#define CALLING_OVERHEAD_PARTITION_CREATE          6
+#define CALLING_OVERHEAD_PARTITION_IDENT           4
+#define CALLING_OVERHEAD_PARTITION_DELETE          4
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      4
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   4
+#define CALLING_OVERHEAD_REGION_CREATE             6
+#define CALLING_OVERHEAD_REGION_IDENT              4
+#define CALLING_OVERHEAD_REGION_DELETE             4
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        5
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     4
+#define CALLING_OVERHEAD_PORT_CREATE               6
+#define CALLING_OVERHEAD_PORT_IDENT                4
+#define CALLING_OVERHEAD_PORT_DELETE               4
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             5
+#define CALLING_OVERHEAD_IO_OPEN                   5
+#define CALLING_OVERHEAD_IO_CLOSE                  5
+#define CALLING_OVERHEAD_IO_READ                   5
+#define CALLING_OVERHEAD_IO_WRITE                  5
+#define CALLING_OVERHEAD_IO_CONTROL                5
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     4
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     4
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S b/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S
new file mode 100644
index 0000000000..fb8f28edbc
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S
@@ -0,0 +1,58 @@
+#include "iregdef.h"
+#include "idtcpu.h"
+
+#define FRAME(name,frm_reg,offset,ret_reg)      \
+        .globl  name;                           \
+        .ent    name;                           \
+name:;                                          \
+        .frame  frm_reg,offset,ret_reg
+
+#define ENDFRAME(name)                          \
+        .end name
+
+#define PROM_LINK(name,entry)           \
+        .globl  name;                   \
+        .ent    name;                   \
+name:   la      $2,+entry;              \
+        j       $2;                     \
+        .end name
+
+#define	PROM_ENTRY(x)	(0xbfc00000+((x)*8))
+
+#define PROM_RESET	PROM_ENTRY(0)
+#define PROM_NOT_IMP	PROM_ENTRY(1)
+#define PROM_RESTART	PROM_ENTRY(2)
+#define PROM_REINIT	PROM_ENTRY(3)
+#define	PROM_GETCHAR	PROM_ENTRY(11)
+#define	PROM_PUTCHAR	PROM_ENTRY(12)
+#define	PROM_SHOWCHAR	PROM_ENTRY(13)
+#define	PROM_PRINTF	PROM_ENTRY(16)
+#define	PROM_RETURN	PROM_ENTRY(17)
+
+#define	PROM_RGETS	PROM_ENTRY(25)
+#define PROM_FLUSHCACHE	PROM_ENTRY(28)
+#define PROM_CLEARCACHE	PROM_ENTRY(29)
+#define PROM_SETJMP	PROM_ENTRY(30)
+#define PROM_LONGJMP	PROM_ENTRY(31)
+
+	.text
+
+PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
+PROM_LINK(idtsim_getchar, PROM_GETCHAR)
+PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
+PROM_LINK(idtsim__exit, PROM_RETURN)
+PROM_LINK(idtsim_reinit, PROM_REINIT)
+PROM_LINK(idtsim_restart, PROM_RESTART)
+PROM_LINK(idtsim_reset, PROM_RESET)
+PROM_LINK(idtsim_promexit, PROM_RETURN)
+PROM_LINK(idtsim_setjmp, PROM_SETJMP)
+PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
+
+FRAME(idtsim_init_sbrk,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_sbrk)
+
+FRAME(idtsim_init_file,sp,0,ra)
+	j	ra
+ENDFRAME(idtsim_init_file)
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/start/start.S b/c/src/lib/libbsp/mips64orion/p4000/start/start.S
new file mode 100644
index 0000000000..bbedf0c5dd
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/start/start.S
@@ -0,0 +1,298 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*************************************************************************
+**
+** Copyright 1991-95 Integrated Device Technology, Inc.
+**	All Rights Reserved
+**
+** idt_csu.S -- IDT stand alone startup code
+**
+**************************************************************************/
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+
+.extern _fbss,4		  /* this is defined by the linker */
+.extern end,4		  /* this is defined by the linker */
+
+.lcomm sim_mem_cfg_struct,12
+
+	.text
+
+
+#define TMP_STKSIZE  1024 
+
+/**************************************************************************
+**
+**  start - Typicl standalone start up code required for R3000/R4000
+**
+**
+**	1)  Initialize the STATUS Register
+**		a) Clear parity error bit
+**		b) Set co_processor 1 usable bit ON
+**		c) Clear all IntMask Enables
+**		d) Set kernel/disabled mode
+**	2)  Initialize Cause Register
+**		a)  clear software interrupt bits       
+**	3)  Determine FPU installed or not
+**		if not, clear CoProcessor 1 usable bit
+**	4)  Clear bss area
+**	5)  MUST allocate temporary stack until memory size determined
+**	    It MUST be uncached to prevent overwriting when caches are cleared
+**	6)  Install exception handlers
+**	7)  Determine memory and cache sizes
+**	8)  Establish permanent stack (cached or uncached as defined by bss)
+**	9)  Flush Instruction and Data caches
+** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
+** 	11)  Execute initialization code if the IDT/c library is to be used
+** 
+** 	12)  Jump to user's "main()"
+** 	13)  Jump to promexit
+**
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	This is used to mark code specific to R3xxx or R4xxx processors.
+**	IDT/C 6.x defines __mips to be the ISA level for which we're 
+**	generating code. This is used to make sure the stack etc. is 
+**	double word aligned, when using -mips3 (default) or -mips2, 
+**	when compiling with IDT/C6.x
+**
+***************************************************************************/
+
+FRAME(start,sp,0,ra)
+
+	.set	noreorder
+#ifdef _R3000
+	li	v0,SR_PE|SR_CU1        /* reset parity error and set */
+					/* cp1 usable */
+#endif
+#ifdef _R4000
+#if __mips==3 || defined(R4650)
+	li	v0,SR_CU1|SR_DE|SR_FR 	/* initally clear ERL, enable FPA 64bit regs*/
+	                                /* 4650: Need fr to be set anyway */
+#else
+	li	v0,SR_CU1|SR_DE 	/* initally clear ERL, enable FPA 32bit regs*/
+#endif mips3
+#endif
+
+	mtc0	v0,C0_SR		/* clr IntMsks/ kernel/disabled mode */
+	nop
+	mtc0	zero,C0_CAUSE		/* clear software interrupts */
+	nop
+
+#ifdef _R4000
+	li	v0,CFG_C_NONCOHERENT	# initialise default cache mode
+	mtc0	v0,C0_CONFIG
+#endif
+
+/*
+**	check to see if an fpu is really plugged in 
+*/
+	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
+	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	zero,fp1		/* try to write zero in fp	*/
+	mfc1	t0,fp0
+	mfc1	t1,fp1
+	nop
+	bne	t0,t3,1f		/* branch if no match  */
+	nop
+	bne	t1,zero,1f		/* double check for positive id   */
+	nop
+	/* We have a FPU. clear fcsr */
+	ctc1	zero, fcr31
+	j	2f			/* status register already correct  */
+	nop
+1:
+#ifdef _R3000
+	li	v0, SR_PE		/* reset parity error/NO cp1 usable */
+#endif
+
+#ifdef _R4000
+        li      v0,SR_DE 		/* clear ERL and disable FPA */
+#endif
+
+	mtc0	v0, C0_SR		/* reset status register */
+2:
+	la  	gp, _gp			
+
+	la	v0,_fbss 		/* clear bss before using it */
+	la	v1,end 			/* end of bss */
+3:	sw	zero,0(v0)
+	bltu	v0,v1,3b
+	add	v0,4 
+
+
+/************************************************************************
+**
+** 	Temporary Stack - needed to  handle stack saves until
+**			  memory size is determined and permanent stack set
+**
+**			  MUST be uncached to avoid confusion at cache
+**			       switching during memory sizing
+**
+*************************************************************************/
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack is aligned on a
+	 * double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 11f   /* Last three bits Zero, already aligned */
+	nop
+	add	v0, 4
+11:
+#endif
+
+	or	v0, K1BASE		/* switch to uncached */
+	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
+	sub	v1, v1, (4*4)		/* overhead */
+	move	sp, v1			/* set sp to top of stack */
+4:	sw	zero, 0(v0)  
+	bltu	v0, v1, 4b		/* clear out temp stack */
+	add	v0, 4 
+	
+	jal	init_exc_vecs		/* install exception handlers */ 
+	nop				/* MUST do before memory probes */
+
+	la	v0, 5f
+	li	v1, K1BASE		/* force into uncached space */
+	or	v0, v1			/* during memory/cache probes */
+	j	v0
+	nop
+5:
+	la	a0, sim_mem_cfg_struct
+	jal	sim_mem_cfg		/* Make SIM call to get mem size */
+	nop
+	la	a0, sim_mem_cfg_struct
+	lw	a0, 0(a0)		/* Get memory size from struct */
+#ifdef _R3000
+	jal	config_Icache
+	nop
+	jal	config_Dcache		/* determine size of D & I caches */
+	nop	
+#endif
+#ifdef _R4000
+	jal	config_cache		/* determine size of D & I caches */
+	nop
+#endif
+
+	move	v0, a0			/* mem_size */
+
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack (and hence v0
+	 * here) is aligned on a double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 12f   /* Last three bits Zero, already aligned */
+	nop
+	subu	v0, 4	/* mem_size was not aligned on doubleword bdry????*/
+12:
+#endif
+
+
+
+/**************************************************************************
+**
+**  Permanent Stack - now know top of memory, put permanent stack there	
+**
+***************************************************************************/ 
+
+	la	t2, _fbss		/* cache mode as linked */
+	and	t2, 0xF0000000		/* isolate segment */
+	la	t1, 6f
+	j	t1			/* back to original cache mode */
+	nop
+6:
+	or 	v0, t2			/* stack back to original cache mode */
+	addiu   v0,v0,-16		/* overhead */
+	move	sp, v0			/* now replace count w top of memory */
+	move	v1, v0
+	subu	v1, P_STACKSIZE 	/* clear requested stack size */
+
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+	bltu	v1,v0,7b
+	add	v1, 4 
+	.set	reorder
+
+#ifdef _R3000 
+	jal	flush_Icache	
+	jal	flush_Dcache		/* flush Data & Instruction caches */
+#endif
+#ifdef _R4000 
+	jal	flush_cache_nowrite	/* flush Data & Instruction caches */
+#endif
+
+
+
+/**************************************************************************
+**
+**	If this chip supports a Translation Lookaside Buffer, clear it
+**
+***************************************************************************/ 
+
+	.set	noreorder
+	mfc0	t1,  C0_SR		/* look at Status Register */
+	nop
+	.set 	reorder
+#ifdef _R3000
+	li	t2, SR_TS		/* TLB Shutdown bit */
+	and 	t1,t2      		/* TLB Shutdown if 1 */
+	bnez	t1, 8f			/* skip clearing if no TLB */	
+#endif
+
+#ifndef R4650
+	jal	init_tlb		/* clear the tlb */
+#endif
+
+
+/************************************************************************
+**
+**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**
+**  can SKIP if not necessary for application
+**
+************************************************************************/
+8:
+
+	jal	idtsim_init_sbrk
+	jal	idtsim_init_file
+/***********************  END I/O initialization **********************/
+
+
+	jal	main
+
+	jal	idtsim_promexit
+
+ENDFRAME(start)
+
+
+	.globl	sim_mem_cfg
+sim_mem_cfg:
+	.set noat
+	.set noreorder
+	li	AT, (0xbfc00000+((55)*8))
+	jr	AT
+	nop
+	.set at
+	.set reorder
diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c b/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c
new file mode 100644
index 0000000000..ecaff11004
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c
@@ -0,0 +1,30 @@
+/*  bsp_cleanup()
+ *
+ *  This routine normally is part of start.s and usually returns
+ *  control to a monitor.
+ *
+ *  INPUT:  NONE
+ *
+ *  OUTPUT: NONE
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  bspclean.c,v 1.2 1995/05/31 16:56:27 joel Exp
+ */
+#ifndef lint
+static char _sccsid[] = "@(#)bspclean.c 03/15/96     1.1\n";
+#endif
+
+
+#include <rtems.h>
+#include <bsp.h>
+
+void bsp_cleanup( void )
+{
+}
diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds b/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds
new file mode 100644
index 0000000000..cf2a80bf8d
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds
@@ -0,0 +1,15 @@
+-map
+-sec
+{
+  .text 0x80010000  :
+  .data  align(16)  :
+  .rodata :
+  .fini :
+#  .sdata :
+  .symtab :
+  .strtab :
+  .debug :
+#  .sbss :
+  .bss     align(8)  :
+  .init 0xbfc00000 :
+}
diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S
new file mode 100644
index 0000000000..66c1a4ecbc
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S
@@ -0,0 +1,938 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/
+
+/************************************************************************
+**
+**	idtmem.s - memory and cache functions
+**
+**	Copyright 1991 Integrated Device Technology, Inc.
+**	All Rights Reserved
+**
+**************************************************************************/
+
+/*
+ * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack 
+ * to set mem_size. 
+ */
+
+#include "iregdef.h"
+#include "idtcpu.h"  
+#include "idtmon.h"  
+#include "saunder.h"
+
+
+	.data
+mem_size:
+	.word	0	
+dcache_size:
+	.word 	0		
+icache_size:
+#if defined(CPU_R3000)
+	.word	MINCACHE	
+#endif
+#if defined(CPU_R4000)
+	.word	0
+#endif
+
+#if defined(CPU_R4000)
+	.data
+scache_size:
+	.word 	0
+icache_linesize:
+	.word	0
+dcache_linesize:
+	.word	0
+scache_linesize:
+	.word	0
+#endif
+
+
+		.text
+
+#if defined (CPU_R3000)
+#define CONFIGFRM ((2*4)+4)	
+
+/*************************************************************************
+**
+** Config_Dcache() -- determine size of Data cache 
+**
+**************************************************************************/
+
+FRAME(config_Dcache,sp, CONFIGFRM, ra)
+	.set	noreorder
+	subu	sp,CONFIGFRM
+	sw	ra,CONFIGFRM-4(sp)	/* save return address */
+	sw	s0,4*4(sp)		/* save s0 in first regsave slot */
+	mfc0	s0,C0_SR		/* save SR */
+	nop
+	mtc0	zero,C0_SR		/* disable interrupts */
+	.set	reorder
+	jal	_size_cache		/* returns Data cache size in v0 */
+	sw	v0, dcache_size		/* save it */
+	and 	s0, ~SR_PE		/* do not clear PE */
+	.set	noreorder
+	mtc0	s0,C0_SR		/* restore SR */
+	nop
+	.set	reorder
+	lw	s0, 4*4(sp)		/* restore s0 */
+	lw	ra,CONFIGFRM-4(sp)	/* restore ra */
+	addu	sp,CONFIGFRM		/* pop stack */
+	j	ra
+ENDFRAME(config_Dcache)
+ 
+
+/*************************************************************************
+**
+** Config_Icache() -- determine size of Instruction cache
+**		      MUST be run in uncached mode/handled in idt_csu.s
+**
+**************************************************************************/
+
+FRAME(config_Icache,sp, CONFIGFRM, ra)
+	.set	noreorder
+	subu	sp,CONFIGFRM
+	sw	ra,CONFIGFRM-4(sp)	/* save return address */
+	sw	s0,4*4(sp)		/* save s0 in first regsave slot */
+	mfc0	s0,C0_SR		/* save SR */
+	nop
+ 	mtc0	zero, C0_SR		/* disable interrupts */
+	li	v0,SR_SWC		/* swap caches/disable ints  */
+	mtc0	v0,C0_SR
+	nop
+	.set	reorder
+	jal	_size_cache		/* returns instruction cache size */
+	.set	noreorder
+	mtc0	zero,C0_SR		/* swap back caches */  
+	nop
+	and	s0,~SR_PE		/* do not inadvertantly clear PE */
+	mtc0	s0,C0_SR		/* restore SR */
+	nop
+	.set	reorder
+	sw	v0, icache_size		/* save it AFTER caches back */
+	lw	s0,4*4(sp)		/* restore s0 */
+	lw	ra,CONFIGFRM-4(sp)	/* restore ra */
+	addu	sp,CONFIGFRM		/* pop stack */
+	j	ra
+ENDFRAME(config_Icache)
+
+/************************************************************************
+**
+** _size_cache()
+** returns cache size in v0
+**
+************************************************************************/
+
+FRAME(_size_cache,sp,0,ra)
+	.set	noreorder
+	mfc0	t0,C0_SR		/* save current sr */
+	nop
+	and	t0,~SR_PE		/* do not inadvertently clear PE */
+	or	v0,t0,SR_ISC		/* isolate cache */
+	mtc0	v0,C0_SR
+	/*
+	 * First check if there is a cache there at all
+	 */
+	move	v0,zero
+	li	v1,0xa5a5a5a5		/* distinctive pattern */
+	sw	v1,K0BASE		/* try to write into cache */
+	lw	t1,K0BASE		/* try to read from cache */
+	nop
+	mfc0	t2,C0_SR
+	nop
+	.set	reorder
+	and	t2,SR_CM
+	bne	t2,zero,3f		/* cache miss, must be no cache */
+	bne	v1,t1,3f		/* data not equal -> no cache */
+	/*
+	 * Clear cache size boundries to known state.
+	 */
+	li	v0,MINCACHE
+1:
+	sw	zero,K0BASE(v0)
+	sll	v0,1
+	ble	v0,MAXCACHE,1b
+
+	li	v0,-1
+	sw	v0,K0BASE(zero)		/* store marker in cache */
+	li	v0,MINCACHE		/* MIN cache size */
+
+2:	lw	v1,K0BASE(v0)		/* Look for marker */
+	bne	v1,zero,3f		/* found marker */
+	sll	v0,1			/* cache size * 2 */
+	ble	v0,MAXCACHE,2b		/* keep looking */
+	move	v0,zero			/* must be no cache */
+	.set	noreorder
+3:	mtc0	t0,C0_SR		/* restore sr */
+	j	ra
+	nop
+ENDFRAME(_size_cache)
+	.set	reorder
+
+
+#define FLUSHFRM (2*4)
+
+/***************************************************************************
+**
+** flush_Dcache() -  flush entire Data cache
+**
+****************************************************************************/
+FRAME(flush_Dcache,sp,FLUSHFRM,ra)
+	lw      t2, dcache_size		
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	beq	t2,zero,_Dflush_done	/* no D cache, get out! */
+	nop
+	li	v0, SR_ISC		/* isolate cache */
+	mtc0	v0, C0_SR
+	nop
+	.set	reorder
+	li	t0,K0BASE		/* set loop registers  */
+	or	t1,t0,t2
+
+2:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bne	t0,t1,2b
+
+	.set	noreorder
+_Dflush_done:
+	mtc0	t3,C0_SR		/* restore Status Register */
+	.set	reorder
+	j	ra
+ENDFRAME(flush_Dcache)
+
+
+/***************************************************************************
+**
+** flush_Icache() -  flush entire Instruction cache
+**
+**	NOTE: Icache can only be flushed/cleared when uncached
+**	      Code forces into uncached memory regardless of calling mode
+**
+****************************************************************************/
+FRAME(flush_Icache,sp,FLUSHFRM,ra)
+	lw	t1,icache_size 
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	la	v0,1f
+	li	v1,K1BASE
+	or	v0,v1
+	j	v0			/* force into non-cached space */
+	nop
+1:
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	beq	t1,zero,_Iflush_done	/* no i-cache get out */
+	nop
+	li	v0,SR_ISC|SR_SWC	/* disable intr, isolate and swap */
+	mtc0	v0,C0_SR
+	li	t0,K0BASE
+	.set	reorder
+	or	t1,t0,t1
+
+1:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bne	t0,t1,1b
+	.set	noreorder
+_Iflush_done:
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	.set	reorder
+	j	ra
+ENDFRAME(flush_Icache)
+
+/**************************************************************************
+**
+** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
+**
+**      a0 = base address of portion to be cleared
+**      a1 = byte count of length
+**
+***************************************************************************/
+FRAME(clear_Dcache,sp,0,ra)
+
+	lw  	t2, dcache_size		/* Data cache size */
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	nop
+	nop
+	.set	reorder
+	/*
+	 * flush data cache
+	 */
+
+	.set	noreorder
+	nop
+	li	v0,SR_ISC		/* isolate data cache */
+	mtc0	v0,C0_SR
+	.set	reorder
+	bltu	t2,a1,1f		/* cache is smaller than region */
+	move	t2,a1
+1:	addu	t2,a0			/* ending address + 1 */
+	move	t0,a0
+
+1:	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bltu	t0,t2,1b
+
+	.set	noreorder
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	nop
+	.set	reorder
+	j	ra
+ENDFRAME(clear_Dcache)
+
+
+/**************************************************************************
+**
+** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
+**
+**      a0 = base address of portion to be cleared
+**      a1 = byte count of length
+**
+**	NOTE: Icache can only be flushed/cleared when uncached
+**	      Code forces into uncached memory regardless of calling mode
+**
+***************************************************************************/
+FRAME(clear_Icache,sp,0,ra)
+
+	lw      t1, icache_size		/* Instruction cache size */
+	/*
+	 * flush text cache
+	 */
+	.set	noreorder
+	mfc0	t3,C0_SR		/* save SR */
+	nop 
+	la	v0,1f
+	li	v1,K1BASE
+	or	v0,v1
+	j	v0			/* force into non-cached space */
+	nop
+1:
+	and	t3,~SR_PE		/* dont inadvertently clear PE */
+	nop
+	nop
+	li	v0,SR_ISC|SR_SWC	/* disable intr, isolate and swap */
+	mtc0	v0,C0_SR
+	.set	reorder
+	bltu	t1,a1,1f		/* cache is smaller than region */
+	move	t1,a1
+1:	addu	t1,a0			/* ending address + 1 */
+	move	t0,a0
+
+	sb	zero,0(t0)
+	sb	zero,4(t0)
+	sb	zero,8(t0)
+	sb	zero,12(t0)
+	sb	zero,16(t0)
+	sb	zero,20(t0)
+	sb	zero,24(t0)
+	addu	t0,32
+	sb	zero,-4(t0)
+	bltu	t0,t1,1b
+	.set	noreorder
+	mtc0	t3,C0_SR		/* un-isolate, enable interrupts */
+	nop
+	nop
+	nop				/* allow time for caches to swap */
+	.set	reorder
+	j	ra
+ENDFRAME(clear_Icache)
+
+
+/**************************************************************************
+**
+**  get_mem_conf - get memory configuration 
+**
+***************************************************************************/
+
+
+FRAME(get_mem_conf,sp,0,ra)
+
+	lw	t6, mem_size
+	sw	t6, 0(a0)
+	lw	t7, icache_size
+	sw	t7, 4(a0)
+	lw	t8, dcache_size
+	sw	t8, 8(a0) 
+	j	ra
+
+ENDFRAME(get_mem_conf)
+#endif /* defined CPU_R3000 */
+
+#if defined(CPU_R4000)
+#define LEAF(label)	FRAME(label,sp,0,ra)
+#define XLEAF(label) \
+	.globl label ; \
+label:
+#define END(label)	ENDFRAME(label)
+
+/*
+ * cacheop macro to automate cache operations
+ * first some helpers...
+ */
+#define _mincache(size, maxsize) \
+	bltu	size,maxsize,8f ;	\
+	move	size,maxsize ;		\
+8:
+
+#define _align(tmp, minaddr, maxaddr, linesize) \
+	subu	tmp,linesize,1 ;	\
+	not	tmp ;			\
+	and	minaddr,tmp ;		\
+	addu	maxaddr,-1 ;		\
+	and	maxaddr,tmp
+
+/* This is a bit of a hack really because it relies on minaddr=a0 */
+#define _doop1(op1) \
+	cache	op1,0(a0) 
+
+#define _doop2(op1, op2) \
+	cache	op1,0(a0) ;		\
+	cache	op2,0(a0) 
+
+/* specials for cache initialisation */
+#define _doop1lw1(op1) \
+	cache	op1,0(a0) ;		\
+	lw	zero,0(a0) ;		\
+	cache	op1,0(a0) 
+
+#define _doop121(op1,op2) \
+	cache	op1,0(a0) ;		\
+	nop;				\
+	cache	op2,0(a0) ;		\
+	nop;				\
+	cache	op1,0(a0) 
+
+#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
+	.set	noreorder ;		\
+7: 	_doop##tag##ops ;	 	\
+	bne     minaddr,maxaddr,7b ;	\
+	addu   	minaddr,linesize ;	\
+	.set	reorder
+
+/* finally the cache operation macros */
+#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
+	_mincache(n, cache_size);	\
+ 	blez	n,9f ;			\
+	addu	n,kva ;			\
+	_align(t1, kva, n, cache_linesize) ; \
+	_oploopn(kva, n, cache_linesize, tag, ops) ; \
+9:
+
+#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
+ 	blez	n,9f ;			\
+	addu	n,kva ;			\
+	_align(t1, kva, n, cache_linesize) ; \
+	_oploopn(kva, n, cache_linesize, tag, ops) ; \
+9:
+
+#define icacheop(kva, n, cache_size, cache_linesize, op) \
+	icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
+
+#define vcacheop(kva, n, cache_size, cache_linesize, op) \
+	vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
+
+	.text
+
+/*
+ * static void _size_cache()    R4000
+ * 
+ * Internal routine to determine cache sizes by looking at R4000 config
+ * register.  Sizes are returned in registers, as follows:
+ *	t2	icache size
+ *	t3	dcache size
+ *	t6	scache size
+ *	t4	icache line size
+ *	t5	dcache line size
+ *	t7	scache line size
+ */
+LEAF(_size_cache)
+	mfc0	t0,C0_CONFIG
+
+	and	t1,t0,CFG_ICMASK
+	srl	t1,CFG_ICSHIFT
+	li	t2,0x1000
+	sll	t2,t1
+
+	and	t1,t0,CFG_DCMASK
+	srl	t1,CFG_DCSHIFT
+	li	t3,0x1000
+	sll	t3,t1
+
+	li	t4,32
+	and	t1,t0,CFG_IB
+	bnez	t1,1f
+	li	t4,16
+1:	
+
+	li	t5,32
+	and	t1,t0,CFG_DB
+	bnez	t1,1f
+	li	t5,16
+1:	
+
+	move	t6,zero			# default to no scache
+	move	t7,zero			#
+
+	and	t1,t0,CFG_C_UNCACHED	# test config register
+	bnez	t1,1f			# no scache if uncached/non-coherent
+	
+	li	t6,0x100000		# assume 1Mb scache <<-NOTE
+	and	t1,t0,CFG_SBMASK
+	srl	t1,CFG_SBSHIFT
+	li	t7,16
+	sll	t7,t1
+1:	j	ra
+END(_size_cache)
+
+
+/*
+ * void config_cache()   R4000
+ * 
+ * Work out size of I, D & S caches, assuming they are already initialised.
+ */
+LEAF(config_cache)
+	lw	t0,icache_size
+	bgtz	t0,8f			# already known?
+	move	v0,ra
+	bal	_size_cache
+	move	ra,v0
+
+	sw	t2,icache_size
+	sw	t3,dcache_size
+	sw	t6,scache_size
+	sw	t4,icache_linesize
+	sw	t5,dcache_linesize
+	sw	t7,scache_linesize
+8:	j	ra
+END(config_cache)
+
+
+/*
+ * void _init_cache()   R4000
+ */
+LEAF(_init_cache)
+	/*
+ 	 * First work out the sizes
+	 */
+	move	v0,ra
+	bal	_size_cache
+	move	ra,v0
+	
+	/*
+	 * The caches may be in an indeterminate state,
+	 * so we force good parity into them by doing an
+	 * invalidate, load/fill, invalidate for each line.
+	 */
+
+	/* disable all i/u and cache exceptions */
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	or	v1,SR_DE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	/* assume bottom of RAM will generate good parity for the cache */
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t2		# icache_size
+	move	a3,t4		# icache_linesize
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
+
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t3		# dcache_size
+	move	a3,t5		# dcache_linesize
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
+
+	/* assume unified I & D in scache <<-NOTE */
+	blez	t6,1f
+	li	a0,PHYS_TO_K0(0)
+	move	a2,t6
+	move	a3,t7
+	move	a1,a2
+	icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
+
+1:	mtc0	v0,C0_SR
+	j	ra
+END(_init_cache)
+	
+
+/*
+ * void flush_cache (void)   R4000
+ *
+ * Flush and invalidate all caches
+ */
+LEAF(flush_cache)
+	/* secondary cacheops do all the work if present */
+	lw	a2,scache_size
+	blez	a2,1f
+	lw	a3,scache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
+	b	2f
+
+1:	
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+2:	j	ra
+END(flush_cache)
+	
+/*
+ * void flush_cache_nowrite (void)   R4000
+ *
+ * Invalidate all caches
+ */
+LEAF(flush_cache_nowrite)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+	li	a0,PHYS_TO_K0(0)
+	move	a1,a2
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(flush_cache_nowrite)
+	
+/*
+ * void clean_cache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in all caches
+ */
+LEAF(clean_cache)
+XLEAF(clear_cache)
+
+	/* secondary cacheops do all the work (if fitted) */
+	lw	a2,scache_size
+	blez	a2,1f
+	lw	a3,scache_linesize
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
+	b	2f
+
+1:	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+	/* save kva & n for subsequent loop */
+	move	t8,a0
+	move	t9,a1
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
+
+	lw	a2,dcache_size
+	lw	a3,dcache_linesize
+	/* restore kva & n */
+	move	a0,t8
+	move	a1,t9
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_cache)
+	
+/*
+ * void clean_dcache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in primary data cache
+ */
+LEAF(clean_dcache)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_dcache)
+	
+/*
+ * void clean_dcache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate indexed range in primary data cache
+ */
+LEAF(clean_dcache_indexed)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
+
+2:	j	ra
+END(clean_dcache_indexed)
+	
+/*
+ * void clean_dcache_nowrite (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate an address range in primary data cache
+ */
+LEAF(clean_dcache_nowrite)
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
+
+2:	j	ra
+END(clean_dcache_nowrite)
+	
+/*
+ * void clean_dcache_nowrite_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in primary data cache
+ */
+LEAF(clean_dcache_nowrite_indexed)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,dcache_size
+	blez	a2,2f
+	lw	a3,dcache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(clean_dcache_nowrite_indexed)
+	
+/*
+ * void clean_icache (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate address range in primary instruction cache
+ */
+LEAF(clean_icache)
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
+
+2:	j	ra
+END(clean_icache)
+	
+/*
+ * void clean_icache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in primary instruction cache
+ */
+LEAF(clean_icache_indexed)
+	lw	a2,icache_size
+	blez	a2,2f
+	lw	a3,icache_linesize
+
+#ifdef CPU_ORION
+	srl	a2,1			# do one set (half cache) at a time
+	move	t8,a0			# save kva & n
+	move	t9,a1
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+	addu	a0,t8,a2		# do next set
+	move	a1,t9			# restore n
+#endif
+	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
+
+2:	j	ra
+END(clean_icache_indexed)
+	
+
+
+/*
+ * void clean_scache (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate address range in secondary cache
+ */
+LEAF(clean_scache)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
+
+2:	j	ra
+END(clean_scache)
+	
+/*
+ * void clean_scache_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Writeback and invalidate indexed range in secondary cache
+ */
+LEAF(clean_scache_indexed)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
+
+2:	j	ra
+END(clean_scache_indexed)
+	
+/*
+ * void clean_scache_nowrite (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate an address range in secondary cache
+ */
+LEAF(clean_scache_nowrite)
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
+
+2:	j	ra
+END(clean_scache_nowrite)
+	
+/*
+ * void clean_scache_nowrite_indexed (unsigned kva, size_t n)   R4000
+ *
+ * Invalidate indexed range in secondary cache
+ */
+LEAF(clean_scache_nowrite_indexed)
+	mfc0	v0,C0_SR
+	and	v1,v0,~SR_IE
+	mtc0	v1,C0_SR
+
+	mtc0	zero,C0_TAGLO
+	mtc0	zero,C0_TAGHI
+
+	lw	a2,scache_size
+	blez	a2,2f
+	lw	a3,scache_linesize
+
+	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
+
+2:	mtc0	v0,C0_SR
+	j	ra
+END(clean_scache_nowrite_indexed)
+	
+/**************************************************************************
+**
+**  get_mem_conf - get memory configuration  R4000
+**
+***************************************************************************/
+
+
+FRAME(get_mem_conf,sp,0,ra)
+
+	lw	t6, mem_size
+	sw	t6, 0(a0)
+	lw	t7, icache_size
+	sw	t7, 4(a0)
+	lw	t8, dcache_size
+	sw	t8, 8(a0) 
+	lw	t7, scache_size
+	sw	t7, 12(a0) 
+	j	ra
+
+ENDFRAME(get_mem_conf)
+
+#endif /* defined(CPU_R4000) */
+
+/*
+ * void set_mem_size (mem_size) 
+ *
+ * config_memory()'s memory size gets written into mem_size here.
+ * Now we don't need to call config_cache() with memory size - New to IDTC6.0
+ */
+FRAME(set_memory_size,sp,0,ra)
+	sw	a0, mem_size
+	j	ra
+ENDFRAME(set_memory_size)
+
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds b/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds
new file mode 100644
index 0000000000..e9d0566a12
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds
@@ -0,0 +1,69 @@
+/* @(#)linkcmds       04/08/96     1.2 */
+OUTPUT_FORMAT("elf32-bigmips")
+OUTPUT_ARCH(mips)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+_DYNAMIC_LINK = 0;
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text 0x80030000  :				/* */
+/*  .text 0xa0020000  :				/* */
+/*  .text 0x00020000  :				/* */
+  {
+    _ftext = . ;
+    *(.text)
+    CREATE_OBJECT_SYMBOLS
+    _etext = .;
+  }
+  .init    ALIGN(8)  : { *(.init)    } =0
+  .fini    ALIGN(8)  : { *(.fini)    } =0
+  .ctors   ALIGN(8)  : { *(.ctors)   }
+  .dtors   ALIGN(8)  : { *(.dtors)   }
+  .rodata  ALIGN(8)  : { *(.rodata)  }
+  .rodata1 ALIGN(8)  :
+    {
+      *(.rodata1)
+      . = ALIGN(8);
+    }
+  .reginfo . : { *(.reginfo) }
+  /* also: .hash .dynsym .dynstr .plt(if r/o) .rel.got */
+  /* Read-write section, merged into data segment: */
+  .data  ALIGN(16)  :
+  {
+    _fdata = . ;
+    *(.data)
+    CONSTRUCTORS
+  }
+  .data1 ALIGN(8)  : { *(.data1) }
+  _gp = . + 0x8000;
+  .lit8 . : { *(.lit8) }
+  .lit4 . : { *(.lit4) }
+  /* also (before uninitialized portion): .dynamic .got .plt(if r/w)
+     (or does .dynamic go into its own segment?) */
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   ALIGN(8)  : { *(.sdata) }
+  _edata  =  .;
+  __bss_start = ALIGN(8);
+  _fbss = .;
+  .sbss    ALIGN(8)  : { *(.sbss) *(.scommon) }
+  .bss     ALIGN(8)  :
+  {
+   *(.bss)
+   *(COMMON)
+   _end = . ;
+   end = . ;
+  }
+  /* Debug sections.  These should never be loadable, but they must have
+     zero addresses for the debuggers to work correctly.  */
+  .line			0 : { *(.line)			}
+  .debug		0 : { *(.debug)			}
+  .debug_sfnames	0 : { *(.debug_sfnames)		}
+  .debug_srcinfo	0 : { *(.debug_srcinfo)		}
+  .debug_macinfo	0 : { *(.debug_macinfo)		}
+  .debug_pubnames	0 : { *(.debug_pubnames)	}
+  .debug_aranges	0 : { *(.debug_aranges)		}
+}
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c b/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c
new file mode 100644
index 0000000000..1c6b581296
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c
@@ -0,0 +1,51 @@
+/*  set_vector
+ *
+ *  This routine installs an interrupt vector on the target Board/CPU.
+ *  This routine is allowed to be as board dependent as necessary.
+ *
+ *  INPUT:
+ *    handler - interrupt handler entry point
+ *    vector  - vector number
+ *    type    - 0 indicates raw hardware connect
+ *              1 indicates RTEMS interrupt connect
+ *
+ *  RETURNS:
+ *    address of previous interrupt handler
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  setvec.c,v 1.2 1995/05/31 16:56:35 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)setvec.c 04/25/96     1.2\n";
+#endif
+
+#include <rtems.h>
+#include <bsp.h>
+
+#include <excepthdr.h>
+
+mips_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+)
+{
+  mips_isr_entry previous_isr;
+
+  if ( type )
+    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
+  else {
+    /* XXX: install non-RTEMS ISR as "raw" interupt */
+    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
+  }
+  return previous_isr;
+}
+
diff --git a/c/src/lib/libbsp/mips64orion/p4000/times b/c/src/lib/libbsp/mips64orion/p4000/times
new file mode 100644
index 0000000000..6a3dbfe1fb
--- /dev/null
+++ b/c/src/lib/libbsp/mips64orion/p4000/times
@@ -0,0 +1,200 @@
+#
+#  Timing Test Suite Results for the NO_BSP
+#
+#  NOTE: This is just a template.  The times are irrelevant since this BSP
+#        can only be compiled -- not executed.
+#
+#  times,v 1.2 1995/12/07 15:44:23 joel Exp
+#
+# @(#)times        08/01/96     1.4
+
+NOTE:  To obtain the execution time in microseconds, divide the number of
+       cycles by the clock speed.  For example, if rtems_semaphore create
+       is reported to be 1164 cycles, then at 66 Mhz it takes 17.64
+       microseconds or 8.75 microseconds at 133 Mhz.
+
+Board: Algorithmics P4000i 
+CPU: IDT 4650
+Clock Speed: 100MHz
+Memory Configuration: SRAM, DRAM, cache, etc
+Wait States:
+
+Times Reported in: cycles
+Timer Source: on-CPU cycle counter
+
+Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types
+Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types
+
+#                          DESCRIPTION                                 A    B
+== =================================================================  ==== ====
+ 1 rtems_semaphore_create                                              788  759
+   rtems_semaphore_delete                                              903  945
+   rtems_semaphore_obtain: available                                   119  119
+   rtems_semaphore_obtain: not available -- NO_WAIT                    118  118
+   rtems_semaphore_release: no waiting tasks                           127  127
+
+ 2 rtems_semaphore_obtain: not available -- caller blocks              842  840
+
+ 3 rtems_semaphore_release: task readied -- preempts caller            777  751
+
+ 4 rtems_task_restart: blocked task -- preempts caller                1611 1595
+   rtems_task_restart: ready task -- preempts caller                  1253 1395
+   rtems_semaphore_release: task readied -- returns to caller          365  345
+   rtems_task_create                                                   798  797
+   rtems_task_start                                                    464  460
+   rtems_task_restart: suspended task -- returns to caller             517  517
+   rtems_task_delete: suspended task                                   529  595
+   rtems_task_restart: ready task -- returns to caller                 527  525
+   rtems_task_restart: blocked task -- returns to caller               707  684
+   rtems_task_delete: blocked task                                     609  675
+
+ 5 rtems_task_suspend: calling task                                    549  549
+   rtems_task_resume: task readied -- preempts caller                  702  699
+
+ 6 rtems_task_restart: calling task                                    291  291
+   rtems_task_suspend: returns to caller                               195  194
+   rtems_task_resume: task readied -- returns to caller                198  198
+   rtems_task_delete: ready task                                       734  736
+
+ 7 rtems_task_restart: suspended task -- preempts caller              1049  990
+
+ 8 rtems_task_set_priority: obtain current priority                     94   94
+   rtems_task_set_priority: returns to caller                          418  355
+   rtems_task_mode: obtain current mode                                 44   43
+   rtems_task_mode: no reschedule                                        0   49
+   rtems_task_mode: reschedule -- returns to caller                      0  232 
+   rtems_task_mode: reschedule -- preempts caller                        0  687
+   rtems_task_set_note                                                   0  101
+   rtems_task_get_note                                                   0  103
+   rtems_clock_set                                                       0  237
+   rtems_clock_get                                                       0   16
+
+ 9 rtems_message_queue_create                                         3583 3432
+   rtems_message_queue_send: no waiting tasks                          252  252
+   rtems_message_queue_urgent: no waiting tasks                        252  252
+   rtems_message_queue_receive: available                              207  207
+   rtems_message_queue_flush: no messages flushed                       95   96
+   rtems_message_queue_flush: messages flushed                         110  110
+   rtems_message_queue_delete                                         1044 1111
+
+10 rtems_message_queue_receive: not available -- NO_WAIT               132  131
+   rtems_message_queue_receive: not available -- caller blocks         884  892
+
+11 rtems_message_queue_send: task readied -- preempts caller           397  817 
+
+12 rtems_message_queue_send: task readied -- returns to caller         397  397
+
+13 rtems_message_queue_urgent: task readied -- preempts caller         816  817
+
+14 rtems_message_queue_urgent: task readied -- returns to caller       397  398
+
+15 rtems_event_receive: obtain current events                            5    5
+   rtems_event_receive: not available -- NO_WAIT                        99   99
+   rtems_event_receive: not available -- caller blocks                 689  689
+   rtems_event_send: no task readied                                   123  123
+   rtems_event_receive: available                                      326  349
+   rtems_event_send: task readied -- returns to caller                 333  429
+
+16 rtems_event_send: task readied -- preempts caller                   843  838
+
+17 rtems_task_set_priority: preempts caller                           1002  991
+
+18 rtems_task_delete: calling task                                    1171 1157
+
+19 rtems_signal_catch                                                    0 1306
+   rtems_signal_send: returns to caller                                  0 1019
+   rtems_signal_send: signal to self                                     0  496
+   exit ASR overhead: returns to calling task                            0  120
+   exit ASR overhead: returns to preempting task                         0   73
+
+20 rtems_partition_create                                             1293 1306
+   rtems_region_create                                                1010 1019
+   rtems_partition_get_buffer: available                               481  496
+   rtems_partition_get_buffer: not available                           120  120
+   rtems_partition_return_buffer                                       587  460
+   rtems_partition_delete                                              379  320
+   rtems_region_get_segment: available                                 179  179
+   rtems_region_get_segment: not available -- NO_WAIT                  349  293
+   rtems_region_return_segment: no waiting tasks                       335  322
+   rtems_region_get_segment: not available -- caller blocks           1603 1496
+   rtems_region_return_segment: task readied -- preempts caller       1616 1533
+   rtems_region_return_segment: task readied -- returns to caller      940  939
+   rtems_region_delete                                                 301  348
+   rtems_io_initialize                                                   9   10
+   rtems_io_open                                                         6    6
+   rtems_io_close                                                        6    6
+   rtems_io_read                                                         6    6
+   rtems_io_write                                                        6    5
+   rtems_io_control                                                      6    6
+
+21 rtems_task_ident                                                   1057 1058
+   rtems_message_queue_ident                                           963  963
+   rtems_semaphore_ident                                              1137 1136
+   rtems_partition_ident                                               962  961
+   rtems_region_ident                                                  923  924
+   rtems_port_ident                                                    918  917
+   rtems_timer_ident                                                   942  941
+   rtems_rate_monotonic_ident                                          924  925
+
+22 rtems_message_queue_broadcast: task readied -- returns to caller   1084 1095
+   rtems_message_queue_broadcast: no waiting tasks                     147  148
+   rtems_message_queue_broadcast: task readied -- preempts caller     1305 1268
+
+23 rtems_timer_create                                                  202  201
+   rtems_timer_fire_after: inactive                                    261  261
+   rtems_timer_fire_after: active                                      271  269
+   rtems_timer_cancel: active                                          142  141
+   rtems_timer_cancel: inactive                                        122  124
+   rtems_timer_reset: inactive                                         222  222
+   rtems_timer_reset: active                                           246  245
+   rtems_timer_fire_when: inactive                                     312  311
+   rtems_timer_fire_when: active                                       358  358
+   rtems_timer_delete: active                                          263  263
+   rtems_timer_delete: inactive                                        247  247
+   rtems_task_wake_when                                                833  831
+
+24 rtems_task_wake_after: yield -- returns to caller                    99   98
+   rtems_task_wake_after: yields -- preempts caller                    479  478
+
+25 rtems_clock_tick                                                    313  318
+
+26 _ISR_Disable                                                         64   57
+   _ISR_Flash                                                           51   36
+   _ISR_Enable                                                          31   18
+   _Thread_Disable_dispatch                                             53   37
+   _Thread_Enable_dispatch                                             260  233
+   _Thread_Set_state                                                   446  463
+   _Thread_Disptach (NO FP)                                            839  801
+   context switch: no floating point contexts                          673  653
+   context switch: self                                                156  162
+   context switch: to another task                                      84   70
+   context switch: restore 1st FP task                                1030 1013
+   fp context switch: save idle, restore idle                          969  948
+   fp context switch: save idle, restore initialized                   275  267
+   fp context switch: save initialized, restore initialized            319  292
+   _Thread_Resume                                                      512  480
+   _Thread_Unblock                                                     121  139
+   _Thread_Ready                                                       199  203
+   _Thread_Get                                                          27   27
+   _Semaphore_Get                                                       20   21
+   _Thread_Get: invalid id                                               5    5
+
+27 interrupt entry overhead: returns to interrupted task                 0    0
+   interrupt exit overhead: returns to interrupted task                 27   41
+   interrupt entry overhead: returns to nested interrupt                 0    0
+   interrupt exit overhead: returns to nested interrupt                  0    0
+   interrupt entry overhead: returns to preempting task                  0    0
+   interrupt exit overhead: returns to preempting task                   0    0
+
+28 rtems_port_create                                                   574  560
+   rtems_port_external_to_internal                                      87   87
+   rtems_port_internal_to_external                                      86   86
+   rtems_port_delete                                                   395  353
+
+29 rtems_rate_monotonic_create                                         621  633
+   rtems_rate_monotonic_period: initiate period -- returns to caller   773  694
+   rtems_rate_monotonic_period: obtain status                          295  284
+   rtems_rate_monotonic_cancel                                         408  451
+   rtems_rate_monotonic_delete: inactive                               453  471
+   rtems_rate_monotonic_delete: active                                 332  336
+   rtems_rate_monotonic_period: conclude periods -- caller blocks      664  686
diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c
new file mode 100644
index 0000000000..9677a02b47
--- /dev/null
+++ b/c/src/lib/libcpu/mips/clock/ckinit.c
@@ -0,0 +1,245 @@
+
+/*  ckinit.c
+ *
+ *  This file contains the clock driver initialization for the IDT 4650.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  ckinit.c,v 1.5 1995/10/30 21:53:23 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)ckinit.c 08/20/96     1.3\n";
+#endif
+
+#include <stdlib.h>
+
+#include <rtems.h>
+#include <rtems/libio.h>
+#include <bsp.h>
+
+#include <excepthdr.h>
+
+#include "clock.h"
+
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
+
+void Clock_exit( void );
+rtems_isr Clock_isr( rtems_vector_number vector );
+
+
+/*
+ *  The interrupt vector number associated with the clock tick device
+ *  driver.
+ */
+
+#define CLOCK_VECTOR_MASK    EXT_INT5
+#define CLOCK_VECTOR         0x7
+
+/*
+ *  Clock_driver_ticks is a monotonically increasing counter of the
+ *  number of clock ticks since the driver was initialized.
+ */
+
+volatile rtems_unsigned32 Clock_driver_ticks;
+
+/*
+ *  Clock_isrs is the number of clock ISRs until the next invocation of
+ *  the RTEMS clock tick routine.  The clock tick device driver
+ *  gets an interrupt once a millisecond and counts down until the
+ *  length of time between the user configured microseconds per tick
+ *  has passed.
+ */
+
+rtems_unsigned32 Clock_isrs;              /* ISRs until next tick */
+
+/*
+ * These are set by clock driver during its init
+ */
+ 
+rtems_device_major_number rtems_clock_major = ~0;
+rtems_device_minor_number rtems_clock_minor;
+
+/*
+ *  The previous ISR on this clock tick interrupt vector.
+ */
+
+rtems_isr_entry  Old_ticker;
+
+void Clock_exit( void );
+
+static unsigned32 mips_timer_rate = 0;
+
+/*
+ *  Isr Handler
+ */
+
+rtems_isr Clock_isr(
+  rtems_vector_number vector
+)
+{
+/*
+ * bump the number of clock driver ticks since initialization
+ *
+ * determine if it is time to announce the passing of tick as configured
+ * to RTEMS through the rtems_clock_tick directive
+ *
+ * perform any timer dependent tasks
+ */
+
+  /* refresh the internal CPU timer */
+  mips_set_timer( mips_timer_rate );
+
+  Clock_driver_ticks += 1;
+
+  rtems_clock_tick();
+}
+
+/* User callback shell (set from Clock_Control) */
+static void (*user_callback)(void);
+
+rtems_isr User_Clock_isr(
+  rtems_vector_number vector
+)
+{
+   /* refresh the internal CPU timer */
+   mips_set_timer( mips_timer_rate );
+
+   if (user_callback)
+      user_callback();
+}
+
+/*
+ *  Install_clock
+ *
+ *  Install a clock tick handleR and reprograms the chip.  This
+ *  is used to initially establish the clock tick.
+ */
+
+void Install_clock(
+  rtems_isr_entry clock_isr
+)
+{
+  /*
+   *  Initialize the clock tick device driver variables
+   */
+
+  Clock_driver_ticks = 0;
+  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
+
+  /*
+   *  If ticks_per_timeslice is configured as non-zero, then the user
+   *  wants a clock tick.
+   */
+
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+    Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
+    /*
+     *  Hardware specific initialize goes here
+     */
+
+    mips_timer_rate = BSP_Configuration.microseconds_per_tick * CLOCKS_PER_MICROSECOND;
+    mips_set_timer( mips_timer_rate );
+    enable_int(CLOCK_VECTOR_MASK);
+  }
+
+  /*
+   *  Schedule the clock cleanup routine to execute if the application exits.
+   */
+
+  atexit( Clock_exit );
+}
+
+/*
+ *  Clean up before the application exits
+ */
+
+void Clock_exit( void )
+{
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+
+    /* mips: turn off the timer interrupts */
+    disable_int(CLOCK_VECTOR_MASK);
+
+  }
+}
+
+/*
+ *  Clock_initialize
+ *
+ *  Device driver entry point for clock tick driver initialization.
+ */
+
+rtems_device_driver Clock_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  Install_clock( Clock_isr );
+ 
+  /*
+   * make major/minor avail to others such as shared memory driver
+   */
+ 
+  rtems_clock_major = major;
+  rtems_clock_minor = minor;
+ 
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_device_driver Clock_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+    rtems_unsigned32 isrlevel;
+    rtems_libio_ioctl_args_t *args = pargp;
+ 
+    if (args == 0)
+        goto done;
+ 
+    /*
+     * This is hokey, but until we get a defined interface
+     * to do this, it will just be this simple...
+     */
+ 
+    if (args->command == rtems_build_name('I', 'S', 'R', ' '))
+    {
+        Clock_isr(CLOCK_VECTOR);
+    }
+    else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
+    {
+      rtems_interrupt_disable( isrlevel );
+      user_callback = (void (*)(void))args->buffer;
+      (void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 );
+      rtems_interrupt_enable( isrlevel );
+    }
+ 
+done:
+    return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libcpu/mips/clock/clock.S b/c/src/lib/libcpu/mips/clock/clock.S
new file mode 100644
index 0000000000..a41edf5ea5
--- /dev/null
+++ b/c/src/lib/libcpu/mips/clock/clock.S
@@ -0,0 +1,44 @@
+/*  clock.s 
+ *
+ *  This file contains the assembly code for the IDT 4650 clock driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+/* @(#)clock.S       08/20/96     1.2 */
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+FRAME(mips_set_timer,sp,0,ra)
+	.set noreorder
+        mfc0 t0,C0_COUNT
+        nop
+        addu t0,a0,t0
+        mtc0 t0,C0_COMPARE
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_set_timer)
+
+FRAME(mips_get_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_get_timer)
diff --git a/c/src/lib/libcpu/mips/clock/clock.h b/c/src/lib/libcpu/mips/clock/clock.h
new file mode 100644
index 0000000000..19bc7f6bfe
--- /dev/null
+++ b/c/src/lib/libcpu/mips/clock/clock.h
@@ -0,0 +1,24 @@
+/*  clock.s
+ *
+ *  This file contains the assembly code for the IDT 4650 clock driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+
+/* @(#)clock.h       08/20/96     1.2 */
+
+extern void mips_set_timer( unsigned32 timer_clock_interval );
diff --git a/c/src/lib/libcpu/mips/timer/gettime.S b/c/src/lib/libcpu/mips/timer/gettime.S
new file mode 100644
index 0000000000..2c97c6e66e
--- /dev/null
+++ b/c/src/lib/libcpu/mips/timer/gettime.S
@@ -0,0 +1,34 @@
+/*  gettime.s
+ *
+ *  This file contains the assembly code for the IDT 4650 timer driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+
+/* @(#)gettime.S       08/20/96     1.2 */
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+FRAME(mips_read_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_read_timer)
diff --git a/c/src/lib/libcpu/mips/timer/timer.c b/c/src/lib/libcpu/mips/timer/timer.c
new file mode 100644
index 0000000000..a141232229
--- /dev/null
+++ b/c/src/lib/libcpu/mips/timer/timer.c
@@ -0,0 +1,136 @@
+/*  timer.c
+ *
+ *  This file contains the initialization code for the IDT 4650 timer driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c
+ *
+ *  This file manages the benchmark timer used by the RTEMS Timing Test
+ *  Suite.  Each measured time period is demarcated by calls to
+ *  Timer_initialize() and Read_timer().  Read_timer() usually returns
+ *  the number of microseconds since Timer_initialize() exitted.
+ *
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  timer.c,v 1.2 1995/05/31 16:56:39 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)timer.c 08/20/96     1.5\n";
+#endif
+
+#include <rtems.h>
+#include <bsp.h>
+
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ )
+#define TIMER_MAX_VALUE 0xffffffff
+
+extern unsigned32 mips_read_timer( void );
+
+static rtems_boolean Timer_driver_Find_average_overhead;
+static unsigned32 Timer_initial_value = 0;
+
+void Timer_initialize( void )
+{
+   Timer_initial_value = mips_read_timer();
+  /*
+   *  Somehow start the timer
+   */
+
+  /* Timer on 4650 is always running */
+}
+
+/*
+ *  The following controls the behavior of Read_timer().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      8  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in cycles. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+int Read_timer( void )
+{
+  unsigned64 clicks;
+  unsigned32 total;
+
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+  clicks = mips_read_timer();   /* XXX: read some HW here */
+  if (clicks < Timer_initial_value)
+  {
+      clicks += TIMER_MAX_VALUE;
+  }
+  clicks -= Timer_initial_value;
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+#if 0 /* leave total in number of cycles */
+   total = clicks / CLOCKS_PER_MICROSECOND;
+#else
+   total = clicks;
+#endif
+
+  if ( Timer_driver_Find_average_overhead == 1 )
+    return total;          /* in # cycles units */
+  else {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  leave total in cycles
+   */
+      return (total - AVG_OVERHEAD);
+    }
+}
+
+/*
+ *  Empty function call used in loops to measure basic cost of looping
+ *  in Timing Test Suite.
+ */
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
+
diff --git a/c/src/lib/libcpu/mips64orion/clock/ckinit.c b/c/src/lib/libcpu/mips64orion/clock/ckinit.c
new file mode 100644
index 0000000000..9677a02b47
--- /dev/null
+++ b/c/src/lib/libcpu/mips64orion/clock/ckinit.c
@@ -0,0 +1,245 @@
+
+/*  ckinit.c
+ *
+ *  This file contains the clock driver initialization for the IDT 4650.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c:
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  ckinit.c,v 1.5 1995/10/30 21:53:23 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)ckinit.c 08/20/96     1.3\n";
+#endif
+
+#include <stdlib.h>
+
+#include <rtems.h>
+#include <rtems/libio.h>
+#include <bsp.h>
+
+#include <excepthdr.h>
+
+#include "clock.h"
+
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
+
+void Clock_exit( void );
+rtems_isr Clock_isr( rtems_vector_number vector );
+
+
+/*
+ *  The interrupt vector number associated with the clock tick device
+ *  driver.
+ */
+
+#define CLOCK_VECTOR_MASK    EXT_INT5
+#define CLOCK_VECTOR         0x7
+
+/*
+ *  Clock_driver_ticks is a monotonically increasing counter of the
+ *  number of clock ticks since the driver was initialized.
+ */
+
+volatile rtems_unsigned32 Clock_driver_ticks;
+
+/*
+ *  Clock_isrs is the number of clock ISRs until the next invocation of
+ *  the RTEMS clock tick routine.  The clock tick device driver
+ *  gets an interrupt once a millisecond and counts down until the
+ *  length of time between the user configured microseconds per tick
+ *  has passed.
+ */
+
+rtems_unsigned32 Clock_isrs;              /* ISRs until next tick */
+
+/*
+ * These are set by clock driver during its init
+ */
+ 
+rtems_device_major_number rtems_clock_major = ~0;
+rtems_device_minor_number rtems_clock_minor;
+
+/*
+ *  The previous ISR on this clock tick interrupt vector.
+ */
+
+rtems_isr_entry  Old_ticker;
+
+void Clock_exit( void );
+
+static unsigned32 mips_timer_rate = 0;
+
+/*
+ *  Isr Handler
+ */
+
+rtems_isr Clock_isr(
+  rtems_vector_number vector
+)
+{
+/*
+ * bump the number of clock driver ticks since initialization
+ *
+ * determine if it is time to announce the passing of tick as configured
+ * to RTEMS through the rtems_clock_tick directive
+ *
+ * perform any timer dependent tasks
+ */
+
+  /* refresh the internal CPU timer */
+  mips_set_timer( mips_timer_rate );
+
+  Clock_driver_ticks += 1;
+
+  rtems_clock_tick();
+}
+
+/* User callback shell (set from Clock_Control) */
+static void (*user_callback)(void);
+
+rtems_isr User_Clock_isr(
+  rtems_vector_number vector
+)
+{
+   /* refresh the internal CPU timer */
+   mips_set_timer( mips_timer_rate );
+
+   if (user_callback)
+      user_callback();
+}
+
+/*
+ *  Install_clock
+ *
+ *  Install a clock tick handleR and reprograms the chip.  This
+ *  is used to initially establish the clock tick.
+ */
+
+void Install_clock(
+  rtems_isr_entry clock_isr
+)
+{
+  /*
+   *  Initialize the clock tick device driver variables
+   */
+
+  Clock_driver_ticks = 0;
+  Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
+
+  /*
+   *  If ticks_per_timeslice is configured as non-zero, then the user
+   *  wants a clock tick.
+   */
+
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+    Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
+    /*
+     *  Hardware specific initialize goes here
+     */
+
+    mips_timer_rate = BSP_Configuration.microseconds_per_tick * CLOCKS_PER_MICROSECOND;
+    mips_set_timer( mips_timer_rate );
+    enable_int(CLOCK_VECTOR_MASK);
+  }
+
+  /*
+   *  Schedule the clock cleanup routine to execute if the application exits.
+   */
+
+  atexit( Clock_exit );
+}
+
+/*
+ *  Clean up before the application exits
+ */
+
+void Clock_exit( void )
+{
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+
+    /* mips: turn off the timer interrupts */
+    disable_int(CLOCK_VECTOR_MASK);
+
+  }
+}
+
+/*
+ *  Clock_initialize
+ *
+ *  Device driver entry point for clock tick driver initialization.
+ */
+
+rtems_device_driver Clock_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  Install_clock( Clock_isr );
+ 
+  /*
+   * make major/minor avail to others such as shared memory driver
+   */
+ 
+  rtems_clock_major = major;
+  rtems_clock_minor = minor;
+ 
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_device_driver Clock_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+    rtems_unsigned32 isrlevel;
+    rtems_libio_ioctl_args_t *args = pargp;
+ 
+    if (args == 0)
+        goto done;
+ 
+    /*
+     * This is hokey, but until we get a defined interface
+     * to do this, it will just be this simple...
+     */
+ 
+    if (args->command == rtems_build_name('I', 'S', 'R', ' '))
+    {
+        Clock_isr(CLOCK_VECTOR);
+    }
+    else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
+    {
+      rtems_interrupt_disable( isrlevel );
+      user_callback = (void (*)(void))args->buffer;
+      (void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 );
+      rtems_interrupt_enable( isrlevel );
+    }
+ 
+done:
+    return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libcpu/mips64orion/clock/clock.S b/c/src/lib/libcpu/mips64orion/clock/clock.S
new file mode 100644
index 0000000000..a41edf5ea5
--- /dev/null
+++ b/c/src/lib/libcpu/mips64orion/clock/clock.S
@@ -0,0 +1,44 @@
+/*  clock.s 
+ *
+ *  This file contains the assembly code for the IDT 4650 clock driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+/* @(#)clock.S       08/20/96     1.2 */
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+FRAME(mips_set_timer,sp,0,ra)
+	.set noreorder
+        mfc0 t0,C0_COUNT
+        nop
+        addu t0,a0,t0
+        mtc0 t0,C0_COMPARE
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_set_timer)
+
+FRAME(mips_get_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_get_timer)
diff --git a/c/src/lib/libcpu/mips64orion/clock/clock.h b/c/src/lib/libcpu/mips64orion/clock/clock.h
new file mode 100644
index 0000000000..19bc7f6bfe
--- /dev/null
+++ b/c/src/lib/libcpu/mips64orion/clock/clock.h
@@ -0,0 +1,24 @@
+/*  clock.s
+ *
+ *  This file contains the assembly code for the IDT 4650 clock driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+
+/* @(#)clock.h       08/20/96     1.2 */
+
+extern void mips_set_timer( unsigned32 timer_clock_interval );
diff --git a/c/src/lib/libcpu/mips64orion/timer/gettime.S b/c/src/lib/libcpu/mips64orion/timer/gettime.S
new file mode 100644
index 0000000000..2c97c6e66e
--- /dev/null
+++ b/c/src/lib/libcpu/mips64orion/timer/gettime.S
@@ -0,0 +1,34 @@
+/*  gettime.s
+ *
+ *  This file contains the assembly code for the IDT 4650 timer driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ */
+
+/* @(#)gettime.S       08/20/96     1.2 */
+
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+FRAME(mips_read_timer,sp,0,ra)
+	.set noreorder
+        mfc0 v0,C0_COUNT
+        nop
+        j ra
+	.set reorder
+ENDFRAME(mips_read_timer)
diff --git a/c/src/lib/libcpu/mips64orion/timer/timer.c b/c/src/lib/libcpu/mips64orion/timer/timer.c
new file mode 100644
index 0000000000..a141232229
--- /dev/null
+++ b/c/src/lib/libcpu/mips64orion/timer/timer.c
@@ -0,0 +1,136 @@
+/*  timer.c
+ *
+ *  This file contains the initialization code for the IDT 4650 timer driver.
+ *
+ *  Author:     Craig Lebakken <craigl@transition.com>
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c
+ *
+ *  This file manages the benchmark timer used by the RTEMS Timing Test
+ *  Suite.  Each measured time period is demarcated by calls to
+ *  Timer_initialize() and Read_timer().  Read_timer() usually returns
+ *  the number of microseconds since Timer_initialize() exitted.
+ *
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  timer.c,v 1.2 1995/05/31 16:56:39 joel Exp
+ */
+
+#ifndef lint
+static char _sccsid[] = "@(#)timer.c 08/20/96     1.5\n";
+#endif
+
+#include <rtems.h>
+#include <bsp.h>
+
+#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ )
+#define TIMER_MAX_VALUE 0xffffffff
+
+extern unsigned32 mips_read_timer( void );
+
+static rtems_boolean Timer_driver_Find_average_overhead;
+static unsigned32 Timer_initial_value = 0;
+
+void Timer_initialize( void )
+{
+   Timer_initial_value = mips_read_timer();
+  /*
+   *  Somehow start the timer
+   */
+
+  /* Timer on 4650 is always running */
+}
+
+/*
+ *  The following controls the behavior of Read_timer().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      8  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in cycles. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+int Read_timer( void )
+{
+  unsigned64 clicks;
+  unsigned32 total;
+
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+  clicks = mips_read_timer();   /* XXX: read some HW here */
+  if (clicks < Timer_initial_value)
+  {
+      clicks += TIMER_MAX_VALUE;
+  }
+  clicks -= Timer_initial_value;
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+#if 0 /* leave total in number of cycles */
+   total = clicks / CLOCKS_PER_MICROSECOND;
+#else
+   total = clicks;
+#endif
+
+  if ( Timer_driver_Find_average_overhead == 1 )
+    return total;          /* in # cycles units */
+  else {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  leave total in cycles
+   */
+      return (total - AVG_OVERHEAD);
+    }
+}
+
+/*
+ *  Empty function call used in loops to measure basic cost of looping
+ *  in Timing Test Suite.
+ */
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
+
diff --git a/c/src/lib/start/mips64orion/idt_csu.S b/c/src/lib/start/mips64orion/idt_csu.S
new file mode 100644
index 0000000000..bbedf0c5dd
--- /dev/null
+++ b/c/src/lib/start/mips64orion/idt_csu.S
@@ -0,0 +1,298 @@
+/*
+
+Based upon IDT provided code with the following release:
+
+This source code has been made available to you by IDT on an AS-IS
+basis. Anyone receiving this source is licensed under IDT copyrights
+to use it in any way he or she deems fit, including copying it,
+modifying it, compiling it, and redistributing it either with or
+without modifications.  No license under IDT patents or patent
+applications is to be implied by the copyright license.
+
+Any user of this software should understand that IDT cannot provide
+technical support for this software and will not be responsible for
+any consequences resulting from the use of this software.
+
+Any person who transfers this source code or any derivative work must
+include the IDT copyright notice, this paragraph, and the preceeding
+two paragraphs in the transferred software.
+
+COPYRIGHT IDT CORPORATION 1996
+LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+
+*/ 
+
+/*************************************************************************
+**
+** Copyright 1991-95 Integrated Device Technology, Inc.
+**	All Rights Reserved
+**
+** idt_csu.S -- IDT stand alone startup code
+**
+**************************************************************************/
+#include <rtems/score/iregdef.h>
+#include <rtems/score/idtcpu.h>
+#include <rtems/score/idtmon.h>
+
+
+.extern _fbss,4		  /* this is defined by the linker */
+.extern end,4		  /* this is defined by the linker */
+
+.lcomm sim_mem_cfg_struct,12
+
+	.text
+
+
+#define TMP_STKSIZE  1024 
+
+/**************************************************************************
+**
+**  start - Typicl standalone start up code required for R3000/R4000
+**
+**
+**	1)  Initialize the STATUS Register
+**		a) Clear parity error bit
+**		b) Set co_processor 1 usable bit ON
+**		c) Clear all IntMask Enables
+**		d) Set kernel/disabled mode
+**	2)  Initialize Cause Register
+**		a)  clear software interrupt bits       
+**	3)  Determine FPU installed or not
+**		if not, clear CoProcessor 1 usable bit
+**	4)  Clear bss area
+**	5)  MUST allocate temporary stack until memory size determined
+**	    It MUST be uncached to prevent overwriting when caches are cleared
+**	6)  Install exception handlers
+**	7)  Determine memory and cache sizes
+**	8)  Establish permanent stack (cached or uncached as defined by bss)
+**	9)  Flush Instruction and Data caches
+** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
+** 	11)  Execute initialization code if the IDT/c library is to be used
+** 
+** 	12)  Jump to user's "main()"
+** 	13)  Jump to promexit
+**
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	This is used to mark code specific to R3xxx or R4xxx processors.
+**	IDT/C 6.x defines __mips to be the ISA level for which we're 
+**	generating code. This is used to make sure the stack etc. is 
+**	double word aligned, when using -mips3 (default) or -mips2, 
+**	when compiling with IDT/C6.x
+**
+***************************************************************************/
+
+FRAME(start,sp,0,ra)
+
+	.set	noreorder
+#ifdef _R3000
+	li	v0,SR_PE|SR_CU1        /* reset parity error and set */
+					/* cp1 usable */
+#endif
+#ifdef _R4000
+#if __mips==3 || defined(R4650)
+	li	v0,SR_CU1|SR_DE|SR_FR 	/* initally clear ERL, enable FPA 64bit regs*/
+	                                /* 4650: Need fr to be set anyway */
+#else
+	li	v0,SR_CU1|SR_DE 	/* initally clear ERL, enable FPA 32bit regs*/
+#endif mips3
+#endif
+
+	mtc0	v0,C0_SR		/* clr IntMsks/ kernel/disabled mode */
+	nop
+	mtc0	zero,C0_CAUSE		/* clear software interrupts */
+	nop
+
+#ifdef _R4000
+	li	v0,CFG_C_NONCOHERENT	# initialise default cache mode
+	mtc0	v0,C0_CONFIG
+#endif
+
+/*
+**	check to see if an fpu is really plugged in 
+*/
+	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
+	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	zero,fp1		/* try to write zero in fp	*/
+	mfc1	t0,fp0
+	mfc1	t1,fp1
+	nop
+	bne	t0,t3,1f		/* branch if no match  */
+	nop
+	bne	t1,zero,1f		/* double check for positive id   */
+	nop
+	/* We have a FPU. clear fcsr */
+	ctc1	zero, fcr31
+	j	2f			/* status register already correct  */
+	nop
+1:
+#ifdef _R3000
+	li	v0, SR_PE		/* reset parity error/NO cp1 usable */
+#endif
+
+#ifdef _R4000
+        li      v0,SR_DE 		/* clear ERL and disable FPA */
+#endif
+
+	mtc0	v0, C0_SR		/* reset status register */
+2:
+	la  	gp, _gp			
+
+	la	v0,_fbss 		/* clear bss before using it */
+	la	v1,end 			/* end of bss */
+3:	sw	zero,0(v0)
+	bltu	v0,v1,3b
+	add	v0,4 
+
+
+/************************************************************************
+**
+** 	Temporary Stack - needed to  handle stack saves until
+**			  memory size is determined and permanent stack set
+**
+**			  MUST be uncached to avoid confusion at cache
+**			       switching during memory sizing
+**
+*************************************************************************/
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack is aligned on a
+	 * double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 11f   /* Last three bits Zero, already aligned */
+	nop
+	add	v0, 4
+11:
+#endif
+
+	or	v0, K1BASE		/* switch to uncached */
+	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
+	sub	v1, v1, (4*4)		/* overhead */
+	move	sp, v1			/* set sp to top of stack */
+4:	sw	zero, 0(v0)  
+	bltu	v0, v1, 4b		/* clear out temp stack */
+	add	v0, 4 
+	
+	jal	init_exc_vecs		/* install exception handlers */ 
+	nop				/* MUST do before memory probes */
+
+	la	v0, 5f
+	li	v1, K1BASE		/* force into uncached space */
+	or	v0, v1			/* during memory/cache probes */
+	j	v0
+	nop
+5:
+	la	a0, sim_mem_cfg_struct
+	jal	sim_mem_cfg		/* Make SIM call to get mem size */
+	nop
+	la	a0, sim_mem_cfg_struct
+	lw	a0, 0(a0)		/* Get memory size from struct */
+#ifdef _R3000
+	jal	config_Icache
+	nop
+	jal	config_Dcache		/* determine size of D & I caches */
+	nop	
+#endif
+#ifdef _R4000
+	jal	config_cache		/* determine size of D & I caches */
+	nop
+#endif
+
+	move	v0, a0			/* mem_size */
+
+#if __mips==3
+	/* For MIPS 3, we need to be sure that the stack (and hence v0
+	 * here) is aligned on a double word boundary. 
+	 */
+	andi	t0, v0, 0x7
+	beqz	t0, 12f   /* Last three bits Zero, already aligned */
+	nop
+	subu	v0, 4	/* mem_size was not aligned on doubleword bdry????*/
+12:
+#endif
+
+
+
+/**************************************************************************
+**
+**  Permanent Stack - now know top of memory, put permanent stack there	
+**
+***************************************************************************/ 
+
+	la	t2, _fbss		/* cache mode as linked */
+	and	t2, 0xF0000000		/* isolate segment */
+	la	t1, 6f
+	j	t1			/* back to original cache mode */
+	nop
+6:
+	or 	v0, t2			/* stack back to original cache mode */
+	addiu   v0,v0,-16		/* overhead */
+	move	sp, v0			/* now replace count w top of memory */
+	move	v1, v0
+	subu	v1, P_STACKSIZE 	/* clear requested stack size */
+
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+	bltu	v1,v0,7b
+	add	v1, 4 
+	.set	reorder
+
+#ifdef _R3000 
+	jal	flush_Icache	
+	jal	flush_Dcache		/* flush Data & Instruction caches */
+#endif
+#ifdef _R4000 
+	jal	flush_cache_nowrite	/* flush Data & Instruction caches */
+#endif
+
+
+
+/**************************************************************************
+**
+**	If this chip supports a Translation Lookaside Buffer, clear it
+**
+***************************************************************************/ 
+
+	.set	noreorder
+	mfc0	t1,  C0_SR		/* look at Status Register */
+	nop
+	.set 	reorder
+#ifdef _R3000
+	li	t2, SR_TS		/* TLB Shutdown bit */
+	and 	t1,t2      		/* TLB Shutdown if 1 */
+	bnez	t1, 8f			/* skip clearing if no TLB */	
+#endif
+
+#ifndef R4650
+	jal	init_tlb		/* clear the tlb */
+#endif
+
+
+/************************************************************************
+**
+**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**
+**  can SKIP if not necessary for application
+**
+************************************************************************/
+8:
+
+	jal	idtsim_init_sbrk
+	jal	idtsim_init_file
+/***********************  END I/O initialization **********************/
+
+
+	jal	main
+
+	jal	idtsim_promexit
+
+ENDFRAME(start)
+
+
+	.globl	sim_mem_cfg
+sim_mem_cfg:
+	.set noat
+	.set noreorder
+	li	AT, (0xbfc00000+((55)*8))
+	jr	AT
+	nop
+	.set at
+	.set reorder