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authorJoel Sherrill <joel.sherrill@OARcorp.com>2003-07-18 17:24:18 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2003-07-18 17:24:18 +0000
commitae20a3e22e14ed65dd34666ef54e7956f57714e0 (patch)
tree08437fb9b50c9877fd73189d647cef9a54581463 /c/src
parent2003-07-18 Till Straumann <strauman@slac.stanford.edu> (diff)
downloadrtems-ae20a3e22e14ed65dd34666ef54e7956f57714e0.tar.bz2
2003-07-18 Till Straumann <strauman@slac.stanford.edu>
PR 288/rtems * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly maintained.
Diffstat (limited to 'c/src')
-rw-r--r--c/src/lib/libbsp/powerpc/eth_comm/ChangeLog6
-rw-r--r--c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S27
-rw-r--r--c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c11
-rw-r--r--c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog6
-rw-r--r--c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S27
-rw-r--r--c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c11
6 files changed, 80 insertions, 8 deletions
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/ChangeLog b/c/src/lib/libbsp/powerpc/eth_comm/ChangeLog
index 0280d468bd..d191c8dc32 100644
--- a/c/src/lib/libbsp/powerpc/eth_comm/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/eth_comm/ChangeLog
@@ -1,3 +1,9 @@
+2003-07-18 Till Straumann <strauman@slac.stanford.edu>
+
+ PR 288/rtems
+ * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
+ maintained.
+
2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove AC_CONFIG_AUX_DIR.
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S
index 9a44367deb..f302faff88 100644
--- a/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S
+++ b/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S
@@ -9,6 +9,9 @@
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
+ * Till Straumann <strauman@slac.stanford.edu>, 2003/7:
+ * - store isr nesting level in _ISR_Nest_level rather than
+ * SPRG0 - RTEMS relies on that variable.
*
* $Id$
*/
@@ -136,10 +139,18 @@ SYM (shared_raw_irq_code_entry):
* store part of _Thread_Dispatch_disable_level address in R15
*/
addis r15,0, _Thread_Dispatch_disable_level@ha
+#if BROKEN_ISR_NEST_LEVEL
/*
* Get current nesting level in R2
*/
mfspr r2, SPRG0
+#else
+ /*
+ * Retrieve current nesting level from _ISR_Nest_level
+ */
+ lis r7, _ISR_Nest_level@ha
+ lwz r2, _ISR_Nest_level@l(r7)
+#endif
/*
* Check if stack switch is necessary
*/
@@ -156,10 +167,15 @@ nested:
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
lwz r6,_Thread_Dispatch_disable_level@l(r15)
+#if BROKEN_ISR_NEST_LEVEL
/*
- * store new nesting level in SPRG0
+ * Store new nesting level in SPRG0
*/
mtspr SPRG0, r2
+#else
+ /* store new nesting level in _ISR_Nest_level */
+ stw r2, _ISR_Nest_level@l(r7)
+#endif
addi r6, r6, 1
mfmsr r5
@@ -183,14 +199,23 @@ nested:
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
+#if BROKEN_ISR_NEST_LEVEL
mfspr r2, SPRG0
+#else
+ lis r7, _ISR_Nest_level@ha
+ lwz r2, _ISR_Nest_level@l(r7)
+#endif
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
addi r2, r2, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
+#if BROKEN_ISR_NEST_LEVEL
mtspr SPRG0, r2 /* End decrementing nesting level */
+#else
+ stw r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
+#endif
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
diff --git a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
index 5832ee1307..57381115cf 100644
--- a/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c
@@ -25,6 +25,7 @@
#include <rtems/libcsupport.h>
#include <info.h>
#include <libcpu/cpuIdent.h>
+#include <libcpu/spr.h>
#include <rtems/bspIo.h>
boardinfo_t M860_binfo;
@@ -108,6 +109,8 @@ bsp_pretasking_hook(void)
#endif
}
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
void bsp_start(void)
{
@@ -117,7 +120,6 @@ void bsp_start(void)
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
- register unsigned int intrNestingLevel = 0;
extern void cpu_init(void);
/*
@@ -134,8 +136,11 @@ void bsp_start(void)
*/
intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
- asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack));
- asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
+
+ _write_SPRG1((unsigned int)intrStack);
+
+ /* Signal them that this BSP has fixed PR288 - eventually, this should go away */
+ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
* Install our own set of exception vectors
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
index e8fc01f377..cd1e47b6b8 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
@@ -1,3 +1,9 @@
+2003-07-18 Till Straumann <strauman@slac.stanford.edu>
+
+ PR 288/rtems
+ * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
+ maintained.
+
2003-04-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* ide/.cvsignore: Add.
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S
index 6131100e9f..b59bf862f2 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S
@@ -9,6 +9,9 @@
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
+ * Till Straumann <strauman@slac.stanford.edu>, 2003/7:
+ * - store isr nesting level in _ISR_Nest_level rather than
+ * SPRG0 - RTEMS relies on that variable.
*
* $Id$
*/
@@ -176,10 +179,18 @@ SYM (shared_raw_irq_code_entry):
* store part of _Thread_Dispatch_disable_level address in R15
*/
addis r15,0, _Thread_Dispatch_disable_level@ha
+#if BROKEN_ISR_NEST_LEVEL
/*
* Get current nesting level in R2
*/
mfspr r2, SPRG0
+#else
+ /*
+ * Retrieve current nesting level from _ISR_Nest_level
+ */
+ lis r7, _ISR_Nest_level@ha
+ lwz r2, _ISR_Nest_level@l(r7)
+#endif
/*
* Check if stack switch is necessary
*/
@@ -196,10 +207,15 @@ nested:
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
lwz r6,_Thread_Dispatch_disable_level@l(r15)
+#if BROKEN_ISR_NEST_LEVEL
/*
- * store new nesting level in SPRG0
+ * Store new nesting level in SPRG0
*/
mtspr SPRG0, r2
+#else
+ /* store new nesting level in _ISR_Nest_level */
+ stw r2, _ISR_Nest_level@l(r7)
+#endif
addi r6, r6, 1
mfmsr r5
@@ -223,14 +239,23 @@ nested:
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
+#if BROKEN_ISR_NEST_LEVEL
mfspr r2, SPRG0
+#else
+ lis r7, _ISR_Nest_level@ha
+ lwz r2, _ISR_Nest_level@l(r7)
+#endif
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
addi r2, r2, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
+#if BROKEN_ISR_NEST_LEVEL
mtspr SPRG0, r2 /* End decrementing nesting level */
+#else
+ stw r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
+#endif
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
index 832c698c45..33f37fc0fd 100644
--- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
@@ -26,6 +26,11 @@
#include <rtems/libcsupport.h>
#include <rtems/bspIo.h>
#include <libcpu/cpuIdent.h>
+#include <libcpu/spr.h>
+
+
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
/*
* The original table from the application (in ROM) and our copy of it with
@@ -134,7 +139,6 @@ void bsp_start(void)
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
- register unsigned int intrNestingLevel = 0;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
@@ -166,8 +170,9 @@ void bsp_start(void)
*/
intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
- asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack));
- asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
+ _write_SPRG1((unsigned int)intrStack);
+ /* signal them that we have fixed PR288 - eventually, this should go away */
+ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
* Install our own set of exception vectors