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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-06-14 17:07:54 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-06-14 17:07:54 +0000
commitac8154305172ebcb347f5563dd3ce17d95b4736b (patch)
tree6f24392d14911a8911b287a8b478016c40cb3a26 /c/src
parent61bd030179f252d14f9639cf4921eb4eee07b5ef (diff)
downloadrtems-ac8154305172ebcb347f5563dd3ce17d95b4736b.tar.bz2
Patch rtems-rc-20000614-sh.tar.gz from Ralf Corsepius
<corsepiu@faw.uni-ulm.de> that migrates the SH port to multilib'ing. This patch involved moving a number of files in the CVS repository, adding new files, and deleting files from their previous location. Ralf gave good instructions (not repeated here) and here are his notes: Note 1: In this version, I did not change the installation points of the headers which are moved inside of the source-tree. This is a temporary hack for not breaking compatibility with 4.5 based BSPs, but will probably not last once having real multilibs (We would have include file conflicts when several BSPs/CPU_MODELS share a common installation prefix). Note 2: I hope not to have broken too much, but I would not be astonished if something goes wrong. Note 3: There are more patches to come :)
Diffstat (limited to 'c/src')
-rw-r--r--c/src/exec/score/cpu/sh/Makefile.am4
-rw-r--r--c/src/exec/score/cpu/sh/cpu_asm.c318
-rw-r--r--c/src/exec/score/cpu/sh/ispsh7032.c256
-rw-r--r--c/src/exec/score/cpu/sh/ispsh7045.c315
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/Makefile.am6
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/iosh7032.h223
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/iosh7045.h321
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h165
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h211
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/sh.h19
-rw-r--r--c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.am2
-rw-r--r--c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.am2
-rw-r--r--c/src/lib/libcpu/sh/Makefile.am2
-rw-r--r--c/src/lib/libcpu/sh/configure.in23
-rw-r--r--c/src/lib/libcpu/sh/sh7032/Makefile.am7
-rw-r--r--c/src/lib/libcpu/sh/sh7032/clock/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7032/configure.in38
-rw-r--r--c/src/lib/libcpu/sh/sh7032/delay/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7032/include/Makefile.am9
-rw-r--r--c/src/lib/libcpu/sh/sh7032/null/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7032/sci/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7032/score/Makefile.am30
-rw-r--r--c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c6
-rw-r--r--c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c4
-rw-r--r--c/src/lib/libcpu/sh/sh7032/timer/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7045/Makefile.am7
-rw-r--r--c/src/lib/libcpu/sh/sh7045/clock/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7045/configure.in37
-rw-r--r--c/src/lib/libcpu/sh/sh7045/include/Makefile.am9
-rw-r--r--c/src/lib/libcpu/sh/sh7045/null/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7045/sci/Makefile.am4
-rw-r--r--c/src/lib/libcpu/sh/sh7045/score/Makefile.am30
-rw-r--r--c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c6
-rw-r--r--c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c4
-rw-r--r--c/src/lib/libcpu/sh/sh7045/timer/Makefile.am4
35 files changed, 198 insertions, 1892 deletions
diff --git a/c/src/exec/score/cpu/sh/Makefile.am b/c/src/exec/score/cpu/sh/Makefile.am
index d6c8f3ae05..1ed4187fe0 100644
--- a/c/src/exec/score/cpu/sh/Makefile.am
+++ b/c/src/exec/score/cpu/sh/Makefile.am
@@ -21,7 +21,7 @@ $(PROJECT_INCLUDE)/%.h: %.h
$(PROJECT_RELEASE)/lib/rtems$(LIB_VARIANT).o: $(ARCH)/rtems.o
$(INSTALL_DATA) $< $@
-C_FILES = cpu.c cpu_asm.c isp$(RTEMS_CPU_MODEL).c
+C_FILES = cpu.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
REL = $(ARCH)/rtems-cpu.rel
@@ -40,7 +40,7 @@ all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \
.PRECIOUS: $(REL)
-EXTRA_DIST = asm.h cpu.c cpu_asm.c ispsh7032.c ispsh7045.c rtems.c
+EXTRA_DIST = asm.h cpu.c rtems.c
include $(top_srcdir)/../../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/exec/score/cpu/sh/cpu_asm.c b/c/src/exec/score/cpu/sh/cpu_asm.c
deleted file mode 100644
index 192c2f43d2..0000000000
--- a/c/src/exec/score/cpu/sh/cpu_asm.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * This file contains the basic algorithms for all assembly code used
- * in an specific CPU port of RTEMS. These algorithms must be implemented
- * in assembly language
- *
- * NOTE: This port uses a C file with inline assembler instructions
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- *
- * This material may be reproduced by or for the U.S. Government pursuant
- * to the copyright license under the clause at DFARS 252.227-7013. This
- * notice must appear in all copies of this file and its derivatives.
- *
- */
-
-/*
- * This is supposed to be an assembly file. This means that system.h
- * and cpu.h should not be included in a "real" cpu_asm file. An
- * implementation in assembly should include "cpu_asm.h"
- */
-
-#include <rtems/system.h>
-#include <rtems/score/cpu.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/thread.h>
-#include <rtems/score/sh.h>
-
-#if defined(sh7032)
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-#elif defined (sh7045)
-#include <rtems/score/ispsh7045.h>
-#include <rtems/score/iosh7045.h>
-#endif
-
-#include <rtems/score/sh_io.h>
-
-/* from cpu_isps.c */
-extern proc_ptr _Hardware_isr_Table[];
-
-#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
- unsigned long *_old_stack_ptr;
-#endif
-
-register unsigned long *stack_ptr asm("r15");
-
-/*
- * sh_set_irq_priority
- *
- * this function sets the interrupt level of the specified interrupt
- *
- * parameters:
- * - irq : interrupt number
- * - prio: priority to set for this interrupt number
- *
- * returns: 0 if ok
- * -1 on error
- */
-
-unsigned int sh_set_irq_priority(
- unsigned int irq,
- unsigned int prio )
-{
- unsigned32 shiftcount;
- unsigned32 prioreg;
- unsigned16 temp16;
- unsigned32 level;
-
- /*
- * first check for valid interrupt
- */
- if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
- return -1;
- /*
- * check for valid irq priority
- */
- if( prio > 15 )
- return -1;
-
- /*
- * look up appropriate interrupt priority register
- */
- if( irq > 71)
- {
- irq = irq - 72;
- shiftcount = 12 - ((irq & ~0x03) % 16);
-
- switch( irq / 16)
- {
- case 0: { prioreg = INTC_IPRC; break;}
- case 1: { prioreg = INTC_IPRD; break;}
- case 2: { prioreg = INTC_IPRE; break;}
- default: return -1;
- }
- }
- else
- {
- shiftcount = 12 - 4 * ( irq % 4);
- if( irq > 67)
- prioreg = INTC_IPRB;
- else
- prioreg = INTC_IPRA;
- }
-
- /*
- * Set the interrupt priority register
- */
- _CPU_ISR_Disable( level );
-
- temp16 = read16( prioreg);
- temp16 &= ~( 15 << shiftcount);
- temp16 |= prio << shiftcount;
- write16( temp16, prioreg);
-
- _CPU_ISR_Enable( level );
-
- return 0;
-}
-
-/*
- * _CPU_Context_save_fp_context
- *
- * This routine is responsible for saving the FP context
- * at *fp_context_ptr. If the point to load the FP context
- * from is changed then the pointer is modified by this routine.
- *
- * Sometimes a macro implementation of this is in cpu.h which dereferences
- * the ** and a similarly named routine in this file is passed something
- * like a (Context_Control_fp *). The general rule on making this decision
- * is to avoid writing assembly language.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-)
-{
-}
-
-/*
- * _CPU_Context_restore_fp_context
- *
- * This routine is responsible for restoring the FP context
- * at *fp_context_ptr. If the point to load the FP context
- * from is changed then the pointer is modified by this routine.
- *
- * Sometimes a macro implementation of this is in cpu.h which dereferences
- * the ** and a similarly named routine in this file is passed something
- * like a (Context_Control_fp *). The general rule on making this decision
- * is to avoid writing assembly language.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-)
-{
-}
-
-/* _CPU_Context_switch
- *
- * This routine performs a normal non-FP context switch.
- */
-
-/* within __CPU_Context_switch:
- * _CPU_Context_switch
- * _CPU_Context_restore
- *
- * This routine is generally used only to restart self in an
- * efficient manner. It may simply be a label in _CPU_Context_switch.
- *
- * NOTE: It should be safe not to store r4, r5
- *
- * NOTE: It is doubtful if r0 is really needed to be stored
- *
- * NOTE: gbr is added, but should not be necessary, as it is
- * only used globally in this port.
- */
-
-/*
- * FIXME: This is an ugly hack, but we wanted to avoid recalculating
- * the offset each time Context_Control is changed
- */
-void __CPU_Context_switch(
- Context_Control *run, /* r4 */
- Context_Control *heir /* r5 */
-)
-{
-
-asm volatile("
- .global __CPU_Context_switch
-__CPU_Context_switch:
-
- add %0,r4
-
- stc.l sr,@-r4
- stc.l gbr,@-r4
- mov.l r0,@-r4
- mov.l r1,@-r4
- mov.l r2,@-r4
- mov.l r3,@-r4
-
- mov.l r6,@-r4
- mov.l r7,@-r4
- mov.l r8,@-r4
- mov.l r9,@-r4
- mov.l r10,@-r4
- mov.l r11,@-r4
- mov.l r12,@-r4
- mov.l r13,@-r4
- mov.l r14,@-r4
- sts.l pr,@-r4
- sts.l mach,@-r4
- sts.l macl,@-r4
- mov.l r15,@-r4
-
- mov r5, r4"
- :: "I" (sizeof(Context_Control))
- );
-
- asm volatile("
- .global __CPU_Context_restore
-__CPU_Context_restore:
- mov.l @r4+,r15
- lds.l @r4+,macl
- lds.l @r4+,mach
- lds.l @r4+,pr
- mov.l @r4+,r14
- mov.l @r4+,r13
- mov.l @r4+,r12
- mov.l @r4+,r11
- mov.l @r4+,r10
- mov.l @r4+,r9
- mov.l @r4+,r8
- mov.l @r4+,r7
- mov.l @r4+,r6
-
- mov.l @r4+,r3
- mov.l @r4+,r2
- mov.l @r4+,r1
- mov.l @r4+,r0
- ldc.l @r4+,gbr
- ldc.l @r4+,sr
-
- rts
- nop" );
-}
-
-/*
- * This routine provides the RTEMS interrupt management.
- */
-
-void __ISR_Handler( unsigned32 vector)
-{
- register unsigned32 level;
-
- _CPU_ISR_Disable( level );
-
- _Thread_Dispatch_disable_level++;
-
-#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
- if( _ISR_Nest_level == 0 )
- {
- /* Install irq stack */
- _old_stack_ptr = stack_ptr;
- stack_ptr = _CPU_Interrupt_stack_high;
- }
-
-#endif
-
- _ISR_Nest_level++;
-
- _CPU_ISR_Enable( level );
-
- /* call isp */
- if( _ISR_Vector_table[ vector])
- (*_ISR_Vector_table[ vector ])( vector );
-
- _CPU_ISR_Disable( level );
-
- _ISR_Nest_level--;
-
-#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
-
- if( _ISR_Nest_level == 0 )
- /* restore old stack pointer */
- stack_ptr = _old_stack_ptr;
-#endif
-
- _Thread_Dispatch_disable_level--;
-
- _CPU_ISR_Enable( level );
-
- if ( _Thread_Dispatch_disable_level == 0 )
- {
- if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
- {
- _ISR_Signals_to_thread_executing = FALSE;
- _Thread_Dispatch();
- }
- }
-}
diff --git a/c/src/exec/score/cpu/sh/ispsh7032.c b/c/src/exec/score/cpu/sh/ispsh7032.c
deleted file mode 100644
index 9fcc9badbf..0000000000
--- a/c/src/exec/score/cpu/sh/ispsh7032.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * This file contains the isp frames for the user interrupts.
- * From these procedures __ISR_Handler is called with the vector number
- * as argument.
- *
- * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
- * some releases of gcc doesn't properly handle #pragma interrupt, if a
- * file contains both isrs and normal functions.
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#include <rtems/system.h>
-#include <rtems/score/shtypes.h>
-#include <rtems/score/ispsh7032.h>
-
-#if !defined(sh7032)
-#error Wrong CPU MODEL
-#endif
-
-/*
- * This is an exception vector table
- *
- * It has the same structure like the actual vector table (vectab)
- */
-proc_ptr _Hardware_isr_Table[256]={
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-_nmi_isp, _usb_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-/* trapa 0 -31 */
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-/* irq 64 ... */
-_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
-_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
-_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
-_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
-_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
-_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
-_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
-_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
-_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
-_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
-_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
-_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
-_wdt_isp,
-/* 113 */ _dref_isp
-};
-
-#define Str(a)#a
-
-/*
- * Some versions of gcc and all version of egcs at least until egcs-1.1b
- * are not able to handle #pragma interrupt correctly if more than 1 isr is
- * contained in a file and when optimizing.
- * We try to work around this problem by using the macro below.
- */
-#define isp( name, number, func)\
-asm (".global _"Str(name)"\n\t" \
- "_"Str(name)": \n\t" \
- " mov.l r0,@-r15 \n\t" \
- " mov.l r1,@-r15 \n\t" \
- " mov.l r2,@-r15 \n\t" \
- " mov.l r3,@-r15 \n\t" \
- " mov.l r4,@-r15 \n\t" \
- " mov.l r5,@-r15 \n\t" \
- " mov.l r6,@-r15 \n\t" \
- " mov.l r7,@-r15 \n\t" \
- " mov.l r14,@-r15 \n\t" \
- " sts.l pr,@-r15 \n\t" \
- " sts.l mach,@-r15 \n\t" \
- " sts.l macl,@-r15 \n\t" \
- " mov r15,r14 \n\t" \
- " mov.l "Str(name)"_k, r1\n\t" \
- " jsr @r1 \n\t" \
- " mov #"Str(number)", r4\n\t" \
- " mov r14,r15 \n\t" \
- " lds.l @r15+,macl \n\t" \
- " lds.l @r15+,mach \n\t" \
- " lds.l @r15+,pr \n\t" \
- " mov.l @r15+,r14 \n\t" \
- " mov.l @r15+,r7 \n\t" \
- " mov.l @r15+,r6 \n\t" \
- " mov.l @r15+,r5 \n\t" \
- " mov.l @r15+,r4 \n\t" \
- " mov.l @r15+,r3 \n\t" \
- " mov.l @r15+,r2 \n\t" \
- " mov.l @r15+,r1 \n\t" \
- " mov.l @r15+,r0 \n\t" \
- " rte \n\t" \
- " nop \n\t" \
- " .align 2 \n\t" \
- #name"_k: \n\t" \
- ".long "Str(func));
-
-/************************************************
- * Dummy interrupt service procedure for
- * interrupts being not allowed --> Trap 34
- ************************************************/
-asm(" .section .text
-.global __dummy_isp
-__dummy_isp:
- mov.l r14,@-r15
- mov r15, r14
- trapa #34
- mov.l @r15+,r14
- rte
- nop");
-
-/*****************************
- * Non maskable interrupt
- *****************************/
-isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
-
-/*****************************
- * User break controller
- *****************************/
-isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
-
-/*****************************
- * External interrupts 0-7
- *****************************/
-isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
-isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
-isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
-isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
-isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
-isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
-isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
-isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
-
-/*****************************
- * DMA - controller
- *****************************/
-isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
-isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
-isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
-isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Interrupt timer unit
- *****************************/
-
-/*****************************
- * Timer 0
- *****************************/
-isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
-isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
-isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 1
- *****************************/
-isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
-isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
-isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 2
- *****************************/
-isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
-isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
-isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 3
- *****************************/
-isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
-isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
-isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 4
- *****************************/
-isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
-isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
-isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Serial interfaces
- *****************************/
-
-/*****************************
- * Serial interface 0
- *****************************/
-isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
-isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
-isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
-isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Serial interface 1
- *****************************/
-isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
-isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
-isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
-isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Parity control unit of
- * the bus state controller
- *****************************/
-isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Analog digital converter
- * ADC
- ******************************/
-isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Watchdog timer
- ******************************/
-isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * DRAM refresh control unit
- * of bus state controller
- ******************************/
-isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);
diff --git a/c/src/exec/score/cpu/sh/ispsh7045.c b/c/src/exec/score/cpu/sh/ispsh7045.c
deleted file mode 100644
index 4009ea152a..0000000000
--- a/c/src/exec/score/cpu/sh/ispsh7045.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * This file contains the isp frames for the user interrupts.
- * From these procedures __ISR_Handler is called with the vector number
- * as argument.
- *
- * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
- * some releases of gcc doesn't properly handle #pragma interrupt, if a
- * file contains both isrs and normal functions.
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * Modified to reflect isp entries for sh7045 processor:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- * August, 1999
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- *
- * $Id$
- */
-
-#include <rtems/system.h>
-#include <rtems/score/shtypes.h>
-
-#if !defined (sh7045)
-#error Wrong CPU MODEL
-#endif
-
-/*
- * This is a exception vector table
- *
- * It has the same structure as the actual vector table (vectab)
- */
-
-
-/* SH-2 ISR Table */
-#include <rtems/score/ispsh7045.h>
-
-proc_ptr _Hardware_isr_Table[256]={
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-_nmi_isp, _usb_isp, /* irq 11, 12*/
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp,
-/* trapa 0 -31 */
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
-_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
-_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
-_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
-_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
-_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
-_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
-_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
-_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
-_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
-_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
-_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
-_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
-_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
-_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
-_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
-_wdt_isp, /* WDT: irq 152*/
-_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
-_oei_isp, /* I/O Port: irq 156*/
-};
-
-#define Str(a)#a
-
-/*
- * Some versions of gcc and all version of egcs at least until egcs-1.1b
- * are not able to handle #pragma interrupt correctly if more than 1 isr is
- * contained in a file and when optimizing.
- * We try to work around this problem by using the macro below.
- */
-#define isp( name, number, func)\
-asm (".global _"Str(name)"\n\t" \
- "_"Str(name)": \n\t" \
- " mov.l r0,@-r15 \n\t" \
- " mov.l r1,@-r15 \n\t" \
- " mov.l r2,@-r15 \n\t" \
- " mov.l r3,@-r15 \n\t" \
- " mov.l r4,@-r15 \n\t" \
- " mov.l r5,@-r15 \n\t" \
- " mov.l r6,@-r15 \n\t" \
- " mov.l r7,@-r15 \n\t" \
- " mov.l r14,@-r15 \n\t" \
- " sts.l pr,@-r15 \n\t" \
- " sts.l mach,@-r15 \n\t" \
- " sts.l macl,@-r15 \n\t" \
- " mov r15,r14 \n\t" \
- " mov.l "Str(name)"_k, r1\n\t" \
- " jsr @r1 \n\t" \
- " mov #"Str(number)", r4\n\t" \
- " mov r14,r15 \n\t" \
- " lds.l @r15+,macl \n\t" \
- " lds.l @r15+,mach \n\t" \
- " lds.l @r15+,pr \n\t" \
- " mov.l @r15+,r14 \n\t" \
- " mov.l @r15+,r7 \n\t" \
- " mov.l @r15+,r6 \n\t" \
- " mov.l @r15+,r5 \n\t" \
- " mov.l @r15+,r4 \n\t" \
- " mov.l @r15+,r3 \n\t" \
- " mov.l @r15+,r2 \n\t" \
- " mov.l @r15+,r1 \n\t" \
- " mov.l @r15+,r0 \n\t" \
- " rte \n\t" \
- " nop \n\t" \
- " .align 2 \n\t" \
- #name"_k: \n\t" \
- ".long "Str(func));
-
-/************************************************
- * Dummy interrupt service procedure for
- * interrupts being not allowed --> Trap 34
- ************************************************/
-asm(" .section .text
-.global __dummy_isp
-__dummy_isp:
- mov.l r14,@-r15
- mov r15, r14
- trapa #34
- mov.l @r15+,r14
- rte
- nop");
-
-/*******************************************************************
- * ISP Vector Table for sh7045 family of processors *
- *******************************************************************/
-
-
-/*****************************
- * Non maskable interrupt
- *****************************/
-isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
-
-/*****************************
- * User break controller
- *****************************/
-isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
-
-/*****************************
- * External interrupts 0-7
- *****************************/
-isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
-isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
-isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
-isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
-isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
-isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
-isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
-isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
-
-/*****************************
- * DMA - controller
- *****************************/
-isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
-isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
-isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
-isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Match timer unit
- *****************************/
-
-/*****************************
- * Timer 0
- *****************************/
-isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
-isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
-isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
-isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
-isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 1
- *****************************/
-isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
-isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
-isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
-isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 2
- *****************************/
-isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
-isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
-isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
-isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 3
- *****************************/
-isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
-isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
-isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
-isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
-isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Timer 4
- *****************************/
-isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
-isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
-isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
-isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
-isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Serial interfaces
- *****************************/
-
-/*****************************
- * Serial interface 0
- *****************************/
-isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
-isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
-isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
-isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
-
-/*****************************
- * Serial interface 1
- *****************************/
-isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
-isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
-isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
-isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * A/D converters
- * ADC0-1
- ******************************/
-isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
-isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Data transfer controller
- ******************************/
-isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Counter match timer
- ******************************/
-isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
-isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * Watchdog timer
- ******************************/
-isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
-
-
-/******************************
- * DRAM refresh control unit
- * of bus state controller
- ******************************/
-isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
-
-/******************************
- * I/O port
- ******************************/
-isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
-
-
-/*****************************
- * Parity control unit of
- * the bus state controller
- * NOT PROVIDED IN SH-2
- *****************************/
-/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */
diff --git a/c/src/exec/score/cpu/sh/rtems/score/Makefile.am b/c/src/exec/score/cpu/sh/rtems/score/Makefile.am
index f650704221..a9b4cae02a 100644
--- a/c/src/exec/score/cpu/sh/rtems/score/Makefile.am
+++ b/c/src/exec/score/cpu/sh/rtems/score/Makefile.am
@@ -4,10 +4,8 @@
AUTOMAKE_OPTIONS = foreign 1.4
-H_FILES = cpu.h shtypes.h sh.h sh_io.h isp$(RTEMS_CPU_MODEL).h \
- io$(RTEMS_CPU_MODEL).h
-noinst_HEADERS = cpu.h shtypes.h sh.h sh_io.h iosh7032.h ispsh7032.h \
- iosh7045.h ispsh7045.h
+H_FILES = cpu.h shtypes.h sh.h sh_io.h
+noinst_HEADERS = cpu.h shtypes.h sh.h sh_io.h
#
# (OPTIONAL) Add local stuff here using +=
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h
deleted file mode 100644
index e98185414b..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
- * contained no copyright notice.
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __IOSH7030_H
-#define __IOSH7030_H
-
-/*
- * After each line is explained whether the access is char short or long.
- * The functions read/writeb, w, l, 8, 16, 32 can be found
- * in exec/score/cpu/sh/sh_io.h
- *
- * 8 bit == char ( readb, writeb, read8, write8)
- * 16 bit == short ( readw, writew, read16, write16 )
- * 32 bit == long ( readl, writel, read32, write32 )
- */
-
-#define SCI0_SMR 0x05fffec0 /* char */
-#define SCI0_BRR 0x05fffec1 /* char */
-#define SCI0_SCR 0x05fffec2 /* char */
-#define SCI0_TDR 0x05fffec3 /* char */
-#define SCI0_SSR 0x05fffec4 /* char */
-#define SCI0_RDR 0x05fffec5 /* char */
-
-#define SCI1_SMR 0x05fffec8 /* char */
-#define SCI1_BRR 0x05fffec9 /* char */
-#define SCI1_SCR 0x05fffeca /* char */
-#define SCI1_TDR 0x05fffecb /* char */
-#define SCI1_SSR 0x05fffecc /* char */
-#define SCI1_RDR 0x05fffecd /* char */
-
-
-#define ADDRAH 0x05fffee0 /* char */
-#define ADDRAL 0x05fffee1 /* char */
-#define ADDRBH 0x05fffee2 /* char */
-#define ADDRBL 0x05fffee3 /* char */
-#define ADDRCH 0x05fffee4 /* char */
-#define ADDRCL 0x05fffee5 /* char */
-#define ADDRDH 0x05fffee6 /* char */
-#define ADDRDL 0x05fffee7 /* char */
-#define AD_DRA 0x05fffee0 /* short */
-#define AD_DRB 0x05fffee2 /* short */
-#define AD_DRC 0x05fffee4 /* short */
-#define AD_DRD 0x05fffee6 /* short */
-#define ADCSR 0x05fffee8 /* char */
-#define ADCR 0x05fffee9 /* char */
-
-/*ITU SHARED*/
-#define ITU_TSTR 0x05ffff00 /* char */
-#define ITU_TSNC 0x05ffff01 /* char */
-#define ITU_TMDR 0x05ffff02 /* char */
-#define ITU_TFCR 0x05ffff03 /* char */
-
-/*ITU CHANNEL 0*/
-#define ITU_TCR0 0x05ffff04 /* char */
-#define ITU_TIOR0 0x05ffff05 /* char */
-#define ITU_TIER0 0x05ffff06 /* char */
-#define ITU_TSR0 0x05ffff07 /* char */
-#define ITU_TCNT0 0x05ffff08 /* short */
-#define ITU_GRA0 0x05ffff0a /* short */
-#define ITU_GRB0 0x05ffff0c /* short */
-
- /*ITU CHANNEL 1*/
-#define ITU_TCR1 0x05ffff0E /* char */
-#define ITU_TIOR1 0x05ffff0F /* char */
-#define ITU_TIER1 0x05ffff10 /* char */
-#define ITU_TSR1 0x05ffff11 /* char */
-#define ITU_TCNT1 0x05ffff12 /* short */
-#define ITU_GRA1 0x05ffff14 /* short */
-#define ITU_GRB1 0x05ffff16 /* short */
-
-
- /*ITU CHANNEL 2*/
-#define ITU_TCR2 0x05ffff18 /* char */
-#define ITU_TIOR2 0x05ffff19 /* char */
-#define ITU_TIER2 0x05ffff1A /* char */
-#define ITU_TSR2 0x05ffff1B /* char */
-#define ITU_TCNT2 0x05ffff1C /* short */
-#define ITU_GRA2 0x05ffff1E /* short */
-#define ITU_GRB2 0x05ffff20 /* short */
-
- /*ITU CHANNEL 3*/
-#define ITU_TCR3 0x05ffff22 /* char */
-#define ITU_TIOR3 0x05ffff23 /* char */
-#define ITU_TIER3 0x05ffff24 /* char */
-#define ITU_TSR3 0x05ffff25 /* char */
-#define ITU_TCNT3 0x05ffff26 /* short */
-#define ITU_GRA3 0x05ffff28 /* short */
-#define ITU_GRB3 0x05ffff2A /* short */
-#define ITU_BRA3 0x05ffff2C /* short */
-#define ITU_BRB3 0x05ffff2E /* short */
-
- /*ITU CHANNELS 0-4 SHARED*/
-#define ITU_TOCR 0x05ffff31 /* char */
-
- /*ITU CHANNEL 4*/
-#define ITU_TCR4 0x05ffff32 /* char */
-#define ITU_TIOR4 0x05ffff33 /* char */
-#define ITU_TIER4 0x05ffff34 /* char */
-#define ITU_TSR4 0x05ffff35 /* char */
-#define ITU_TCNT4 0x05ffff36 /* short */
-#define ITU_GRA4 0x05ffff38 /* short */
-#define ITU_GRB4 0x05ffff3A /* short */
-#define ITU_BRA4 0x05ffff3C /* short */
-#define ITU_BRB4 0x05ffff3E /* short */
-
- /*DMAC CHANNELS 0-3 SHARED*/
-#define DMAOR 0x05ffff48 /* short */
-
- /*DMAC CHANNEL 0*/
-#define DMA_SAR0 0x05ffff40 /* long */
-#define DMA_DAR0 0x05ffff44 /* long */
-#define DMA_TCR0 0x05ffff4a /* short */
-#define DMA_CHCR0 0x05ffff4e /* short */
-
- /*DMAC CHANNEL 1*/
-#define DMA_SAR1 0x05ffff50 /* long */
-#define DMA_DAR1 0x05ffff54 /* long */
-#define DMA_TCR1 0x05fffF5a /* short */
-#define DMA_CHCR1 0x05ffff5e /* short */
-
- /*DMAC CHANNEL 3*/
-#define DMA_SAR3 0x05ffff60 /* long */
-#define DMA_DAR3 0x05ffff64 /* long */
-#define DMA_TCR3 0x05fffF6a /* short */
-#define DMA_CHCR3 0x05ffff6e /* short */
-
-/*DMAC CHANNEL 4*/
-#define DMA_SAR4 0x05ffff70 /* long */
-#define DMA_DAR4 0x05ffff74 /* long */
-#define DMA_TCR4 0x05fffF7a /* short */
-#define DMA_CHCR4 0x05ffff7e /* short */
-
-/*INTC*/
-#define INTC_IPRA 0x05ffff84 /* short */
-#define INTC_IPRB 0x05ffff86 /* short */
-#define INTC_IPRC 0x05ffff88 /* short */
-#define INTC_IPRD 0x05ffff8A /* short */
-#define INTC_IPRE 0x05ffff8C /* short */
-#define INTC_ICR 0x05ffff8E /* short */
-
-/*UBC*/
-#define UBC_BARH 0x05ffff90 /* short */
-#define UBC_BARL 0x05ffff92 /* short */
-#define UBC_BAMRH 0x05ffff94 /* short */
-#define UBC_BAMRL 0x05ffff96 /* short */
-#define UBC_BBR 0x05ffff98 /* short */
-
-/*BSC*/
-#define BSC_BCR 0x05ffffA0 /* short */
-#define BSC_WCR1 0x05ffffA2 /* short */
-#define BSC_WCR2 0x05ffffA4 /* short */
-#define BSC_WCR3 0x05ffffA6 /* short */
-#define BSC_DCR 0x05ffffA8 /* short */
-#define BSC_PCR 0x05ffffAA /* short */
-#define BSC_RCR 0x05ffffAC /* short */
-#define BSC_RTCSR 0x05ffffAE /* short */
-#define BSC_RTCNT 0x05ffffB0 /* short */
-#define BSC_RTCOR 0x05ffffB2 /* short */
-
-/*WDT*/
-#define WDT_TCSR 0x05ffffB8 /* char */
-#define WDT_TCNT 0x05ffffB9 /* char */
-#define WDT_RSTCSR 0x05ffffBB /* char */
-
-/*POWER DOWN STATE*/
-#define PDT_SBYCR 0x05ffffBC /* char */
-
-/*PORT A*/
-#define PADR 0x05ffffC0 /* short */
-
-/*PORT B*/
-#define PBDR 0x05ffffC2 /* short */
-
- /*PORT C*/
-#define PCDR 0x05ffffD0 /* short */
-
-/*PFC*/
-#define PFC_PAIOR 0x05ffffC4 /* short */
-#define PFC_PBIOR 0x05ffffC6 /* short */
-#define PFC_PACR1 0x05ffffC8 /* short */
-#define PFC_PACR2 0x05ffffCA /* short */
-#define PFC_PBCR1 0x05ffffCC /* short */
-#define PFC_PBCR2 0x05ffffCE /* short */
-#define PFC_CASCR 0x05ffffEE /* short */
-
-/*TPC*/
-#define TPC_TPMR 0x05ffffF0 /* short */
-#define TPC_TPCR 0x05ffffF1 /* short */
-#define TPC_NDERH 0x05ffffF2 /* short */
-#define TPC_NDERL 0x05ffffF3 /* short */
-#define TPC_NDRB 0x05ffffF4 /* char */
-#define TPC_NDRA 0x05ffffF5 /* char */
-#define TPC_NDRB1 0x05ffffF6 /* char */
-#define TPC_NDRA1 0x05ffffF7 /* char */
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h
deleted file mode 100644
index 62918dd958..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
- * contained no copyright notice.
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * Modified to reflect on-chip registers for sh7045 processor, based on
- * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
- * contained no copyright notice:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- * August, 1999
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- *
- * $Id$
- */
-
-#ifndef __IOSH7045_H
-#define __IOSH7045_H
-
-/*
- * After each line is explained whether the access is char short or long.
- * The functions read/writeb, w, l, 8, 16, 32 can be found
- * in exec/score/cpu/sh/sh_io.h
- *
- * 8 bit == char ( readb, writeb, read8, write8)
- * 16 bit == short ( readw, writew, read16, write16 )
- * 32 bit == long ( readl, writel, read32, write32 )
- * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
- * ENGINE_..Hardware_Manual; alignment access-restrictions may apply
- */
-
-#define REG_BASE 0xFFFF8000
-
-/* SCI0 Registers */
-#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
-#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
-#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
-#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
-#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
-#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
-
-/* SCI1 Registers */
-#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
-#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
-#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
-#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
-#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
-#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
-
-/* ADI */
-/* High Speed A/D (Excluding A-Mask Part)*/
-#define ADDRA (REG_BASE + 0x03F0) /* short */
-#define ADDRB (REG_BASE + 0x03F2) /* short */
-#define ADDRC (REG_BASE + 0x03F4) /* short */
-#define ADDRD (REG_BASE + 0x03F6) /* short */
-#define ADDRE (REG_BASE + 0x03F8) /* short */
-#define ADDRF (REG_BASE + 0x03FA) /* short */
-#define ADDRG (REG_BASE + 0x03FC) /* short */
-#define ADDRH (REG_BASE + 0x03FE) /* short */
-#define ADCSR (REG_BASE + 0x03E0) /* char */
-#define ADCR (REG_BASE + 0x03E1) /* char */
-
-/* Mid-Speed A/D (A-Mask part)*/
-#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
-#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
-#define ADDRA0L (REG_BASE + 0x0401) /* char */
-#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
-#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
-#define ADDRB0L (REG_BASE + 0x0403) /* char */
-#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
-#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
-#define ADDRC0L (REG_BASE + 0x0405) /* char */
-#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
-#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
-#define ADDRD0L (REG_BASE + 0x0407) /* char */
-#define ADCSR0 (REG_BASE + 0x0410) /* char */
-#define ADCR0 (REG_BASE + 0x0412) /* char */
-#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
-#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
-#define ADDRA1L (REG_BASE + 0x0409) /* char */
-#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
-#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
-#define ADDRB1L (REG_BASE + 0x040B) /* char */
-#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
-#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
-#define ADDRC1L (REG_BASE + 0x040D) /* char */
-#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
-#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
-#define ADDRD1L (REG_BASE + 0x040F) /* char */
-#define ADCSR1 (REG_BASE + 0x0411) /* char */
-#define ADCR1 (REG_BASE + 0x0413) /* char */
-
-/*MTU SHARED*/
-#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
-#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
-#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
-#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
-
-/*MTU CHANNEL 0*/
-#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
-#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
-#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
-#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
-#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
-#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
-#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
-#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
-#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
-#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
-#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
-
-/*MTU CHANNEL 1*/
-#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
-#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
-#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
-#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
-#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
-#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
-#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
-#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
-
-/*MTU CHANNEL 2*/
-#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
-#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
-#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
-#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
-#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
-#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
-#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
-#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
-
-/*MTU CHANNELS 3-4 SHARED*/
-#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
-#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
-#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
-#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
-#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
-#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
-#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
-
-/*MTU CHANNEL 3*/
-#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
-#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
-#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
-#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
-#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
-#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
-#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
-#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
-#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
-#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
-#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
-
-/*MTU CHANNEL 4*/
-#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
-#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
-#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
-#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
-#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
-#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
-#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
-#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
-#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
-#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
-#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
-#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
-
-/*DMAC CHANNELS 0-3 SHARED*/
-#define DMAOR (REG_BASE + 0x06B0) /* short */
-
-/*DMAC CHANNEL 0*/
-#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
-#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
-#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
-#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
-
-/*DMAC CHANNEL 1*/
-#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
-#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
-#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
-#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
-
-/*DMAC CHANNEL 3*/
-#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
-#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
-#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
-#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
-
-/*DMAC CHANNEL 4*/
-#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
-#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
-#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
-#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
-
-/*Data Transfer Controller*/
-#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
-#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
-#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
-#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
-#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
-#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
-#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
-
-/*Cache Memory*/
-#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
-
-/*INTC*/
-#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
-#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
-#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
-#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
-#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
-#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
-#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
-#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
-#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
-#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
-
-/*Flash (F-ZTAT)*/
-#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
-#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
-#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
-#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
-#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
-
-/*UBC*/
-#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
-#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
-#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
-#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
-#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
-/*BSC*/
-#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
-#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
-#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
-#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
-#define BSC_DCR (REG_BASE + 0x062A) /* short */
-#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
-#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
-#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
-
-/*WDT*/
-#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
-#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
-#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
-#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
-#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
-#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
-
-/*POWER DOWN STATE*/
-#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
-
-/* Port I/O Control Registers */
-#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
-#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
-#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
-#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
-#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
-#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
-#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
-#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
-
-/*Pin Function Control Register*/
-#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
-#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
-#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
-#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
-#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
-#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
-#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
-#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
-#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
-#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
-#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
-#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
-#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
-#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
-#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
-#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
-#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
-#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
-#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
-
-/*Compare/Match Timer*/
-#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
-#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
-#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
-#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
-#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
-#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
-#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h
deleted file mode 100644
index 3f9baf1ad2..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __CPU_ISPS_H
-#define __CPU_ISPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/shtypes.h>
-
-extern void __ISR_Handler( unsigned32 vector );
-
-
-/*
- * interrupt vector table offsets
- */
-#define NMI_ISP_V 11
-#define USB_ISP_V 12
-#define IRQ0_ISP_V 64
-#define IRQ1_ISP_V 65
-#define IRQ2_ISP_V 66
-#define IRQ3_ISP_V 67
-#define IRQ4_ISP_V 68
-#define IRQ5_ISP_V 69
-#define IRQ6_ISP_V 70
-#define IRQ7_ISP_V 71
-#define DMA0_ISP_V 72
-#define DMA1_ISP_V 74
-#define DMA2_ISP_V 76
-#define DMA3_ISP_V 78
-
-#define IMIA0_ISP_V 80
-#define IMIB0_ISP_V 81
-#define OVI0_ISP_V 82
-
-#define IMIA1_ISP_V 84
-#define IMIB1_ISP_V 85
-#define OVI1_ISP_V 86
-
-#define IMIA2_ISP_V 88
-#define IMIB2_ISP_V 89
-#define OVI2_ISP_V 90
-
-#define IMIA3_ISP_V 92
-#define IMIB3_ISP_V 93
-#define OVI3_ISP_V 94
-
-#define IMIA4_ISP_V 96
-#define IMIB4_ISP_V 97
-#define OVI4_ISP_V 98
-
-#define ERI0_ISP_V 100
-#define RXI0_ISP_V 101
-#define TXI0_ISP_V 102
-#define TEI0_ISP_V 103
-
-#define ERI1_ISP_V 104
-#define RXI1_ISP_V 105
-#define TXI1_ISP_V 106
-#define TEI1_ISP_V 107
-
-#define PRT_ISP_V 108
-#define ADU_ISP_V 109
-#define WDT_ISP_V 112
-#define DREF_ISP_V 113
-
-
-/* dummy ISP */
-extern void _dummy_isp( void );
-
-/* Non Maskable Interrupt */
-extern void _nmi_isp( void );
-
-/* User Break Controller */
-extern void _usb_isp( void );
-
-/* External interrupts 0-7 */
-extern void _irq0_isp( void );
-extern void _irq1_isp( void );
-extern void _irq2_isp( void );
-extern void _irq3_isp( void );
-extern void _irq4_isp( void );
-extern void _irq5_isp( void );
-extern void _irq6_isp( void );
-extern void _irq7_isp( void );
-
-/* DMA - Controller */
-extern void _dma0_isp( void );
-extern void _dma1_isp( void );
-extern void _dma2_isp( void );
-extern void _dma3_isp( void );
-
-/* Interrupt Timer Unit */
-/* Timer 0 */
-extern void _imia0_isp( void );
-extern void _imib0_isp( void );
-extern void _ovi0_isp( void );
-/* Timer 1 */
-extern void _imia1_isp( void );
-extern void _imib1_isp( void );
-extern void _ovi1_isp( void );
-/* Timer 2 */
-extern void _imia2_isp( void );
-extern void _imib2_isp( void );
-extern void _ovi2_isp( void );
-/* Timer 3 */
-extern void _imia3_isp( void );
-extern void _imib3_isp( void );
-extern void _ovi3_isp( void );
-/* Timer 4 */
-extern void _imia4_isp( void );
-extern void _imib4_isp( void );
-extern void _ovi4_isp( void );
-
-/* seriell interfaces */
-extern void _eri0_isp( void );
-extern void _rxi0_isp( void );
-extern void _txi0_isp( void );
-extern void _tei0_isp( void );
-extern void _eri1_isp( void );
-extern void _rxi1_isp( void );
-extern void _txi1_isp( void );
-extern void _tei1_isp( void );
-
-/* Parity Control Unit of the Bus State Controllers */
-extern void _prt_isp( void );
-
-/* ADC */
-extern void _adu_isp( void );
-
-/* Watchdog Timer */
-extern void _wdt_isp( void );
-
-/* DRAM refresh control unit of bus state controller */
-extern void _dref_isp( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h
deleted file mode 100644
index e711bb1a21..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * Modified to reflect isp entries for sh7045 processor:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- *
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- *
- * $Id$
- */
-
-#ifndef __CPU_ISPS_H
-#define __CPU_ISPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/shtypes.h>
-
-extern void __ISR_Handler( unsigned32 vector );
-
-
-/*
- * interrupt vector table offsets
- */
-#define NMI_ISP_V 11
-#define USB_ISP_V 12
-#define IRQ0_ISP_V 64
-#define IRQ1_ISP_V 65
-#define IRQ2_ISP_V 66
-#define IRQ3_ISP_V 67
-#define IRQ4_ISP_V 68
-#define IRQ5_ISP_V 69
-#define IRQ6_ISP_V 70
-#define IRQ7_ISP_V 71
-#define DMA0_ISP_V 72
-#define DMA1_ISP_V 76
-#define DMA2_ISP_V 80
-#define DMA3_ISP_V 84
-
-#define MTUA0_ISP_V 88
-#define MTUB0_ISP_V 89
-#define MTUC0_ISP_V 90
-#define MTUD0_ISP_V 91
-#define MTUV0_ISP_V 92
-
-#define MTUA1_ISP_V 96
-#define MTUB1_ISP_V 97
-#define MTUV1_ISP_V 100
-#define MTUU1_ISP_V 101
-
-#define MTUA2_ISP_V 104
-#define MTUB2_ISP_V 105
-#define MTUV2_ISP_V 108
-#define MTUU2_ISP_V 109
-
-#define MTUA3_ISP_V 112
-#define MTUB3_ISP_V 113
-#define MTUC3_ISP_V 114
-#define MTUD3_ISP_V 115
-#define MTUV3_ISP_V 116
-
-#define MTUA4_ISP_V 120
-#define MTUB4_ISP_V 121
-#define MTUC4_ISP_V 122
-#define MTUD4_ISP_V 123
-#define MTUV4_ISP_V 124
-
-#define ERI0_ISP_V 128
-#define RXI0_ISP_V 129
-#define TXI0_ISP_V 130
-#define TEI0_ISP_V 131
-
-#define ERI1_ISP_V 132
-#define RXI1_ISP_V 133
-#define TXI1_ISP_V 134
-#define TEI1_ISP_V 135
-
-#define ADI0_ISP_V 136
-#define ADI1_ISP_V 137
-#define DTC_ISP_V 140 /* Data Transfer Controller */
-#define CMT0_ISP_V 144 /* Compare Match Timer */
-#define CMT1_ISP_V 148
-#define WDT_ISP_V 152 /* Wtachdog Timer */
-#define CMI_ISP_V 153 /* BSC RAS interrupt */
-#define OEI_ISP_V 156 /* I/O Port */
-#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
-#if 0
-#define PRT_ISP_V /* parity error - no equivalent */
-#endif
-
-/* dummy ISP */
-extern void _dummy_isp( void );
-
-/* Non Maskable Interrupt */
-extern void _nmi_isp( void );
-
-/* User Break Controller */
-extern void _usb_isp( void );
-
-/* External interrupts 0-7 */
-extern void _irq0_isp( void );
-extern void _irq1_isp( void );
-extern void _irq2_isp( void );
-extern void _irq3_isp( void );
-extern void _irq4_isp( void );
-extern void _irq5_isp( void );
-extern void _irq6_isp( void );
-extern void _irq7_isp( void );
-
-/* DMA - Controller */
-extern void _dma0_isp( void );
-extern void _dma1_isp( void );
-extern void _dma2_isp( void );
-extern void _dma3_isp( void );
-
-/* Interrupt Timer Unit */
-/* Timer 0 */
-extern void _mtua0_isp( void );
-extern void _mtub0_isp( void );
-extern void _mtuc0_isp( void );
-extern void _mtud0_isp( void );
-extern void _mtuv0_isp( void );
-/* Timer 1 */
-extern void _mtua1_isp( void );
-extern void _mtub1_isp( void );
-extern void _mtuv1_isp( void );
-extern void _mtuu1_isp( void );
-/* Timer 2 */
-extern void _mtua2_isp( void );
-extern void _mtub2_isp( void );
-extern void _mtuv2_isp( void );
-extern void _mtuu2_isp( void );
-/* Timer 3 */
-extern void _mtua3_isp( void );
-extern void _mtub3_isp( void );
-extern void _mtuc3_isp( void );
-extern void _mtud3_isp( void );
-extern void _mtuv3_isp( void );
-/* Timer 4 */
-extern void _mtua4_isp( void );
-extern void _mtub4_isp( void );
-extern void _mtuc4_isp( void );
-extern void _mtud4_isp( void );
-extern void _mtuv4_isp( void );
-
-/* serial interfaces */
-extern void _eri0_isp( void );
-extern void _rxi0_isp( void );
-extern void _txi0_isp( void );
-extern void _tei0_isp( void );
-extern void _eri1_isp( void );
-extern void _rxi1_isp( void );
-extern void _txi1_isp( void );
-extern void _tei1_isp( void );
-
-/* ADC */
-extern void _adi0_isp( void );
-extern void _adi1_isp( void );
-
-/* Data Transfer Controller */
-extern void _dtci_isp( void );
-
-/* Compare Match Timer */
-extern void _cmt0_isp( void );
-extern void _cmt1_isp( void );
-
-/* Watchdog Timer */
-extern void _wdt_isp( void );
-
-/* DRAM refresh control unit of bus state controller */
-extern void _bsc_isp( void );
-
-/* I/O Port */
-extern void _oei_isp( void );
-
-/* Parity Control Unit of the Bus State Controllers */
-/* extern void _prt_isp( void ); */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h
index 26c633c190..2834ea6c64 100644
--- a/c/src/exec/score/cpu/sh/rtems/score/sh.h
+++ b/c/src/exec/score/cpu/sh/rtems/score/sh.h
@@ -40,6 +40,7 @@ extern "C" {
*/
#if defined(rtems_multilib)
+
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
@@ -49,19 +50,19 @@ extern "C" {
#define SH_HAS_FPU 0
#define SH_HAS_SEPARATE_STACKS 1
-#elif defined(sh7032)
-#define CPU_MODEL_NAME "SH7032"
-#define SH_HAS_FPU 0
-
-#elif defined (sh7045)
-#define CPU_MODEL_NAME "SH7045"
-#define SH_HAS_FPU 0
+#else
+#if defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
+#define SH_HAS_FPU 0
#else
-#error "Unsupported CPU Model"
-
+#define SH_HAS_FPU 1
#endif
+/* this should not be here */
+#define CPU_MODEL_NAME "SH-Multilib"
+
+#endif /* multilib */
+
/*
* If the following macro is set to 0 there will be no software irq stack
*/
diff --git a/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.am b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.am
index c9dc062751..d6337b6fb1 100644
--- a/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.am
+++ b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.am
@@ -9,7 +9,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
BSP_PIECES = startup scitab console
# pieces to pick up out of libcpu/sh/sh7032
-CPU_PIECES = null clock timer sci delay
+CPU_PIECES = null clock timer sci delay score
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \
diff --git a/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.am b/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.am
index 3f58ecd4c3..3aa6d04aec 100644
--- a/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.am
+++ b/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.am
@@ -9,7 +9,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
BSP_PIECES = startup scitab console
# pieces to pick up out of libcpu/sh
-CPU_PIECES = null clock timer sci
+CPU_PIECES = null clock timer sci score
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \
diff --git a/c/src/lib/libcpu/sh/Makefile.am b/c/src/lib/libcpu/sh/Makefile.am
index 8de599ce50..a5932e55dd 100644
--- a/c/src/lib/libcpu/sh/Makefile.am
+++ b/c/src/lib/libcpu/sh/Makefile.am
@@ -5,7 +5,7 @@
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
-SUBDIRS = @RTEMS_CPU_MODEL@
+SUBDIRS = @subdirs@
include $(top_srcdir)/../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/configure.in b/c/src/lib/libcpu/sh/configure.in
index fbf6fbca9e..664b64f105 100644
--- a/c/src/lib/libcpu/sh/configure.in
+++ b/c/src/lib/libcpu/sh/configure.in
@@ -20,25 +20,14 @@ RTEMS_CANONICAL_HOST
RTEMS_PROJECT_ROOT
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_CANONICALIZE_TOOLS
-
RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
+if test -d ${srcdir}/$RTEMS_CPU_MODEL; then
+RTEMS_CPU_MODEL_SUBDIR="$RTEMS_CPU_MODEL"
+fi
+AC_CONFIG_SUBDIRS($RTEMS_CPU_MODEL_SUBDIR)
+
# Explicitly list all Makefiles here
AC_OUTPUT(
-Makefile
-sh7032/Makefile
-sh7032/null/Makefile
-sh7032/clock/Makefile
-sh7032/delay/Makefile
-sh7032/include/Makefile
-sh7032/timer/Makefile
-sh7032/sci/Makefile
-sh7045/Makefile
-sh7045/clock/Makefile
-sh7045/include/Makefile
-sh7045/null/Makefile
-sh7045/sci/Makefile
-sh7045/timer/Makefile)
+Makefile)
diff --git a/c/src/lib/libcpu/sh/sh7032/Makefile.am b/c/src/lib/libcpu/sh/sh7032/Makefile.am
index ad159e941c..1784127471 100644
--- a/c/src/lib/libcpu/sh/sh7032/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/Makefile.am
@@ -3,8 +3,9 @@
##
AUTOMAKE_OPTIONS = foreign 1.4
+ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
-SUBDIRS = include clock timer null sci delay
+SUBDIRS = include score clock timer null sci delay
-include $(top_srcdir)/../../../../../automake/subdirs.am
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/subdirs.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/clock/Makefile.am b/c/src/lib/libcpu/sh/sh7032/clock/Makefile.am
index 10ae91df8f..141e462aa2 100644
--- a/c/src/lib/libcpu/sh/sh7032/clock/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/clock/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = ckinit.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/configure.in b/c/src/lib/libcpu/sh/sh7032/configure.in
new file mode 100644
index 0000000000..af39508c83
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/configure.in
@@ -0,0 +1,38 @@
+dnl Process this file with autoconf to produce a configure script.
+dnl
+dnl $Id$
+
+AC_PREREQ(2.13)
+AC_INIT(include)
+RTEMS_TOP(../../../../../..)
+AC_CONFIG_AUX_DIR(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+
+AM_INIT_AUTOMAKE(rtems-c-src-lib-libcpu-sh-sh7032,$RTEMS_VERSION,no)
+AM_MAINTAINER_MODE
+
+RTEMS_ENABLE_BARE
+RTEMS_ENV_RTEMSBSP
+
+RTEMS_CHECK_CPU
+RTEMS_CANONICAL_HOST
+
+RTEMS_PROJECT_ROOT
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+
+RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
+RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
+
+# Explicitly list all Makefiles here
+AC_OUTPUT(
+Makefile
+null/Makefile
+clock/Makefile
+delay/Makefile
+include/Makefile
+score/Makefile
+timer/Makefile
+sci/Makefile)
diff --git a/c/src/lib/libcpu/sh/sh7032/delay/Makefile.am b/c/src/lib/libcpu/sh/sh7032/delay/Makefile.am
index 44ff144b86..a67cc2c112 100644
--- a/c/src/lib/libcpu/sh/sh7032/delay/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/delay/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = delay.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/include/Makefile.am b/c/src/lib/libcpu/sh/sh7032/include/Makefile.am
index 7d26513f10..b44d68d5c3 100644
--- a/c/src/lib/libcpu/sh/sh7032/include/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/include/Makefile.am
@@ -5,6 +5,7 @@
AUTOMAKE_OPTIONS = foreign 1.4
H_FILES = null.h sci.h sh7_pfc.h sh7_sci.h
+SCORE_H_FILES= ispsh7032.h iosh7032.h
# NOTE: Unlike other CPUS, we install into a subdirectory to avoid
# file name conflicts
@@ -15,11 +16,15 @@ $(PROJECT_INCLUDE)/sh:
$(PROJECT_INCLUDE)/sh/%.h: %.h
$(INSTALL_DATA) $< $@
+$(PROJECT_INCLUDE)/rtems/score/%.h: %.h
+ $(INSTALL_DATA) $< $@
+
TMPINSTALL_FILES += $(PROJECT_INCLUDE)/sh \
- $(H_FILES:%=$(PROJECT_INCLUDE)/sh/%)
+ $(H_FILES:%.h=$(PROJECT_INCLUDE)/sh/%.h) \
+ $(SCORE_H_FILES:%.h=$(PROJECT_INCLUDE)/rtems/score/%.h)
all-local: $(TMPINSTALL_FILES)
EXTRA_DIST = null.h sci.h sh7_pfc.h sh7_sci.h
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/null/Makefile.am b/c/src/lib/libcpu/sh/sh7032/null/Makefile.am
index 2e6baea4a3..81c3843a69 100644
--- a/c/src/lib/libcpu/sh/sh7032/null/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/null/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = close.c cntrl.c init.c open.c read.c write.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/sci/Makefile.am b/c/src/lib/libcpu/sh/sh7032/sci/Makefile.am
index aef7e13b3b..4a0da51e27 100644
--- a/c/src/lib/libcpu/sh/sh7032/sci/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/sci/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = sci.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/score/Makefile.am b/c/src/lib/libcpu/sh/sh7032/score/Makefile.am
new file mode 100644
index 0000000000..2c4e423fbe
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7032/score/Makefile.am
@@ -0,0 +1,30 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/score.rel
+
+C_FILES = cpu_asm.c ispsh7032.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+OBJS = $(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(OBJS)
+ $(make-rel)
+
+all-local: $(ARCH) $(OBJS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = ispsh7032.c
+
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
index 192c2f43d2..41c2c07475 100644
--- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
@@ -43,14 +43,8 @@
#include <rtems/score/thread.h>
#include <rtems/score/sh.h>
-#if defined(sh7032)
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
-#elif defined (sh7045)
-#include <rtems/score/ispsh7045.h>
-#include <rtems/score/iosh7045.h>
-#endif
-
#include <rtems/score/sh_io.h>
/* from cpu_isps.c */
diff --git a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
index 9fcc9badbf..b8e443ea00 100644
--- a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
+++ b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
@@ -32,10 +32,6 @@
#include <rtems/score/shtypes.h>
#include <rtems/score/ispsh7032.h>
-#if !defined(sh7032)
-#error Wrong CPU MODEL
-#endif
-
/*
* This is an exception vector table
*
diff --git a/c/src/lib/libcpu/sh/sh7032/timer/Makefile.am b/c/src/lib/libcpu/sh/sh7032/timer/Makefile.am
index 5a164c0d4c..a32b9f1c7b 100644
--- a/c/src/lib/libcpu/sh/sh7032/timer/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7032/timer/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = timer.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/Makefile.am b/c/src/lib/libcpu/sh/sh7045/Makefile.am
index 5452a07131..3384644485 100644
--- a/c/src/lib/libcpu/sh/sh7045/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/Makefile.am
@@ -3,8 +3,9 @@
##
AUTOMAKE_OPTIONS = foreign 1.4
+ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
-SUBDIRS = include clock sci timer null
+SUBDIRS = include score clock sci timer null
-include $(top_srcdir)/../../../../../automake/subdirs.am
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/subdirs.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/clock/Makefile.am b/c/src/lib/libcpu/sh/sh7045/clock/Makefile.am
index 10ae91df8f..141e462aa2 100644
--- a/c/src/lib/libcpu/sh/sh7045/clock/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/clock/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = ckinit.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/configure.in b/c/src/lib/libcpu/sh/sh7045/configure.in
new file mode 100644
index 0000000000..604255d64f
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/configure.in
@@ -0,0 +1,37 @@
+dnl Process this file with autoconf to produce a configure script.
+dnl
+dnl $Id$
+
+AC_PREREQ(2.13)
+AC_INIT(include)
+RTEMS_TOP(../../../../../..)
+AC_CONFIG_AUX_DIR(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+
+AM_INIT_AUTOMAKE(rtems-c-src-lib-libcpu-sh-sh7045,$RTEMS_VERSION,no)
+AM_MAINTAINER_MODE
+
+RTEMS_ENABLE_BARE
+RTEMS_ENV_RTEMSBSP
+
+RTEMS_CHECK_CPU
+RTEMS_CANONICAL_HOST
+
+RTEMS_PROJECT_ROOT
+
+RTEMS_PROG_CC_FOR_TARGET
+RTEMS_CANONICALIZE_TOOLS
+
+RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
+RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
+
+# Explicitly list all Makefiles here
+AC_OUTPUT(
+Makefile
+clock/Makefile
+include/Makefile
+score/Makefile
+null/Makefile
+sci/Makefile
+timer/Makefile)
diff --git a/c/src/lib/libcpu/sh/sh7045/include/Makefile.am b/c/src/lib/libcpu/sh/sh7045/include/Makefile.am
index 8a424d634f..4a311c6547 100644
--- a/c/src/lib/libcpu/sh/sh7045/include/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/include/Makefile.am
@@ -5,6 +5,7 @@
AUTOMAKE_OPTIONS = foreign 1.4
H_FILES = io_types.h null.h sci.h sh7_pfc.h sh7_sci.h
+SCORE_H_FILES = ispsh7045.h iosh7045.h
# NOTE: Unlike other CPUS, we install into a subdirectory to avoid
# file name conflicts
@@ -15,11 +16,15 @@ $(PROJECT_INCLUDE)/sh:
$(PROJECT_INCLUDE)/sh/%.h: %.h
$(INSTALL_DATA) $< $@
+$(PROJECT_INCLUDE)/rtems/score/%.h: %.h
+ $(INSTALL_DATA) $< $@
+
TMPINSTALL_FILES += $(PROJECT_INCLUDE)/sh \
- $(H_FILES:%=$(PROJECT_INCLUDE)/sh/%)
+ $(H_FILES:%.h=$(PROJECT_INCLUDE)/sh/%.h) \
+ $(SCORE_H_FILES:%.h=$(PROJECT_INCLUDE)/rtems/score/%.h)
all-local: $(TMPINSTALL_FILES)
EXTRA_DIST = io_types.h null.h sci.h sh7_pfc.h sh7_sci.h
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/null/Makefile.am b/c/src/lib/libcpu/sh/sh7045/null/Makefile.am
index 2e6baea4a3..81c3843a69 100644
--- a/c/src/lib/libcpu/sh/sh7045/null/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/null/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = close.c cntrl.c init.c open.c read.c write.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/sci/Makefile.am b/c/src/lib/libcpu/sh/sh7045/sci/Makefile.am
index aef7e13b3b..4a0da51e27 100644
--- a/c/src/lib/libcpu/sh/sh7045/sci/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/sci/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = sci.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/score/Makefile.am b/c/src/lib/libcpu/sh/sh7045/score/Makefile.am
new file mode 100644
index 0000000000..fc26b10368
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/score/Makefile.am
@@ -0,0 +1,30 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = $(ARCH)/score.rel
+
+C_FILES = cpu_asm.c ispsh7045.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+OBJS = $(C_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(OBJS)
+ $(make-rel)
+
+all-local: $(ARCH) $(OBJS) $(PGM)
+
+.PRECIOUS: $(PGM)
+
+EXTRA_DIST = ispsh7045.c
+
+include $(top_srcdir)/../../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
index 192c2f43d2..6453105bdb 100644
--- a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
@@ -43,14 +43,8 @@
#include <rtems/score/thread.h>
#include <rtems/score/sh.h>
-#if defined(sh7032)
-#include <rtems/score/ispsh7032.h>
-#include <rtems/score/iosh7032.h>
-#elif defined (sh7045)
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
-#endif
-
#include <rtems/score/sh_io.h>
/* from cpu_isps.c */
diff --git a/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c b/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
index 4009ea152a..44aeaff8f1 100644
--- a/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
+++ b/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
@@ -43,10 +43,6 @@
#include <rtems/system.h>
#include <rtems/score/shtypes.h>
-#if !defined (sh7045)
-#error Wrong CPU MODEL
-#endif
-
/*
* This is a exception vector table
*
diff --git a/c/src/lib/libcpu/sh/sh7045/timer/Makefile.am b/c/src/lib/libcpu/sh/sh7045/timer/Makefile.am
index 5a164c0d4c..a32b9f1c7b 100644
--- a/c/src/lib/libcpu/sh/sh7045/timer/Makefile.am
+++ b/c/src/lib/libcpu/sh/sh7045/timer/Makefile.am
@@ -12,7 +12,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/lib.am
+include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
@@ -27,4 +27,4 @@ all-local: $(ARCH) $(OBJS) $(PGM)
EXTRA_DIST = timer.c
-include $(top_srcdir)/../../../../../automake/local.am
+include $(top_srcdir)/../../../../../../automake/local.am