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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-10-23 14:11:17 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-10-23 14:19:47 +0200 |
| commit | 8c66f1aa061c67301fdb0571384ef0033bc39af7 (patch) | |
| tree | 28b2af652c14a40fd0a0817efaa7ca167c2c3a2b /c/src | |
| parent | bsp/xilinx-zynqmp: Simplify linkcmds config (diff) | |
| download | rtems-8c66f1aa061c67301fdb0571384ef0033bc39af7.tar.bz2 | |
bsp/xilinx-zynq: Simplify configure.ac
Diffstat (limited to 'c/src')
| -rw-r--r-- | c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 34 |
1 files changed, 10 insertions, 24 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac index f58b737b1b..8876055b48 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac +++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @@ -73,49 +73,35 @@ RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M]) RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region]) +ZYNQ_RAM_MMU_LENGTH="16k" +ZYNQ_RAM_INT_0_ORIGIN="0x00000000" +ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" +ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" +ZYNQ_RAM_INT_1_LENGTH="64k - 512" + AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [ZYNQ_RAM_ORIGIN="0x00000000" ZYNQ_RAM_MMU="0x0fffc000" - ZYNQ_RAM_MMU_LENGTH="16k" ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}" - ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k" - ZYNQ_RAM_INT_0_ORIGIN="0x00000000" - ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" - ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" - ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"]) AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702], [ZYNQ_RAM_ORIGIN="0x00100000" ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" - ZYNQ_RAM_MMU_LENGTH="16k" ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" - ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" - ZYNQ_RAM_INT_0_ORIGIN="0x00000000" - ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" - ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" - ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"]) AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706], [ZYNQ_RAM_ORIGIN="0x00400000" ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" - ZYNQ_RAM_MMU_LENGTH="16k" ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" - ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k" - ZYNQ_RAM_INT_0_ORIGIN="0x00000000" - ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" - ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" - ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"]) AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard], [ZYNQ_RAM_ORIGIN="0x00100000" ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" - ZYNQ_RAM_MMU_LENGTH="16k" ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" - ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" - ZYNQ_RAM_INT_0_ORIGIN="0x00000000" - ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" - ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" - ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"]) AC_DEFUN([ZYNQ_LINKCMD],[ AC_ARG_VAR([$1],[$2; default $3])dnl |