Replacement for the sis bsp which supports the simulator and real

hardware.  From Jiri Gaisler <jgais@wd.estec.esa.nl>.  Supports sis
2.6 and later.

4 files changed, 1184 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
new file mode 100644
index 0000000000..2a391228c7
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
@@ -0,0 +1,262 @@
+/*
+ *  Clock Tick Device Driver
+ *
+ *  This routine initializes the Real Time Clock Counter Timer which is
+ *  part of the MEC on the ERC32 CPU.
+ *
+ *  The tick frequency is directly programmed to the configured number of
+ *  microseconds per tick.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#include <stdlib.h>
+
+#include <bsp.h>
+#include <rtems/libio.h>
+
+/*
+ *  The Real Time Clock Counter Timer uses this trap type.
+ */
+
+#define CLOCK_VECTOR ERC32_TRAP_TYPE( ERC32_INTERRUPT_REAL_TIME_CLOCK )
+
+/*
+ *  Clock ticks since initialization
+ */
+
+volatile rtems_unsigned32 Clock_driver_ticks;
+
+/*
+ *  This is the value programmed into the count down timer.  It
+ *  is artificially lowered when SIMSPARC_FAST_IDLE is defined to
+ *  cut down how long we spend in the idle task while executing on
+ *  the simulator.
+ */
+
+extern rtems_unsigned32 CPU_SPARC_CLICKS_PER_TICK;
+
+rtems_isr_entry  Old_ticker;
+
+void Clock_exit( void );
+ 
+/*
+ * These are set by clock driver during its init
+ */
+ 
+rtems_device_major_number rtems_clock_major = ~0;
+rtems_device_minor_number rtems_clock_minor;
+
+/*
+ *  Clock_isr
+ *
+ *  This is the clock tick interrupt handler.
+ *
+ *  Input parameters:
+ *    vector - vector number
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ *
+ */
+
+rtems_isr Clock_isr(
+  rtems_vector_number vector
+)
+{
+  /*
+   *  If we are in "fast idle" mode, then the value for clicks per tick
+   *  is lowered to decrease the amount of time spent executing the idle
+   *  task while using the SPARC Instruction Simulator.
+   */
+
+#if SIMSPARC_FAST_IDLE
+  ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
+  ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
+    ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
+      ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
+  );
+#endif
+
+  /*
+   *  The driver has seen another tick.
+   */
+
+  Clock_driver_ticks += 1;
+
+  /*
+   *  Real Time Clock counter/timer is set to automatically reload.
+   */
+
+  rtems_clock_tick();
+}
+
+/*
+ *  Install_clock
+ *
+ *  This routine actually performs the hardware initialization for the clock.
+ *
+ *  Input parameters:
+ *    clock_isr - clock interrupt service routine entry point
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ *
+ */
+
+extern int CLOCK_SPEED;
+
+void Install_clock(
+  rtems_isr_entry clock_isr
+)
+{
+  Clock_driver_ticks = 0;
+
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+    Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
+
+    /* approximately 1 us per countdown */
+    ERC32_MEC.Real_Time_Clock_Scalar  = CLOCK_SPEED - 1;
+    ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
+
+    ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
+      ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | 
+        ERC32_MEC_TIMER_COUNTER_LOAD_SCALER | 
+        ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 
+    );
+ 
+    ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
+      ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
+        ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 
+    );
+
+    atexit( Clock_exit );
+  }
+
+}
+
+/*
+ *  Clock_exit
+ *
+ *  This routine allows the clock driver to exit by masking the interrupt and
+ *  disabling the clock's counter.
+ *
+ *  Input parameters:   NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ *
+ */
+
+void Clock_exit( void )
+{
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+    ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
+
+    ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
+      ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 
+    );
+
+    /* do not restore old vector */
+  }
+}
+ 
+/*
+ *  Clock_initialize
+ *
+ *  This routine initializes the clock driver.
+ *
+ *  Input parameters:
+ *    major - clock device major number
+ *    minor - clock device minor number
+ *    parg  - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+
+rtems_device_driver Clock_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  Install_clock( Clock_isr );
+ 
+  /*
+   * make major/minor avail to others such as shared memory driver
+   */
+ 
+  rtems_clock_major = major;
+  rtems_clock_minor = minor;
+ 
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  Clock_control
+ *
+ *  This routine is the clock device driver control entry point.
+ *
+ *  Input parameters:
+ *    major - clock device major number
+ *    minor - clock device minor number
+ *    parg  - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+
+rtems_device_driver Clock_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+    rtems_unsigned32 isrlevel;
+    rtems_libio_ioctl_args_t *args = pargp;
+ 
+    if (args == 0)
+        goto done;
+ 
+    /*
+     * This is hokey, but until we get a defined interface
+     * to do this, it will just be this simple...
+     */
+ 
+    if (args->command == rtems_build_name('I', 'S', 'R', ' '))
+    {
+        Clock_isr(CLOCK_VECTOR);
+    }
+    else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
+    {
+      rtems_interrupt_disable( isrlevel );
+       (void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
+      rtems_interrupt_enable( isrlevel );
+    }
+ 
+done:
+    return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/sparc/erc32/console/console.c b/c/src/lib/libbsp/sparc/erc32/console/console.c
new file mode 100644
index 0000000000..41cea543a4
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/console/console.c
@@ -0,0 +1,630 @@
+/*
+ *  console.c
+ *
+ *  This file contains the Sparc Instruction Simulator Console driver.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <stdlib.h>
+
+/*
+ *  Define RDB_BREAK_IN if you need to be able to break in to the
+ *  program with a ctrl-c during remote target debugging. If so,
+ *  UART B will not be accessible from rtems during remote debugging
+ *  if interrupt driven console is used. Does not affect UART A, polled 
+ *  mode or when the program runs without remote debugging.
+ */
+
+#define RDB_BREAK_IN
+
+/*
+ *  This is a kludge so the tests run without stopping to ask for input.
+ *  It makes it possible to run the RTEMS tests without human intervention.
+ */
+
+/*
+#define CONSOLE_FAKE_INPUT
+*/
+
+/*
+ *  Should we use a polled or interrupt drived console?
+ *  
+ *  NOTE: Define only one of these by default.
+ *
+ *  WARNING:  As of sis 1.6, it did not appear that the UART interrupts
+ *            worked in a desirable fashion.  Immediately upon writing
+ *            a character into the TX buffer, an interrupt was generated.
+ *            This did not allow enough time for the program to put more
+ *            characters in the buffer.  So every character resulted in
+ *            "priming" the transmitter.   This effectively results in 
+ *            in a polled console with a useless interrupt per character
+ *            on output.  It is reasonable to assume that input does not
+ *            share this problem although it was not investigated.
+ */
+
+#define CONSOLE_USE_INTERRUPTS
+
+/*
+#define CONSOLE_USE_POLLED
+*/
+
+#ifdef CONSOLE_USE_POLLED
+#define OUTBYTE console_outbyte_polled
+#define INBYTE  console_inbyte_polled
+#else
+#define OUTBYTE console_outbyte_interrupts
+#define INBYTE  console_inbyte_interrupts
+#endif
+
+void console_initialize_interrupts( void );
+
+/*  console_initialize
+ *
+ *  This routine initializes the console IO driver.
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+ 
+rtems_device_driver console_initialize(
+  rtems_device_major_number  major,
+  rtems_device_minor_number  minor,
+  void                      *arg
+)
+{
+  rtems_status_code status;
+ 
+  status = rtems_io_register_name(
+    "/dev/console",
+    major,
+    (rtems_device_minor_number) 0
+  );
+ 
+  if (status != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred(status);
+
+#ifdef CONSOLE_USE_INTERRUPTS
+  console_initialize_interrupts();
+#endif
+ 
+  return RTEMS_SUCCESSFUL;
+}
+
+/*  console_inbyte_polled
+ *
+ *  This routine reads a character from the UART.
+ *
+ *  Input parameters:
+ *    port - port to read character from
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    character read from UART
+ */
+
+char console_inbyte_polled( int port )
+{
+  int UStat;
+
+  if ( port == 0 ) {
+    while (((UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRA) == 0 )
+	if (UStat & ERC32_MEC_UART_STATUS_ERRA) {
+	    ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRA;
+	    ERC32_MEC.Control = ERC32_MEC.Control;
+	}
+    return (int) ERC32_MEC.UART_Channel_A;
+  } 
+
+  while (((UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRB) == 0 )
+	if (UStat & ERC32_MEC_UART_STATUS_ERRB) {
+	    ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRB;
+	    ERC32_MEC.Control = ERC32_MEC.Control;
+	}
+  return (int) ERC32_MEC.UART_Channel_B;
+}
+
+
+/*  console_outbyte_polled
+ *
+ *  This routine transmits a character out.
+ *
+ *  Input parameters:
+ *    port - port to transmit character to
+ *    ch  - character to be transmitted
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values: NONE
+ */
+
+void console_outbyte_polled(
+  int  port,
+  char ch
+)
+{
+  if ( port == 0 ) {
+    while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) == 0 );
+    ERC32_MEC.UART_Channel_A = (int) ch;
+    return;
+  }
+
+  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) == 0 );
+  ERC32_MEC.UART_Channel_B = (int) ch;
+}
+
+/*
+ *  Interrupt driven console IO
+ */
+
+#ifdef CONSOLE_USE_INTERRUPTS
+
+/*
+ *  Buffers between task and ISRs
+ */
+
+#include <ringbuf.h>
+ 
+Ring_buffer_t  TX_Buffer[ 2 ];
+Ring_buffer_t  RX_Buffer[ 2 ];
+boolean        Is_TX_active[ 2 ];
+ 
+/*
+ *  console_isr_a
+ *
+ *  This routine is the console interrupt handler for Channel A.
+ *
+ *  Input parameters:
+ *    vector - vector number 
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values:     NONE
+ */
+
+rtems_isr console_isr_a(
+  rtems_vector_number vector
+)
+{ 
+  char ch;
+  int UStat;
+ 
+  if ( (UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRA ) {
+    if (UStat & ERC32_MEC_UART_STATUS_ERRA) {
+      ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRA;
+      ERC32_MEC.Control = ERC32_MEC.Control;
+    }
+    ch = ERC32_MEC.UART_Channel_A;
+    if ( !Ring_buffer_Is_full( &RX_Buffer[ 0 ] ) )
+      Ring_buffer_Add_character( &RX_Buffer[ 0 ], ch );
+    /* else toss it */
+  }
+ 
+  if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA ) {
+    if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
+      Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch );
+      ERC32_MEC.UART_Channel_A = (unsigned32) ch;
+    } else
+     Is_TX_active[ 0 ] = FALSE;
+  }
+ 
+  ERC32_Clear_interrupt( ERC32_INTERRUPT_UART_A_RX_TX );
+}
+
+/*
+ *  console_isr_b
+ *
+ *  This routine is the console interrupt handler for Channel B.
+ *
+ *  Input parameters:
+ *    vector - vector number 
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values:     NONE
+ */
+ 
+rtems_isr console_isr_b(
+  rtems_vector_number vector
+)
+{
+  char ch;
+  int UStat;
+
+  if ( (UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRB ) {
+    if (UStat & ERC32_MEC_UART_STATUS_ERRB) {
+      ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRB;
+      ERC32_MEC.Control = ERC32_MEC.Control;
+    }
+    ch = ERC32_MEC.UART_Channel_B;
+    if ( !Ring_buffer_Is_full( &RX_Buffer[ 1 ] ) )
+      Ring_buffer_Add_character( &RX_Buffer[ 1 ], ch );
+    /* else toss it */
+  }
+
+  if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB ) {
+    if ( !Ring_buffer_Is_empty( &TX_Buffer[ 1 ] ) ) {
+      Ring_buffer_Remove_character( &TX_Buffer[ 1 ], ch );
+      ERC32_MEC.UART_Channel_B = (unsigned32) ch;
+    } else
+     Is_TX_active[ 1 ] = FALSE;
+  }
+
+  ERC32_Clear_interrupt( ERC32_INTERRUPT_UART_B_RX_TX );
+}
+
+/*
+ *  console_exit
+ *
+ *  This routine allows the console to exit by masking its associated interrupt
+ *  vectors.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values:     NONE
+ */
+
+void console_exit()
+{
+  rtems_unsigned32 port;
+  rtems_unsigned32 ch;
+
+  /*
+   *  Although the interrupts for the UART are unmasked, the PIL is set to
+   *  disable all external interrupts.  So we might as well do this first.
+   */
+
+  ERC32_Mask_interrupt( ERC32_INTERRUPT_UART_A_RX_TX );
+  ERC32_Mask_interrupt( ERC32_INTERRUPT_UART_B_RX_TX );
+
+  for ( port=0 ; port <= 1 ; port++ ) {
+    while ( !Ring_buffer_Is_empty( &TX_Buffer[ port ] ) ) {
+      Ring_buffer_Remove_character( &TX_Buffer[ port ], ch );
+      console_outbyte_polled( port, ch );
+    }
+  }
+
+  /*
+   *  Now wait for all the data to actually get out ... the send register
+   *  should be empty.
+   */
+ 
+  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) != 
+          ERC32_MEC_UART_STATUS_THEA );
+
+  while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) != 
+          ERC32_MEC_UART_STATUS_THEB );
+
+}
+
+#define CONSOLE_UART_A_TRAP  ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_A_RX_TX )
+#define CONSOLE_UART_B_TRAP  ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_B_RX_TX )
+
+/*
+ *  console_initialize_interrupts
+ *
+ *  This routine initializes the console's receive and transmit
+ *  ring buffers and loads the appropriate vectors to handle the interrupts.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters: NONE
+ *
+ *  Return values:     NONE
+ */
+
+#ifdef RDB_BREAK_IN
+  extern int trap_table[];
+#endif
+
+void console_initialize_interrupts()
+{
+  Ring_buffer_Initialize( &RX_Buffer[ 0 ] );
+  Ring_buffer_Initialize( &RX_Buffer[ 1 ] );
+
+  Ring_buffer_Initialize( &TX_Buffer[ 0 ] );
+  Ring_buffer_Initialize( &TX_Buffer[ 1 ] );
+
+  Is_TX_active[ 0 ] = FALSE;
+  Is_TX_active[ 1 ] = FALSE;
+
+  atexit( console_exit );
+
+  set_vector( console_isr_a, CONSOLE_UART_A_TRAP, 1 );
+#ifdef RDB_BREAK_IN
+  if (trap_table[0x150/4] == 0x91d02000)
+#endif
+  set_vector( console_isr_b, CONSOLE_UART_B_TRAP, 1 );
+}
+
+/*
+ *  console_inbyte_interrupts
+ *
+ *  This routine reads a character from the UART.
+ *
+ *  Input parameters: NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    character read from UART
+ */
+ 
+char console_inbyte_interrupts( int port )
+{
+  char ch;
+
+  while ( Ring_buffer_Is_empty( &RX_Buffer[ port ] ) );
+ 
+  Ring_buffer_Remove_character( &RX_Buffer[ port ], ch );
+  return ch;
+}
+ 
+/*
+ *  console_outbyte_interrupts
+ *
+ *  This routine transmits a character out.
+ *
+ *  Input parameters:
+ *    port - port to transmit character to
+ *    ch  - character to be transmitted
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+ 
+void console_outbyte_interrupts(
+  int  port,
+  char ch
+)
+{
+  /*
+   *  If this is the first character then we need to prime the pump
+   */
+
+  if ( Is_TX_active[ port ] == FALSE ) {
+    Is_TX_active[ port ] = TRUE;
+    console_outbyte_polled( port, ch );
+    return;
+  }
+
+  while ( Ring_buffer_Is_full( &TX_Buffer[ port ] ) );
+ 
+  Ring_buffer_Add_character( &TX_Buffer[ port ], ch );
+}
+
+#endif /* CONSOLE_USE_INTERRUPTS */
+
+/*
+ *  DEBUG_puts
+ *
+ *  This should be safe in the event of an error.  It attempts to insure
+ *  that no TX empty interrupts occur while it is doing polled IO.  Then
+ *  it restores the state of that external interrupt.
+ *
+ *  Input parameters:
+ *    string  - pointer to debug output string
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+
+void DEBUG_puts(
+  char *string
+)
+{
+  char *s;
+  unsigned32 old_level;
+
+  ERC32_Disable_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level );
+    for ( s = string ; *s ; s++ ) 
+      console_outbyte_polled( 0, *s );
+
+    console_outbyte_polled( 0, '\r' );
+    console_outbyte_polled( 0, '\n' );
+  ERC32_Restore_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level );
+}
+
+
+/*
+ *  console_open
+ *
+ *  This routine is the console device driver open entry point. 
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+ 
+rtems_device_driver console_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  console_close
+ *
+ *  This routine is the console device driver close entry point.
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+ 
+rtems_device_driver console_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  console_read
+ *
+ *  This routine is the console device driver read entry point.
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ *
+ *  NOTE:  Read bytes from the serial port. We only have stdin.
+ */
+ 
+rtems_device_driver console_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+  int maximum;
+  int count = 0;
+ 
+  rw_args = (rtems_libio_rw_args_t *) arg;
+ 
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+ 
+#ifdef CONSOLE_FAKE_INPUT
+    count = 0;
+    buffer[ count++ ]  = '\n';
+    buffer[ count ]  = 0;
+#else
+  for (count = 0; count < maximum; count++) {
+    buffer[ count ] = INBYTE( minor );
+    if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
+      buffer[ count++ ]  = '\n';
+      buffer[ count ]  = 0;
+      break;
+    }
+  }
+#endif
+ 
+  rw_args->bytes_moved = count;
+  return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
+}
+ 
+/*
+ *  console_write
+ *
+ *  This routine is the console device driver write entry point.
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ *
+ *  NOTE:  Write bytes to the serial port. Stdout and stderr are the same.
+ */
+ 
+rtems_device_driver console_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  int count;
+  int maximum;
+  rtems_libio_rw_args_t *rw_args;
+  char *buffer;
+ 
+  rw_args = (rtems_libio_rw_args_t *) arg;
+ 
+  buffer = rw_args->buffer;
+  maximum = rw_args->count;
+ 
+  for (count = 0; count < maximum; count++) {
+    OUTBYTE( minor, buffer[ count ] );
+    if ( buffer[ count ] == '\n') {
+      OUTBYTE( minor, '\r');
+    }
+  }
+ 
+  rw_args->bytes_moved = maximum;
+  return RTEMS_SUCCESSFUL;
+}
+ 
+/*
+ *  console_control
+ *
+ *  This routine is the console device driver control entry point.
+ *
+ *  Input parameters:
+ *    major - console device major number
+ *    minor - console device minor number
+ *    arg   - pointer to optional device driver arguments
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:
+ *    rtems_device_driver status code
+ */
+ 
+rtems_device_driver console_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void                    * arg
+)
+{
+  return RTEMS_SUCCESSFUL;
+}
+
diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
new file mode 100644
index 0000000000..8c6f1ce29b
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
@@ -0,0 +1,181 @@
+/*  bsp.h
+ *
+ *  This include file contains all SPARC simulator definitions.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#ifndef __SIS_h
+#define __SIS_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems.h>
+#include <clockdrv.h>
+#include <console.h>
+#include <iosupp.h>
+#include <erc32.h>
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       3   /* 3 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ *
+ *  NOTE: Since the interrupt code for the SPARC supports both synchronous
+ *        and asynchronous trap handlers, support for testing with both
+ *        is included.
+ */
+
+#define SIS_USE_SYNCHRONOUS_TRAP  0
+
+/*
+ *  The synchronous trap is an arbitrarily chosen software trap.
+ */
+
+#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
+
+#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+  set_vector( (handler), TEST_VECTOR, 1 );
+
+#define Cause_tm27_intr() \
+  asm volatile( "ta 0x10; nop " );
+
+#define Clear_tm27_intr()  
+
+#define Lower_tm27_intr() 
+
+/*
+ *  The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
+ */
+
+#else   /* use a regular asynchronous trap */
+
+#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
+#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
+ 
+#define MUST_WAIT_FOR_INTERRUPT 1
+ 
+#define Install_tm27_vector( handler ) \
+  set_vector( (handler), TEST_VECTOR, 1 );
+ 
+#define Cause_tm27_intr() \
+  do { \
+    ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE ); \
+    nop(); \
+    nop(); \
+    nop(); \
+  } while (0)
+ 
+#define Clear_tm27_intr() \
+  ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
+ 
+#define Lower_tm27_intr()
+
+#endif
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+extern void Clock_delay(rtems_unsigned32 microseconds);
+
+#define delay( microseconds ) Clock_delay(microseconds)
+
+/* Constants */
+
+/*
+ *  Information placed in the linkcmds file.
+ */
+
+extern int   RAM_START;
+extern int   RAM_END;
+extern int   RAM_SIZE;
+ 
+extern int   PROM_START;
+extern int   PROM_END;
+extern int   PROM_SIZE;
+
+extern int   CLOCK_SPEED;
+ 
+extern int   end;        /* last address in the program */
+
+/*
+ *  Device Driver Table Entries
+ */
+ 
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+ 
+/*
+ * How many libio files we want
+ */
+ 
+#define BSP_LIBIO_MAX_FDS       20
+ 
+ 
+/* miscellaneous stuff assumed to exist */
+
+void bsp_cleanup( void );
+
+void bsp_start( void );
+
+rtems_isr_entry set_vector(                     /* returns old vector */
+    rtems_isr_entry     handler,                /* isr routine        */
+    rtems_vector_number vector,                 /* vector number      */
+    int                 type                    /* RTEMS or RAW intr  */
+);
+
+void DEBUG_puts( char *string );
+
+void BSP_fatal_return( void );
+
+void bsp_spurious_initialize( void );
+
+extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
+
+extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
+
+extern rtems_unsigned32          bsp_isr_level;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/sparc/erc32/include/coverhd.h b/c/src/lib/libbsp/sparc/erc32/include/coverhd.h
new file mode 100644
index 0000000000..6a266786cd
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/include/coverhd.h
@@ -0,0 +1,111 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C for this target.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  $Id$
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      0
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        0
+#define CALLING_OVERHEAD_TASK_CREATE               0
+#define CALLING_OVERHEAD_TASK_IDENT                0
+#define CALLING_OVERHEAD_TASK_START                0
+#define CALLING_OVERHEAD_TASK_RESTART              0
+#define CALLING_OVERHEAD_TASK_DELETE               0
+#define CALLING_OVERHEAD_TASK_SUSPEND              0
+#define CALLING_OVERHEAD_TASK_RESUME               0
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         0
+#define CALLING_OVERHEAD_TASK_MODE                 0
+#define CALLING_OVERHEAD_TASK_GET_NOTE             0
+#define CALLING_OVERHEAD_TASK_SET_NOTE             0
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            0
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           0
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           0
+#define CALLING_OVERHEAD_CLOCK_GET                 0
+#define CALLING_OVERHEAD_CLOCK_SET                 0
+#define CALLING_OVERHEAD_CLOCK_TICK                0
+
+#define CALLING_OVERHEAD_TIMER_CREATE              0
+#define CALLING_OVERHEAD_TIMER_IDENT               0
+#define CALLING_OVERHEAD_TIMER_DELETE              0
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          0
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           0
+#define CALLING_OVERHEAD_TIMER_RESET               0
+#define CALLING_OVERHEAD_TIMER_CANCEL              0
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          0
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           0
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          0
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          0
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       0
+
+#define CALLING_OVERHEAD_EVENT_SEND                0
+#define CALLING_OVERHEAD_EVENT_RECEIVE             0
+#define CALLING_OVERHEAD_SIGNAL_CATCH              0
+#define CALLING_OVERHEAD_SIGNAL_SEND               0
+#define CALLING_OVERHEAD_PARTITION_CREATE          0
+#define CALLING_OVERHEAD_PARTITION_IDENT           0
+#define CALLING_OVERHEAD_PARTITION_DELETE          0
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      0
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   0
+#define CALLING_OVERHEAD_REGION_CREATE             0
+#define CALLING_OVERHEAD_REGION_IDENT              0
+#define CALLING_OVERHEAD_REGION_DELETE             0
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        0
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     0
+#define CALLING_OVERHEAD_PORT_CREATE               0
+#define CALLING_OVERHEAD_PORT_IDENT                0
+#define CALLING_OVERHEAD_PORT_DELETE               0
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             0
+#define CALLING_OVERHEAD_IO_OPEN                   0
+#define CALLING_OVERHEAD_IO_CLOSE                  0
+#define CALLING_OVERHEAD_IO_READ                   0
+#define CALLING_OVERHEAD_IO_WRITE                  0
+#define CALLING_OVERHEAD_IO_CONTROL                0
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     0
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */