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authorPavel Pisa <ppisa@pikron.com>2016-05-19 10:21:01 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2016-10-02 10:40:33 +0200
commitbe5cf032c5962bb4bc6915b536d2fca668983d34 (patch)
treeef3d455522382d7365511b21506ecbd814993540 /c/src
parentscore: Fix C/C++ compatibility issue (diff)
downloadrtems-be5cf032c5962bb4bc6915b536d2fca668983d34.tar.bz2
bsps/arm: CP15 support for flush prefetch buffer and table base control.
Updates #2782 Updates #2783
Diffstat (limited to 'c/src')
-rw-r--r--c/src/lib/libcpu/arm/shared/include/arm-cp15.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
index 76b05822cd..4c1966d7ff 100644
--- a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
+++ b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
@@ -358,6 +358,37 @@ arm_cp15_set_translation_table_base(uint32_t *base)
);
}
+/* Translation Table Base Control Register - DDI0301H arm1176jzfs TRM 3.2.15 */
+ARM_CP15_TEXT_SECTION static inline uint32_t
+*arm_cp15_get_translation_table_base_control_register(void)
+{
+ ARM_SWITCH_REGISTERS;
+ uint32_t ttb_cr;
+
+ __asm__ volatile (
+ ARM_SWITCH_TO_ARM
+ "mrc p15, 0, %[ttb_cr], c2, c0, 2\n"
+ ARM_SWITCH_BACK
+ : [ttb_cr] "=&r" (ttb_cr) ARM_SWITCH_ADDITIONAL_OUTPUT
+ );
+
+ return ttb_cr;
+}
+
+ARM_CP15_TEXT_SECTION static inline void
+arm_cp15_set_translation_table_base_control_register(uint32_t ttb_cr)
+{
+ ARM_SWITCH_REGISTERS;
+
+ __asm__ volatile (
+ ARM_SWITCH_TO_ARM
+ "mcr p15, 0, %[ttb_cr], c2, c0, 2\n"
+ ARM_SWITCH_BACK
+ : ARM_SWITCH_OUTPUT
+ : [ttb_cr] "r" (ttb_cr)
+ );
+}
+
ARM_CP15_TEXT_SECTION static inline uint32_t
arm_cp15_get_domain_access_control(void)
{
@@ -858,6 +889,23 @@ arm_cp15_branch_predictor_invalidate_all(void)
);
}
+/* Flush Prefetch Buffer - DDI0301H arm1176jzfs TRM 3.2.22 */
+ARM_CP15_TEXT_SECTION static inline void
+arm_cp15_flush_prefetch_buffer(void)
+{
+ ARM_SWITCH_REGISTERS;
+ uint32_t sbz = 0;
+
+ __asm__ volatile (
+ ARM_SWITCH_TO_ARM
+ "mcr p15, 0, %[sbz], c7, c5, 4\n"
+ ARM_SWITCH_BACK
+ : ARM_SWITCH_OUTPUT
+ : [sbz] "r" (sbz)
+ : "memory"
+ );
+}
+
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_instruction_cache_invalidate(void)
{