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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1995-05-11 17:39:37 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1995-05-11 17:39:37 +0000 |
commit | ac7d5ef06a6d6e8d84abbd1f0b82162725f98326 (patch) | |
tree | 9304cf759a73f2a1c6fd3191948f00e870af3787 /c/src/tests/sptests/sp08/sp08.scn | |
download | rtems-ac7d5ef06a6d6e8d84abbd1f0b82162725f98326.tar.bz2 |
Initial revision
Diffstat (limited to 'c/src/tests/sptests/sp08/sp08.scn')
-rw-r--r-- | c/src/tests/sptests/sp08/sp08.scn | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/c/src/tests/sptests/sp08/sp08.scn b/c/src/tests/sptests/sp08/sp08.scn new file mode 100644 index 0000000000..d85ccc384f --- /dev/null +++ b/c/src/tests/sptests/sp08/sp08.scn @@ -0,0 +1,22 @@ +*** TEST 8 *** +TA1 - rtems_task_mode - RTEMS_ASR - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_NO_ASR - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_NO_ASR - previous mode: 00000400 +TA1 - rtems_task_mode - RTEMS_ASR - previous mode: 00000400 +TA1 - rtems_task_mode - RTEMS_NO_TIMESLICE - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_TIMESLICE - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_TIMESLICE - previous mode: 00000200 +TA1 - rtems_task_mode - RTEMS_NO_TIMESLICE - previous mode: 00000200 +TA1 - rtems_task_mode - RTEMS_PREEMPT - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_NO_PREEMPT - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_NO_PREEMPT - previous mode: 00000100 +TA1 - rtems_task_mode - RTEMS_PREEMPT - previous mode: 00000100 +TA1 - rtems_task_mode - RTEMS_INTERRUPT_LEVEL( 3 ) - previous mode: 00000000 +TA1 - rtems_task_mode - RTEMS_INTERRUPT_LEVEL( 5 ) - previous mode: 00000003 +TA1 - rtems_task_mode - set all modes - previous mode: 00000005 +TA1 - rtems_task_mode - set all modes - previous mode: 00000703 +TA1 - rtems_task_mode - clear all modes - previous mode: 00000703 +TA1 - rtems_task_mode - get current mode - previous mode: 00000000 +*** END OF TEST 8 *** + +NOTE: The interrupt level lines will be different on CPUs with few levels. |