libchip: Avoid <bsp/utility.h>

2 files changed, 612 insertions, 578 deletions

diff --git a/c/src/libchip/network/dwmac-desc.h b/c/src/libchip/network/dwmac-desc.h
index bc5b54abbe..622e9b9a43 100644
--- a/c/src/libchip/network/dwmac-desc.h
+++ b/c/src/libchip/network/dwmac-desc.h
@@ -1,198 +1,215 @@
 #ifndef DWMAC_DESC_RX_REGS_H
 #define DWMAC_DESC_RX_REGS_H
 
-#include <bsp/utility.h>
+#include <stdint.h>
+
+#define DWMAC_DESC_BIT32(bit) \
+  ((uint32_t) (((uint32_t) 1) << (bit)))
+
+#define DWMAC_DESC_MSK32(first_bit, last_bit) \
+  ((uint32_t) ((DWMAC_DESC_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit)))
+
+#define DWMAC_DESC_FLD32(val, first_bit, last_bit) \
+  ((uint32_t) \
+    ((((uint32_t) (val)) << (first_bit)) & DWMAC_DESC_MSK32(first_bit, last_bit)))
+
+#define DWMAC_DESC_FLD32GET(reg, first_bit, last_bit) \
+  ((uint32_t) (((reg) & DWMAC_DESC_MSK32(first_bit, last_bit)) >> (first_bit)))
+
+#define DWMAC_DESC_FLD32SET(reg, val, first_bit, last_bit) \
+  ((uint32_t) (((reg) & ~DWMAC_DESC_MSK32(first_bit, last_bit)) \
+    | DWMAC_DESC_FLD32(val, first_bit, last_bit)))
 
 typedef struct {
 	uint32_t des0;
-#define DWMAC_DESC_RX_DES0_OWN_BIT BSP_BIT32(31)
-#define DWMAC_DESC_RX_DES0_DEST_ADDR_FILTER_FAIL BSP_BIT32(30)
-#define DWMAC_DESC_RX_DES0_FRAME_LENGTH(val) BSP_FLD32(val, 16, 29)
-#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_GET(reg) BSP_FLD32GET(reg, 16, 29)
-#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 29)
-#define DWMAC_DESC_RX_DES0_ERROR_SUMMARY BSP_BIT32(15)
-#define DWMAC_DESC_RX_DES0_DESCRIPTOR_ERROR BSP_BIT32(14)
-#define DWMAC_DESC_RX_DES0_SRC_ADDR_FILTER_FAIL BSP_BIT32(13)
-#define DWMAC_DESC_RX_DES0_LENGTH_ERROR BSP_BIT32(12)
-#define DWMAC_DESC_RX_DES0_OVERFLOW_ERROR BSP_BIT32(11)
-#define DWMAC_DESC_RX_DES0_VLAN_TAG BSP_BIT32(10)
-#define DWMAC_DESC_RX_DES0_FIRST_DESCRIPTOR BSP_BIT32(9)
-#define DWMAC_DESC_RX_DES0_LAST_DESCRIPTOR BSP_BIT32(8)
-#define DWMAC_DESC_RX_DES0_CHECKSUM_ERROR BSP_BIT32(7)
-#define DWMAC_DESC_RX_DES0_LATE_COLLISION BSP_BIT32(6)
-#define DWMAC_DESC_RX_DES0_FRAME_TYPE BSP_BIT32(5)
-#define DWMAC_DESC_RX_DES0_RECEIVE_WATCHDOG_TIMEOUT BSP_BIT32(4)
-#define DWMAC_DESC_RX_DES0_RECEIVE_ERROR BSP_BIT32(3)
-#define DWMAC_DESC_RX_DES0_DRIBBLE_BIT_ERROR BSP_BIT32(2)
-#define DWMAC_DESC_RX_DES0_CRC_ERROR BSP_BIT32(1)
-#define DWMAC_DESC_RX_DES0_RX_MAC_ADDR_OR_PAYLOAD_CHECKSUM_ERROR BSP_BIT32(0)
+#define DWMAC_DESC_RX_DES0_OWN_BIT DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_RX_DES0_DEST_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(30)
+#define DWMAC_DESC_RX_DES0_FRAME_LENGTH(val) DWMAC_DESC_FLD32(val, 16, 29)
+#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 29)
+#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 29)
+#define DWMAC_DESC_RX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15)
+#define DWMAC_DESC_RX_DES0_DESCRIPTOR_ERROR DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_RX_DES0_SRC_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(13)
+#define DWMAC_DESC_RX_DES0_LENGTH_ERROR DWMAC_DESC_BIT32(12)
+#define DWMAC_DESC_RX_DES0_OVERFLOW_ERROR DWMAC_DESC_BIT32(11)
+#define DWMAC_DESC_RX_DES0_VLAN_TAG DWMAC_DESC_BIT32(10)
+#define DWMAC_DESC_RX_DES0_FIRST_DESCRIPTOR DWMAC_DESC_BIT32(9)
+#define DWMAC_DESC_RX_DES0_LAST_DESCRIPTOR DWMAC_DESC_BIT32(8)
+#define DWMAC_DESC_RX_DES0_CHECKSUM_ERROR DWMAC_DESC_BIT32(7)
+#define DWMAC_DESC_RX_DES0_LATE_COLLISION DWMAC_DESC_BIT32(6)
+#define DWMAC_DESC_RX_DES0_FRAME_TYPE DWMAC_DESC_BIT32(5)
+#define DWMAC_DESC_RX_DES0_RECEIVE_WATCHDOG_TIMEOUT DWMAC_DESC_BIT32(4)
+#define DWMAC_DESC_RX_DES0_RECEIVE_ERROR DWMAC_DESC_BIT32(3)
+#define DWMAC_DESC_RX_DES0_DRIBBLE_BIT_ERROR DWMAC_DESC_BIT32(2)
+#define DWMAC_DESC_RX_DES0_CRC_ERROR DWMAC_DESC_BIT32(1)
+#define DWMAC_DESC_RX_DES0_RX_MAC_ADDR_OR_PAYLOAD_CHECKSUM_ERROR DWMAC_DESC_BIT32(0)
 	uint32_t des1;
-#define DWMAC_DESC_RX_DES1_DISABLE_IRQ_ON_COMPLETION BSP_BIT32(31)
-#define DWMAC_DESC_RX_DES1_RECEIVE_END_OF_RING BSP_BIT32(25)
-#define DWMAC_DESC_RX_DES1_SECOND_ADDR_CHAINED BSP_BIT32(24)
-#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE(val) BSP_FLD32(val, 11, 21)
-#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 11, 21)
-#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 11, 21)
-#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 10)
-#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 10)
-#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
+#define DWMAC_DESC_RX_DES1_DISABLE_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_RX_DES1_RECEIVE_END_OF_RING DWMAC_DESC_BIT32(25)
+#define DWMAC_DESC_RX_DES1_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(24)
+#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 11, 21)
+#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 11, 21)
+#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 11, 21)
+#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 10)
+#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 10)
+#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 10)
 	uint32_t des2;
-#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
-#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des3;
-#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
-#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_rx;
 
 typedef struct {
 	uint32_t des0;
-#define DWMAC_DESC_TX_DES0_OWN_BIT BSP_BIT32(31)
-#define DWMAC_DESC_TX_DES0_TX_TIMESTAMP_STATUS BSP_BIT32(17)
-#define DWMAC_DESC_TX_DES0_IP_HEADER_ERROR BSP_BIT32(16)
-#define DWMAC_DESC_TX_DES0_ERROR_SUMMARY BSP_BIT32(15)
-#define DWMAC_DESC_TX_DES0_JABBER_TIMEOUT BSP_BIT32(14)
-#define DWMAC_DESC_TX_DES0_FRAME_FLUSHED BSP_BIT32(13)
-#define DWMAC_DESC_TX_DES0_PAYLOAD_CHECKSUM_ERROR BSP_BIT32(12)
-#define DWMAC_DESC_TX_DES0_LOSS_OF_CARRIER BSP_BIT32(11)
-#define DWMAC_DESC_TX_DES0_NO_CARRIER BSP_BIT32(10)
-#define DWMAC_DESC_TX_DES0_EXCESSIVE_COLLISION BSP_BIT32(8)
-#define DWMAC_DESC_TX_DES0_VLAN_FRAME BSP_BIT32(7)
-#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT(val) BSP_FLD32(val, 3, 6)
-#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 3, 6)
-#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6)
-#define DWMAC_DESC_TX_DES0_EXCESSIVE_DEFERAL BSP_BIT32(2)
-#define DWMAC_DESC_TX_DES0_UNDERFLOW_ERROR BSP_BIT32(1)
-#define DWMAC_DESC_TX_DES0_DEFERED_BIT BSP_BIT32(0)
+#define DWMAC_DESC_TX_DES0_OWN_BIT DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_TX_DES0_TX_TIMESTAMP_STATUS DWMAC_DESC_BIT32(17)
+#define DWMAC_DESC_TX_DES0_IP_HEADER_ERROR DWMAC_DESC_BIT32(16)
+#define DWMAC_DESC_TX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15)
+#define DWMAC_DESC_TX_DES0_JABBER_TIMEOUT DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_TX_DES0_FRAME_FLUSHED DWMAC_DESC_BIT32(13)
+#define DWMAC_DESC_TX_DES0_PAYLOAD_CHECKSUM_ERROR DWMAC_DESC_BIT32(12)
+#define DWMAC_DESC_TX_DES0_LOSS_OF_CARRIER DWMAC_DESC_BIT32(11)
+#define DWMAC_DESC_TX_DES0_NO_CARRIER DWMAC_DESC_BIT32(10)
+#define DWMAC_DESC_TX_DES0_EXCESSIVE_COLLISION DWMAC_DESC_BIT32(8)
+#define DWMAC_DESC_TX_DES0_VLAN_FRAME DWMAC_DESC_BIT32(7)
+#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT(val) DWMAC_DESC_FLD32(val, 3, 6)
+#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_GET(reg) DWMAC_DESC_FLD32GET(reg, 3, 6)
+#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 3, 6)
+#define DWMAC_DESC_TX_DES0_EXCESSIVE_DEFERAL DWMAC_DESC_BIT32(2)
+#define DWMAC_DESC_TX_DES0_UNDERFLOW_ERROR DWMAC_DESC_BIT32(1)
+#define DWMAC_DESC_TX_DES0_DEFERED_BIT DWMAC_DESC_BIT32(0)
 	uint32_t des1;
-#define DWMAC_DESC_TX_DES1_IRQ_ON_COMPLETION BSP_BIT32(31)
-#define DWMAC_DESC_TX_DES1_LAST_SEGMENT BSP_BIT32(30)
-#define DWMAC_DESC_TX_DES1_FIRST_SEGMENT BSP_BIT32(29)
-#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL(val) BSP_FLD32(val, 27, 28)
-#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_GET(reg) BSP_FLD32GET(reg, 27, 28)
-#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_SET(reg, val) BSP_FLD32SET(reg, val, 27, 28)
-#define DWMAC_DESC_TX_DES1_DISABLE_CRC BSP_BIT32(26)
-#define DWMAC_DESC_TX_DES1_TRANSMIT_END_OF_RING BSP_BIT32(25)
-#define DWMAC_DESC_TX_DES1_SECOND_ADDRESS_CHAINED BSP_BIT32(24)
-#define DWMAC_DESC_TX_DES1_DISABLE_PADDING BSP_BIT32(23)
-#define DWMAC_DESC_TX_DES1_TRANSMIT_TIMESTAMP_ENABLE BSP_BIT32(22)
-#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE(val) BSP_FLD32(val, 11, 21)
-#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 11, 21)
-#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 11, 21)
-#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 10)
-#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 10)
-#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
+#define DWMAC_DESC_TX_DES1_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_TX_DES1_LAST_SEGMENT DWMAC_DESC_BIT32(30)
+#define DWMAC_DESC_TX_DES1_FIRST_SEGMENT DWMAC_DESC_BIT32(29)
+#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL(val) DWMAC_DESC_FLD32(val, 27, 28)
+#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_GET(reg) DWMAC_DESC_FLD32GET(reg, 27, 28)
+#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 27, 28)
+#define DWMAC_DESC_TX_DES1_DISABLE_CRC DWMAC_DESC_BIT32(26)
+#define DWMAC_DESC_TX_DES1_TRANSMIT_END_OF_RING DWMAC_DESC_BIT32(25)
+#define DWMAC_DESC_TX_DES1_SECOND_ADDRESS_CHAINED DWMAC_DESC_BIT32(24)
+#define DWMAC_DESC_TX_DES1_DISABLE_PADDING DWMAC_DESC_BIT32(23)
+#define DWMAC_DESC_TX_DES1_TRANSMIT_TIMESTAMP_ENABLE DWMAC_DESC_BIT32(22)
+#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 11, 21)
+#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 11, 21)
+#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 11, 21)
+#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 10)
+#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 10)
+#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 10)
 	uint32_t des2;
-#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
-#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des3;
-#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
-#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_tx;
 
 typedef struct {
 	uint32_t des0;
-#define DWMAC_DESC_ERX_DES0_OWN_BIT BSP_BIT32(31)
-#define DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL BSP_BIT32(30)
-#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH(val) BSP_FLD32(val, 16, 29)
-#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET(reg) BSP_FLD32GET(reg, 16, 29)
-#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 29)
-#define DWMAC_DESC_ERX_DES0_ERROR_SUMMARY BSP_BIT32(15)
-#define DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR BSP_BIT32(14)
-#define DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL BSP_BIT32(13)
-#define DWMAC_DESC_ERX_DES0_LENGTH_ERROR BSP_BIT32(12)
-#define DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR BSP_BIT32(11)
-#define DWMAC_DESC_ERX_DES0_VLAN_TAG BSP_BIT32(10)
-#define DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR BSP_BIT32(9)
-#define DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR BSP_BIT32(8)
-#define DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME BSP_BIT32(7)
-#define DWMAC_DESC_ERX_DES0_LATE_COLLISION BSP_BIT32(6)
-#define DWMAC_DESC_ERX_DES0_FREAME_TYPE BSP_BIT32(5)
-#define DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT BSP_BIT32(4)
-#define DWMAC_DESC_ERX_DES0_RECEIVE_ERROR BSP_BIT32(3)
-#define DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR BSP_BIT32(2)
-#define DWMAC_DESC_ERX_DES0_CRC_ERROR BSP_BIT32(1)
-#define DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS BSP_BIT32(0)
+#define DWMAC_DESC_ERX_DES0_OWN_BIT DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(30)
+#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH(val) DWMAC_DESC_FLD32(val, 16, 29)
+#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 29)
+#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 29)
+#define DWMAC_DESC_ERX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15)
+#define DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(13)
+#define DWMAC_DESC_ERX_DES0_LENGTH_ERROR DWMAC_DESC_BIT32(12)
+#define DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR DWMAC_DESC_BIT32(11)
+#define DWMAC_DESC_ERX_DES0_VLAN_TAG DWMAC_DESC_BIT32(10)
+#define DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR DWMAC_DESC_BIT32(9)
+#define DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR DWMAC_DESC_BIT32(8)
+#define DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME DWMAC_DESC_BIT32(7)
+#define DWMAC_DESC_ERX_DES0_LATE_COLLISION DWMAC_DESC_BIT32(6)
+#define DWMAC_DESC_ERX_DES0_FREAME_TYPE DWMAC_DESC_BIT32(5)
+#define DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT DWMAC_DESC_BIT32(4)
+#define DWMAC_DESC_ERX_DES0_RECEIVE_ERROR DWMAC_DESC_BIT32(3)
+#define DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR DWMAC_DESC_BIT32(2)
+#define DWMAC_DESC_ERX_DES0_CRC_ERROR DWMAC_DESC_BIT32(1)
+#define DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS DWMAC_DESC_BIT32(0)
 	uint32_t des1;
-#define DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION BSP_BIT32(31)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE(val) BSP_FLD32(val, 16, 28)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET(reg) BSP_FLD32GET(reg, 16, 28)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 28)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING BSP_BIT32(15)
-#define DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED BSP_BIT32(14)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE(val) BSP_FLD32(val, 0, 12)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 12)
-#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 12)
+#define DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE(val) DWMAC_DESC_FLD32(val, 16, 28)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 28)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 28)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING DWMAC_DESC_BIT32(15)
+#define DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 12)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 12)
+#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 12)
 	uint32_t des2;
-#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des3;
-#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_erx;
 
 typedef struct {
 	uint32_t des0;
-#define DWMAC_DESC_ETX_DES0_OWN_BIT BSP_BIT32(31)
-#define DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION BSP_BIT32(30)
-#define DWMAC_DESC_ETX_DES0_LAST_SEGMENT BSP_BIT32(29)
-#define DWMAC_DESC_ETX_DES0_FIRST_SEGMENT BSP_BIT32(28)
-#define DWMAC_DESC_ETX_DES0_DISABLE_CRC BSP_BIT32(27)
-#define DWMAC_DESC_ETX_DES0_DISABLE_PAD BSP_BIT32(26)
-#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_ENABLE BSP_BIT32(25)
-#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL(val) BSP_FLD32(val, 22, 23)
-#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_GET(reg) BSP_FLD32GET(reg, 22, 23)
-#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_SET(reg, val) BSP_FLD32SET(reg, val, 22, 23)
-#define DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING BSP_BIT32(21)
-#define DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED BSP_BIT32(20)
-#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_STATUS BSP_BIT32(17)
-#define DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR BSP_BIT32(16)
-#define DWMAC_DESC_ETX_DES0_ERROR_SUMMARY BSP_BIT32(15)
-#define DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT BSP_BIT32(14)
-#define DWMAC_DESC_ETX_DES0_FRAME_FLUSHED BSP_BIT32(13)
-#define DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR BSP_BIT32(12)
-#define DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER BSP_BIT32(11)
-#define DWMAC_DESC_ETX_DES0_NO_CARRIER BSP_BIT32(10)
-#define DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION BSP_BIT32(8)
-#define DWMAC_DESC_ETX_DES0_VLAN_FRAME BSP_BIT32(7)
-#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT(val) BSP_FLD32(val, 3, 6)
-#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_GET(reg) BSP_FLD32GET(reg, 3, 6)
-#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6)
-#define DWMAC_DESC_ETX_DES0_EXCESSIVE_DEFERAL BSP_BIT32(2)
-#define DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR BSP_BIT32(1)
-#define DWMAC_DESC_ETX_DES0_DEFERRED_BIT BSP_BIT32(0)
+#define DWMAC_DESC_ETX_DES0_OWN_BIT DWMAC_DESC_BIT32(31)
+#define DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(30)
+#define DWMAC_DESC_ETX_DES0_LAST_SEGMENT DWMAC_DESC_BIT32(29)
+#define DWMAC_DESC_ETX_DES0_FIRST_SEGMENT DWMAC_DESC_BIT32(28)
+#define DWMAC_DESC_ETX_DES0_DISABLE_CRC DWMAC_DESC_BIT32(27)
+#define DWMAC_DESC_ETX_DES0_DISABLE_PAD DWMAC_DESC_BIT32(26)
+#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_ENABLE DWMAC_DESC_BIT32(25)
+#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL(val) DWMAC_DESC_FLD32(val, 22, 23)
+#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_GET(reg) DWMAC_DESC_FLD32GET(reg, 22, 23)
+#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 22, 23)
+#define DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING DWMAC_DESC_BIT32(21)
+#define DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(20)
+#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_STATUS DWMAC_DESC_BIT32(17)
+#define DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR DWMAC_DESC_BIT32(16)
+#define DWMAC_DESC_ETX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15)
+#define DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_ETX_DES0_FRAME_FLUSHED DWMAC_DESC_BIT32(13)
+#define DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR DWMAC_DESC_BIT32(12)
+#define DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER DWMAC_DESC_BIT32(11)
+#define DWMAC_DESC_ETX_DES0_NO_CARRIER DWMAC_DESC_BIT32(10)
+#define DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION DWMAC_DESC_BIT32(8)
+#define DWMAC_DESC_ETX_DES0_VLAN_FRAME DWMAC_DESC_BIT32(7)
+#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT(val) DWMAC_DESC_FLD32(val, 3, 6)
+#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_GET(reg) DWMAC_DESC_FLD32GET(reg, 3, 6)
+#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 3, 6)
+#define DWMAC_DESC_ETX_DES0_EXCESSIVE_DEFERAL DWMAC_DESC_BIT32(2)
+#define DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR DWMAC_DESC_BIT32(1)
+#define DWMAC_DESC_ETX_DES0_DEFERRED_BIT DWMAC_DESC_BIT32(0)
 	uint32_t des1;
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE(val) BSP_FLD32(val, 16, 28)
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 16, 28)
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 28)
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 12)
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 12)
-#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 12)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 16, 28)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 28)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 28)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 12)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 12)
+#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 12)
 	uint32_t des2;
-#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des3;
-#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_etx;
 
 typedef union {
@@ -205,34 +222,34 @@ typedef union {
 typedef struct {
 	dwmac_desc_erx des0_3;
 	uint32_t des4;
-#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED(val) BSP_FLD32(val, 26, 27)
-#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_GET(reg) BSP_FLD32GET(reg, 26, 27)
-#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_SET(reg, val) BSP_FLD32SET(reg, val, 26, 27)
-#define DWMAC_DESC_EXT_ERX_DES4_LAYER4_FILTER_MATCH BSP_BIT32(25)
-#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_FILTER_MATCH BSP_BIT32(24)
-#define DWMAC_DESC_EXT_ERX_DES4_TIMESTAMP_DROPPED BSP_BIT32(14)
-#define DWMAC_DESC_EXT_ERX_DES4_PTP_VERSION BSP_BIT32(13)
-#define DWMAC_DESC_EXT_ERX_DES4_PTP_FRAME_TYPE BSP_BIT32(12)
-#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE(val) BSP_FLD32(val, 8, 11)
-#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_GET(reg) BSP_FLD32GET(reg, 8, 11)
-#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
-#define DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED BSP_BIT32(7)
-#define DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED BSP_BIT32(6)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_CHECKSUM_BYPASSED BSP_BIT32(5)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR BSP_BIT32(4)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR BSP_BIT32(3)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE(val) BSP_FLD32(val, 0, 2)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET(reg) BSP_FLD32GET(reg, 0, 2)
-#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED(val) DWMAC_DESC_FLD32(val, 26, 27)
+#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_GET(reg) DWMAC_DESC_FLD32GET(reg, 26, 27)
+#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 26, 27)
+#define DWMAC_DESC_EXT_ERX_DES4_LAYER4_FILTER_MATCH DWMAC_DESC_BIT32(25)
+#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_FILTER_MATCH DWMAC_DESC_BIT32(24)
+#define DWMAC_DESC_EXT_ERX_DES4_TIMESTAMP_DROPPED DWMAC_DESC_BIT32(14)
+#define DWMAC_DESC_EXT_ERX_DES4_PTP_VERSION DWMAC_DESC_BIT32(13)
+#define DWMAC_DESC_EXT_ERX_DES4_PTP_FRAME_TYPE DWMAC_DESC_BIT32(12)
+#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE(val) DWMAC_DESC_FLD32(val, 8, 11)
+#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_GET(reg) DWMAC_DESC_FLD32GET(reg, 8, 11)
+#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 8, 11)
+#define DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED DWMAC_DESC_BIT32(7)
+#define DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED DWMAC_DESC_BIT32(6)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_CHECKSUM_BYPASSED DWMAC_DESC_BIT32(5)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR DWMAC_DESC_BIT32(4)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR DWMAC_DESC_BIT32(3)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE(val) DWMAC_DESC_FLD32(val, 0, 2)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 2)
+#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 2)
 	uint32_t des5;
 	uint32_t des6;
-#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des7;
-#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_ext_erx;
 
 typedef struct {
@@ -240,13 +257,13 @@ typedef struct {
 	uint32_t des4;
 	uint32_t des5;
 	uint32_t des6;
-#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 	uint32_t des7;
-#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH(val) BSP_FLD32(val, 0, 31)
-#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH(val) DWMAC_DESC_FLD32(val, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31)
+#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31)
 } dwmac_desc_ext_etx;
 
 typedef union {
diff --git a/c/src/libchip/network/dwmac-regs.h b/c/src/libchip/network/dwmac-regs.h
index 53d7486750..03139bd2c6 100644
--- a/c/src/libchip/network/dwmac-regs.h
+++ b/c/src/libchip/network/dwmac-regs.h
@@ -1,217 +1,234 @@
 #ifndef MAC_REGS_H
 #define MAC_REGS_H
 
-#include <bsp/utility.h>
+#include <stdint.h>
+
+#define DWMAC_REGS_BIT32(bit) \
+  ((uint32_t) (((uint32_t) 1) << (bit)))
+
+#define DWMAC_REGS_MSK32(first_bit, last_bit) \
+  ((uint32_t) ((DWMAC_REGS_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit)))
+
+#define DWMAC_REGS_FLD32(val, first_bit, last_bit) \
+  ((uint32_t) \
+    ((((uint32_t) (val)) << (first_bit)) & DWMAC_REGS_MSK32(first_bit, last_bit)))
+
+#define DWMAC_REGS_FLD32GET(reg, first_bit, last_bit) \
+  ((uint32_t) (((reg) & DWMAC_REGS_MSK32(first_bit, last_bit)) >> (first_bit)))
+
+#define DWMAC_REGS_FLD32SET(reg, val, first_bit, last_bit) \
+  ((uint32_t) (((reg) & ~DWMAC_REGS_MSK32(first_bit, last_bit)) \
+    | DWMAC_REGS_FLD32(val, first_bit, last_bit)))
 
 typedef struct {
 	uint32_t high;
-#define MAC_HIGH_ADDRHI(val) BSP_FLD32(val, 0, 15)
-#define MAC_HIGH_ADDRHI_GET(reg) BSP_FLD32GET(reg, 0, 15)
-#define MAC_HIGH_ADDRHI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
-#define MAC_HIGH_MBC0 BSP_BIT32(24)
-#define MAC_HIGH_MBC1 BSP_BIT32(25)
-#define MAC_HIGH_MBC2 BSP_BIT32(26)
-#define MAC_HIGH_MBC3 BSP_BIT32(27)
-#define MAC_HIGH_MBC4 BSP_BIT32(28)
-#define MAC_HIGH_MBC5 BSP_BIT32(29)
-#define MAC_HIGH_SA BSP_BIT32(30)
-#define MAC_HIGH_AE BSP_BIT32(31)
+#define MAC_HIGH_ADDRHI(val) DWMAC_REGS_FLD32(val, 0, 15)
+#define MAC_HIGH_ADDRHI_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15)
+#define MAC_HIGH_ADDRHI_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15)
+#define MAC_HIGH_MBC0 DWMAC_REGS_BIT32(24)
+#define MAC_HIGH_MBC1 DWMAC_REGS_BIT32(25)
+#define MAC_HIGH_MBC2 DWMAC_REGS_BIT32(26)
+#define MAC_HIGH_MBC3 DWMAC_REGS_BIT32(27)
+#define MAC_HIGH_MBC4 DWMAC_REGS_BIT32(28)
+#define MAC_HIGH_MBC5 DWMAC_REGS_BIT32(29)
+#define MAC_HIGH_SA DWMAC_REGS_BIT32(30)
+#define MAC_HIGH_AE DWMAC_REGS_BIT32(31)
 	uint32_t low;
-#define MAC_LOW_ADDRLO(val) BSP_FLD32(val, 0, 32)
-#define MAC_LOW_ADDRLO_GET(reg) BSP_FLD32GET(reg, 0, 32)
-#define MAC_LOW_ADDRLO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 32)
+#define MAC_LOW_ADDRLO(val) DWMAC_REGS_FLD32(val, 0, 32)
+#define MAC_LOW_ADDRLO_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 32)
+#define MAC_LOW_ADDRLO_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 32)
 } mac;
 
 typedef struct {
 	uint32_t mac_configuration;
-#define MACGRP_MAC_CONFIGURATION_PRELEN(val) BSP_FLD32(val, 0, 1)
-#define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) BSP_FLD32GET(reg, 0, 1)
-#define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
-#define MACGRP_MAC_CONFIGURATION_RE BSP_BIT32(2)
-#define MACGRP_MAC_CONFIGURATION_TE BSP_BIT32(3)
-#define MACGRP_MAC_CONFIGURATION_DC BSP_BIT32(4)
-#define MACGRP_MAC_CONFIGURATION_BL(val) BSP_FLD32(val, 5, 6)
-#define MACGRP_MAC_CONFIGURATION_BL_GET(reg) BSP_FLD32GET(reg, 5, 6)
-#define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
-#define MACGRP_MAC_CONFIGURATION_ACS BSP_BIT32(7)
-#define MACGRP_MAC_CONFIGURATION_LUD BSP_BIT32(8)
-#define MACGRP_MAC_CONFIGURATION_DR BSP_BIT32(9)
-#define MACGRP_MAC_CONFIGURATION_IPC BSP_BIT32(10)
-#define MACGRP_MAC_CONFIGURATION_DM BSP_BIT32(11)
-#define MACGRP_MAC_CONFIGURATION_LM BSP_BIT32(12)
-#define MACGRP_MAC_CONFIGURATION_DO BSP_BIT32(13)
-#define MACGRP_MAC_CONFIGURATION_FES BSP_BIT32(14)
-#define MACGRP_MAC_CONFIGURATION_PS BSP_BIT32(15)
-#define MACGRP_MAC_CONFIGURATION_DCRS BSP_BIT32(16)
-#define MACGRP_MAC_CONFIGURATION_IFG(val) BSP_FLD32(val, 17, 19)
-#define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) BSP_FLD32GET(reg, 17, 19)
-#define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19)
-#define MACGRP_MAC_CONFIGURATION_JE BSP_BIT32(20)
-#define MACGRP_MAC_CONFIGURATION_BE BSP_BIT32(21)
-#define MACGRP_MAC_CONFIGURATION_JD BSP_BIT32(22)
-#define MACGRP_MAC_CONFIGURATION_WD BSP_BIT32(23)
-#define MACGRP_MAC_CONFIGURATION_TC BSP_BIT32(24)
-#define MACGRP_MAC_CONFIGURATION_CST BSP_BIT32(25)
-#define MACGRP_MAC_CONFIGURATION_TWOKPE BSP_BIT32(27)
+#define MACGRP_MAC_CONFIGURATION_PRELEN(val) DWMAC_REGS_FLD32(val, 0, 1)
+#define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 1)
+#define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 1)
+#define MACGRP_MAC_CONFIGURATION_RE DWMAC_REGS_BIT32(2)
+#define MACGRP_MAC_CONFIGURATION_TE DWMAC_REGS_BIT32(3)
+#define MACGRP_MAC_CONFIGURATION_DC DWMAC_REGS_BIT32(4)
+#define MACGRP_MAC_CONFIGURATION_BL(val) DWMAC_REGS_FLD32(val, 5, 6)
+#define MACGRP_MAC_CONFIGURATION_BL_GET(reg) DWMAC_REGS_FLD32GET(reg, 5, 6)
+#define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 5, 6)
+#define MACGRP_MAC_CONFIGURATION_ACS DWMAC_REGS_BIT32(7)
+#define MACGRP_MAC_CONFIGURATION_LUD DWMAC_REGS_BIT32(8)
+#define MACGRP_MAC_CONFIGURATION_DR DWMAC_REGS_BIT32(9)
+#define MACGRP_MAC_CONFIGURATION_IPC DWMAC_REGS_BIT32(10)
+#define MACGRP_MAC_CONFIGURATION_DM DWMAC_REGS_BIT32(11)
+#define MACGRP_MAC_CONFIGURATION_LM DWMAC_REGS_BIT32(12)
+#define MACGRP_MAC_CONFIGURATION_DO DWMAC_REGS_BIT32(13)
+#define MACGRP_MAC_CONFIGURATION_FES DWMAC_REGS_BIT32(14)
+#define MACGRP_MAC_CONFIGURATION_PS DWMAC_REGS_BIT32(15)
+#define MACGRP_MAC_CONFIGURATION_DCRS DWMAC_REGS_BIT32(16)
+#define MACGRP_MAC_CONFIGURATION_IFG(val) DWMAC_REGS_FLD32(val, 17, 19)
+#define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19)
+#define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19)
+#define MACGRP_MAC_CONFIGURATION_JE DWMAC_REGS_BIT32(20)
+#define MACGRP_MAC_CONFIGURATION_BE DWMAC_REGS_BIT32(21)
+#define MACGRP_MAC_CONFIGURATION_JD DWMAC_REGS_BIT32(22)
+#define MACGRP_MAC_CONFIGURATION_WD DWMAC_REGS_BIT32(23)
+#define MACGRP_MAC_CONFIGURATION_TC DWMAC_REGS_BIT32(24)
+#define MACGRP_MAC_CONFIGURATION_CST DWMAC_REGS_BIT32(25)
+#define MACGRP_MAC_CONFIGURATION_TWOKPE DWMAC_REGS_BIT32(27)
 	uint32_t mac_frame_filter;
-#define MACGRP_MAC_FRAME_FILTER_PR BSP_BIT32(0)
-#define MACGRP_MAC_FRAME_FILTER_HUC BSP_BIT32(1)
-#define MACGRP_MAC_FRAME_FILTER_HMC BSP_BIT32(2)
-#define MACGRP_MAC_FRAME_FILTER_DAIF BSP_BIT32(3)
-#define MACGRP_MAC_FRAME_FILTER_PM BSP_BIT32(4)
-#define MACGRP_MAC_FRAME_FILTER_DBF BSP_BIT32(5)
-#define MACGRP_MAC_FRAME_FILTER_PCF(val) BSP_FLD32(val, 6, 7)
-#define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) BSP_FLD32GET(reg, 6, 7)
-#define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
-#define MACGRP_MAC_FRAME_FILTER_SAIF BSP_BIT32(8)
-#define MACGRP_MAC_FRAME_FILTER_SAF BSP_BIT32(9)
-#define MACGRP_MAC_FRAME_FILTER_HPF BSP_BIT32(10)
-#define MACGRP_MAC_FRAME_FILTER_VTFE BSP_BIT32(16)
-#define MACGRP_MAC_FRAME_FILTER_IPFE BSP_BIT32(20)
-#define MACGRP_MAC_FRAME_FILTER_DNTU BSP_BIT32(21)
-#define MACGRP_MAC_FRAME_FILTER_RA BSP_BIT32(31)
+#define MACGRP_MAC_FRAME_FILTER_PR DWMAC_REGS_BIT32(0)
+#define MACGRP_MAC_FRAME_FILTER_HUC DWMAC_REGS_BIT32(1)
+#define MACGRP_MAC_FRAME_FILTER_HMC DWMAC_REGS_BIT32(2)
+#define MACGRP_MAC_FRAME_FILTER_DAIF DWMAC_REGS_BIT32(3)
+#define MACGRP_MAC_FRAME_FILTER_PM DWMAC_REGS_BIT32(4)
+#define MACGRP_MAC_FRAME_FILTER_DBF DWMAC_REGS_BIT32(5)
+#define MACGRP_MAC_FRAME_FILTER_PCF(val) DWMAC_REGS_FLD32(val, 6, 7)
+#define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 7)
+#define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 7)
+#define MACGRP_MAC_FRAME_FILTER_SAIF DWMAC_REGS_BIT32(8)
+#define MACGRP_MAC_FRAME_FILTER_SAF DWMAC_REGS_BIT32(9)
+#define MACGRP_MAC_FRAME_FILTER_HPF DWMAC_REGS_BIT32(10)
+#define MACGRP_MAC_FRAME_FILTER_VTFE DWMAC_REGS_BIT32(16)
+#define MACGRP_MAC_FRAME_FILTER_IPFE DWMAC_REGS_BIT32(20)
+#define MACGRP_MAC_FRAME_FILTER_DNTU DWMAC_REGS_BIT32(21)
+#define MACGRP_MAC_FRAME_FILTER_RA DWMAC_REGS_BIT32(31)
 	uint32_t reserved_08[2];
 	uint32_t gmii_address;
-#define MACGRP_GMII_ADDRESS_GMII_BUSY BSP_BIT32(0)
-#define MACGRP_GMII_ADDRESS_GMII_WRITE BSP_BIT32(1)
-#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) BSP_FLD32(val, 2, 5)
-#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) BSP_FLD32GET(reg, 2, 5)
-#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) BSP_FLD32SET(reg, val, 2, 5)
-#define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) BSP_FLD32(val, 6, 10)
-#define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) BSP_FLD32GET(reg, 6, 10)
-#define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
-#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) BSP_FLD32(val, 11, 15)
-#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) BSP_FLD32GET(reg, 11, 15)
-#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
+#define MACGRP_GMII_ADDRESS_GMII_BUSY DWMAC_REGS_BIT32(0)
+#define MACGRP_GMII_ADDRESS_GMII_WRITE DWMAC_REGS_BIT32(1)
+#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) DWMAC_REGS_FLD32(val, 2, 5)
+#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 5)
+#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 5)
+#define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) DWMAC_REGS_FLD32(val, 6, 10)
+#define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 10)
+#define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 10)
+#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) DWMAC_REGS_FLD32(val, 11, 15)
+#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 15)
+#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 15)
 	uint32_t gmii_data;
-#define MACGRP_GMII_DATA_GMII_DATA(val) BSP_FLD32(val, 0, 15)
-#define MACGRP_GMII_DATA_GMII_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
-#define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+#define MACGRP_GMII_DATA_GMII_DATA(val) DWMAC_REGS_FLD32(val, 0, 15)
+#define MACGRP_GMII_DATA_GMII_DATA_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15)
+#define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15)
 	uint32_t reserved_18[9];
 	uint32_t interrupt_mask;
-#define MACGRP_INTERRUPT_MASK_RGSMIIIM BSP_BIT32(0)
-#define MACGRP_INTERRUPT_MASK_PCSLCHGIM BSP_BIT32(1)
-#define MACGRP_INTERRUPT_MASK_PCSANCIM BSP_BIT32(2)
-#define MACGRP_INTERRUPT_MASK_TSIM BSP_BIT32(9)
-#define MACGRP_INTERRUPT_MASK_LPIIM BSP_BIT32(10)
+#define MACGRP_INTERRUPT_MASK_RGSMIIIM DWMAC_REGS_BIT32(0)
+#define MACGRP_INTERRUPT_MASK_PCSLCHGIM DWMAC_REGS_BIT32(1)
+#define MACGRP_INTERRUPT_MASK_PCSANCIM DWMAC_REGS_BIT32(2)
+#define MACGRP_INTERRUPT_MASK_TSIM DWMAC_REGS_BIT32(9)
+#define MACGRP_INTERRUPT_MASK_LPIIM DWMAC_REGS_BIT32(10)
 	mac mac_addr0_15[16];
 	uint32_t reserved_c0[16];
 	uint32_t mmc_control;
-#define MACGRP_MMC_CONTROL_CNTRST BSP_BIT32(0)
-#define MACGRP_MMC_CONTROL_CNTSTOPRO BSP_BIT32(1)
-#define MACGRP_MMC_CONTROL_RSTONRD BSP_BIT32(2)
-#define MACGRP_MMC_CONTROL_CNTFREEZ BSP_BIT32(3)
-#define MACGRP_MMC_CONTROL_CNTPRST BSP_BIT32(4)
-#define MACGRP_MMC_CONTROL_CNTPRSTLVL BSP_BIT32(5)
-#define MACGRP_MMC_CONTROL_UCDBC BSP_BIT32(8)
+#define MACGRP_MMC_CONTROL_CNTRST DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_CONTROL_CNTSTOPRO DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_CONTROL_RSTONRD DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_CONTROL_CNTFREEZ DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_CONTROL_CNTPRST DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_CONTROL_CNTPRSTLVL DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_CONTROL_UCDBC DWMAC_REGS_BIT32(8)
 	uint32_t mmc_receive_interrupt;
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS BSP_BIT32(0)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS BSP_BIT32(1)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS BSP_BIT32(2)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS BSP_BIT32(3)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS BSP_BIT32(4)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS BSP_BIT32(5)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS BSP_BIT32(6)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS BSP_BIT32(7)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS BSP_BIT32(8)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS BSP_BIT32(9)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS BSP_BIT32(10)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS BSP_BIT32(11)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS BSP_BIT32(12)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS BSP_BIT32(13)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS BSP_BIT32(14)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS BSP_BIT32(15)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS BSP_BIT32(16)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS BSP_BIT32(17)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS BSP_BIT32(18)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS BSP_BIT32(19)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS BSP_BIT32(20)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS BSP_BIT32(21)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS BSP_BIT32(22)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS BSP_BIT32(23)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS BSP_BIT32(24)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS BSP_BIT32(25)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS DWMAC_REGS_BIT32(14)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS DWMAC_REGS_BIT32(15)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS DWMAC_REGS_BIT32(25)
 	uint32_t mmc_transmit_interrupt;
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS BSP_BIT32(0)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS BSP_BIT32(1)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS BSP_BIT32(2)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS BSP_BIT32(3)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS BSP_BIT32(4)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS BSP_BIT32(5)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS BSP_BIT32(6)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS BSP_BIT32(7)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS BSP_BIT32(8)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS BSP_BIT32(9)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS BSP_BIT32(10)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS BSP_BIT32(11)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS BSP_BIT32(12)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS BSP_BIT32(13)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS BSP_BIT32(14)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS BSP_BIT32(15)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS BSP_BIT32(16)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS BSP_BIT32(17)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS BSP_BIT32(18)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS BSP_BIT32(19)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS BSP_BIT32(20)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS BSP_BIT32(21)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS BSP_BIT32(22)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS BSP_BIT32(23)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS BSP_BIT32(24)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS BSP_BIT32(25)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS DWMAC_REGS_BIT32(14)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS DWMAC_REGS_BIT32(15)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS DWMAC_REGS_BIT32(25)
 	uint32_t mmc_receive_interrupt_mask;
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM BSP_BIT32(0)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM BSP_BIT32(1)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM BSP_BIT32(2)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM BSP_BIT32(3)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM BSP_BIT32(4)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM BSP_BIT32(5)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM BSP_BIT32(6)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM BSP_BIT32(7)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM BSP_BIT32(8)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM BSP_BIT32(9)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM BSP_BIT32(10)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM BSP_BIT32(11)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM BSP_BIT32(12)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM BSP_BIT32(13)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM BSP_BIT32(14)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM BSP_BIT32(15)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM BSP_BIT32(16)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM BSP_BIT32(17)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM BSP_BIT32(18)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM BSP_BIT32(19)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM BSP_BIT32(20)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM BSP_BIT32(21)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM BSP_BIT32(22)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM BSP_BIT32(23)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM BSP_BIT32(24)
-#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM BSP_BIT32(25)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM DWMAC_REGS_BIT32(14)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM DWMAC_REGS_BIT32(15)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM DWMAC_REGS_BIT32(25)
 	uint32_t mmc_transmit_interrupt_mask;
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM BSP_BIT32(0)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM BSP_BIT32(1)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM BSP_BIT32(2)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM BSP_BIT32(3)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM BSP_BIT32(4)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM BSP_BIT32(5)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM BSP_BIT32(6)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM BSP_BIT32(7)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM BSP_BIT32(8)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM BSP_BIT32(9)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM BSP_BIT32(10)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM BSP_BIT32(11)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM BSP_BIT32(12)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM BSP_BIT32(13)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM BSP_BIT32(14)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM BSP_BIT32(15)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM BSP_BIT32(16)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM BSP_BIT32(17)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM BSP_BIT32(18)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM BSP_BIT32(19)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM BSP_BIT32(20)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM BSP_BIT32(21)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM BSP_BIT32(22)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM BSP_BIT32(23)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM BSP_BIT32(24)
-#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM BSP_BIT32(25)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM DWMAC_REGS_BIT32(14)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM DWMAC_REGS_BIT32(15)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM DWMAC_REGS_BIT32(25)
 	uint32_t txoctetcount_gb;
 	uint32_t txframecount_gb;
 	uint32_t txbroadcastframes_g;
@@ -267,64 +284,64 @@ typedef struct {
 	uint32_t rxctrlframes_g;
 	uint32_t reserved_1e8[6];
 	uint32_t mmc_ipc_receive_interrupt_mask;
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM BSP_BIT32(0)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM BSP_BIT32(1)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM BSP_BIT32(2)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM BSP_BIT32(3)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM BSP_BIT32(4)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM BSP_BIT32(5)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM BSP_BIT32(6)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM BSP_BIT32(7)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM BSP_BIT32(8)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM BSP_BIT32(9)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM BSP_BIT32(10)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM BSP_BIT32(11)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM BSP_BIT32(12)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM BSP_BIT32(13)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM BSP_BIT32(16)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM BSP_BIT32(17)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM BSP_BIT32(18)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM BSP_BIT32(19)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM BSP_BIT32(20)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM BSP_BIT32(21)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM BSP_BIT32(22)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM BSP_BIT32(23)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM BSP_BIT32(24)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM BSP_BIT32(25)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM BSP_BIT32(26)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM BSP_BIT32(27)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM BSP_BIT32(28)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM BSP_BIT32(29)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM DWMAC_REGS_BIT32(25)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM DWMAC_REGS_BIT32(26)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM DWMAC_REGS_BIT32(27)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM DWMAC_REGS_BIT32(28)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM DWMAC_REGS_BIT32(29)
 	uint32_t reserved_204;
 	uint32_t mmc_ipc_receive_interrupt;
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS BSP_BIT32(0)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS BSP_BIT32(1)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS BSP_BIT32(2)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS BSP_BIT32(3)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS BSP_BIT32(4)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS BSP_BIT32(5)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS BSP_BIT32(6)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS BSP_BIT32(7)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS BSP_BIT32(8)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS BSP_BIT32(9)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS BSP_BIT32(10)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS BSP_BIT32(11)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS BSP_BIT32(12)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS BSP_BIT32(13)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS BSP_BIT32(16)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS BSP_BIT32(17)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS BSP_BIT32(18)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS BSP_BIT32(19)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS BSP_BIT32(20)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS BSP_BIT32(21)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS BSP_BIT32(22)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS BSP_BIT32(23)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS BSP_BIT32(24)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS BSP_BIT32(25)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS BSP_BIT32(26)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS BSP_BIT32(27)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS BSP_BIT32(28)
-#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS BSP_BIT32(29)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS DWMAC_REGS_BIT32(0)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS DWMAC_REGS_BIT32(1)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS DWMAC_REGS_BIT32(2)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS DWMAC_REGS_BIT32(3)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS DWMAC_REGS_BIT32(4)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS DWMAC_REGS_BIT32(5)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS DWMAC_REGS_BIT32(6)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS DWMAC_REGS_BIT32(7)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS DWMAC_REGS_BIT32(8)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS DWMAC_REGS_BIT32(9)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS DWMAC_REGS_BIT32(10)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS DWMAC_REGS_BIT32(11)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS DWMAC_REGS_BIT32(12)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS DWMAC_REGS_BIT32(13)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS DWMAC_REGS_BIT32(16)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS DWMAC_REGS_BIT32(17)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS DWMAC_REGS_BIT32(18)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS DWMAC_REGS_BIT32(19)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS DWMAC_REGS_BIT32(20)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS DWMAC_REGS_BIT32(21)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS DWMAC_REGS_BIT32(22)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS DWMAC_REGS_BIT32(23)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS DWMAC_REGS_BIT32(24)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS DWMAC_REGS_BIT32(25)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS DWMAC_REGS_BIT32(26)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS DWMAC_REGS_BIT32(27)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS DWMAC_REGS_BIT32(28)
+#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS DWMAC_REGS_BIT32(29)
 	uint32_t reserved_20c;
 	uint32_t rxipv4_gd_frms;
 	uint32_t rxipv4_hdrerr_frms;
@@ -363,153 +380,153 @@ typedef struct {
 
 typedef struct {
 	uint32_t bus_mode;
-#define DMAGRP_BUS_MODE_SWR BSP_BIT32(0)
-#define DMAGRP_BUS_MODE_DSL(val) BSP_FLD32(val, 2, 6)
-#define DMAGRP_BUS_MODE_DSL_GET(reg) BSP_FLD32GET(reg, 2, 6)
-#define DMAGRP_BUS_MODE_DSL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 6)
-#define DMAGRP_BUS_MODE_ATDS BSP_BIT32(7)
-#define DMAGRP_BUS_MODE_PBL(val) BSP_FLD32(val, 8, 13)
-#define DMAGRP_BUS_MODE_PBL_GET(reg) BSP_FLD32GET(reg, 8, 13)
-#define DMAGRP_BUS_MODE_PBL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
-#define DMAGRP_BUS_MODE_FB BSP_BIT32(16)
-#define DMAGRP_BUS_MODE_RPBL(val) BSP_FLD32(val, 17, 22)
-#define DMAGRP_BUS_MODE_RPBL_GET(reg) BSP_FLD32GET(reg, 17, 22)
-#define DMAGRP_BUS_MODE_RPBL_SET(reg, val) BSP_FLD32SET(reg, val, 17, 22)
-#define DMAGRP_BUS_MODE_USP BSP_BIT32(23)
-#define DMAGRP_BUS_MODE_EIGHTXPBL BSP_BIT32(24)
-#define DMAGRP_BUS_MODE_AAL BSP_BIT32(25)
-#define DMAGRP_BUS_MODE_MB BSP_BIT32(26)
+#define DMAGRP_BUS_MODE_SWR DWMAC_REGS_BIT32(0)
+#define DMAGRP_BUS_MODE_DSL(val) DWMAC_REGS_FLD32(val, 2, 6)
+#define DMAGRP_BUS_MODE_DSL_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 6)
+#define DMAGRP_BUS_MODE_DSL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 6)
+#define DMAGRP_BUS_MODE_ATDS DWMAC_REGS_BIT32(7)
+#define DMAGRP_BUS_MODE_PBL(val) DWMAC_REGS_FLD32(val, 8, 13)
+#define DMAGRP_BUS_MODE_PBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 8, 13)
+#define DMAGRP_BUS_MODE_PBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 8, 13)
+#define DMAGRP_BUS_MODE_FB DWMAC_REGS_BIT32(16)
+#define DMAGRP_BUS_MODE_RPBL(val) DWMAC_REGS_FLD32(val, 17, 22)
+#define DMAGRP_BUS_MODE_RPBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 22)
+#define DMAGRP_BUS_MODE_RPBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 22)
+#define DMAGRP_BUS_MODE_USP DWMAC_REGS_BIT32(23)
+#define DMAGRP_BUS_MODE_EIGHTXPBL DWMAC_REGS_BIT32(24)
+#define DMAGRP_BUS_MODE_AAL DWMAC_REGS_BIT32(25)
+#define DMAGRP_BUS_MODE_MB DWMAC_REGS_BIT32(26)
 	uint32_t transmit_poll_demand;
-#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) BSP_FLD32(val, 0, 31)
-#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) DWMAC_REGS_FLD32(val, 0, 31)
+#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31)
+#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31)
 	uint32_t receive_poll_demand;
-#define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) BSP_FLD32(val, 0, 31)
-#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) BSP_FLD32GET(reg, 0, 31)
-#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+#define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) DWMAC_REGS_FLD32(val, 0, 31)
+#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31)
+#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31)
 	uint32_t receive_descr_list_addr;
-#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) BSP_FLD32(val, 2, 31)
-#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31)
-#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31)
+#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31)
+#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31)
+#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31)
 	uint32_t transmit_descr_list_addr;
-#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) BSP_FLD32(val, 2, 31)
-#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31)
-#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31)
+#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31)
+#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31)
+#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31)
 	uint32_t status;
-#define DMAGRP_STATUS_TI BSP_BIT32(0)
-#define DMAGRP_STATUS_TPS BSP_BIT32(1)
-#define DMAGRP_STATUS_TU BSP_BIT32(2)
-#define DMAGRP_STATUS_TJT BSP_BIT32(3)
-#define DMAGRP_STATUS_OVF BSP_BIT32(4)
-#define DMAGRP_STATUS_UNF BSP_BIT32(5)
-#define DMAGRP_STATUS_RI BSP_BIT32(6)
-#define DMAGRP_STATUS_RU BSP_BIT32(7)
-#define DMAGRP_STATUS_RPS BSP_BIT32(8)
-#define DMAGRP_STATUS_RWT BSP_BIT32(9)
-#define DMAGRP_STATUS_ETI BSP_BIT32(10)
-#define DMAGRP_STATUS_FBI BSP_BIT32(13)
-#define DMAGRP_STATUS_ERI BSP_BIT32(14)
-#define DMAGRP_STATUS_AIS BSP_BIT32(15)
-#define DMAGRP_STATUS_NIS BSP_BIT32(16)
-#define DMAGRP_STATUS_RS(val) BSP_FLD32(val, 17, 19)
-#define DMAGRP_STATUS_RS_GET(reg) BSP_FLD32GET(reg, 17, 19)
-#define DMAGRP_STATUS_RS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19)
-#define DMAGRP_STATUS_TS(val) BSP_FLD32(val, 20, 22)
-#define DMAGRP_STATUS_TS_GET(reg) BSP_FLD32GET(reg, 20, 22)
-#define DMAGRP_STATUS_TS_SET(reg, val) BSP_FLD32SET(reg, val, 20, 22)
-#define DMAGRP_STATUS_EB(val) BSP_FLD32(val, 23, 25)
-#define DMAGRP_STATUS_EB_GET(reg) BSP_FLD32GET(reg, 23, 25)
-#define DMAGRP_STATUS_EB_SET(reg, val) BSP_FLD32SET(reg, val, 23, 25)
-#define DMAGRP_STATUS_GLI BSP_BIT32(26)
-#define DMAGRP_STATUS_GMI BSP_BIT32(27)
-#define DMAGRP_STATUS_TTI BSP_BIT32(29)
-#define DMAGRP_STATUS_GLPII BSP_BIT32(30)
+#define DMAGRP_STATUS_TI DWMAC_REGS_BIT32(0)
+#define DMAGRP_STATUS_TPS DWMAC_REGS_BIT32(1)
+#define DMAGRP_STATUS_TU DWMAC_REGS_BIT32(2)
+#define DMAGRP_STATUS_TJT DWMAC_REGS_BIT32(3)
+#define DMAGRP_STATUS_OVF DWMAC_REGS_BIT32(4)
+#define DMAGRP_STATUS_UNF DWMAC_REGS_BIT32(5)
+#define DMAGRP_STATUS_RI DWMAC_REGS_BIT32(6)
+#define DMAGRP_STATUS_RU DWMAC_REGS_BIT32(7)
+#define DMAGRP_STATUS_RPS DWMAC_REGS_BIT32(8)
+#define DMAGRP_STATUS_RWT DWMAC_REGS_BIT32(9)
+#define DMAGRP_STATUS_ETI DWMAC_REGS_BIT32(10)
+#define DMAGRP_STATUS_FBI DWMAC_REGS_BIT32(13)
+#define DMAGRP_STATUS_ERI DWMAC_REGS_BIT32(14)
+#define DMAGRP_STATUS_AIS DWMAC_REGS_BIT32(15)
+#define DMAGRP_STATUS_NIS DWMAC_REGS_BIT32(16)
+#define DMAGRP_STATUS_RS(val) DWMAC_REGS_FLD32(val, 17, 19)
+#define DMAGRP_STATUS_RS_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19)
+#define DMAGRP_STATUS_RS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19)
+#define DMAGRP_STATUS_TS(val) DWMAC_REGS_FLD32(val, 20, 22)
+#define DMAGRP_STATUS_TS_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 22)
+#define DMAGRP_STATUS_TS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 22)
+#define DMAGRP_STATUS_EB(val) DWMAC_REGS_FLD32(val, 23, 25)
+#define DMAGRP_STATUS_EB_GET(reg) DWMAC_REGS_FLD32GET(reg, 23, 25)
+#define DMAGRP_STATUS_EB_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 23, 25)
+#define DMAGRP_STATUS_GLI DWMAC_REGS_BIT32(26)
+#define DMAGRP_STATUS_GMI DWMAC_REGS_BIT32(27)
+#define DMAGRP_STATUS_TTI DWMAC_REGS_BIT32(29)
+#define DMAGRP_STATUS_GLPII DWMAC_REGS_BIT32(30)
 	uint32_t operation_mode;
-#define DMAGRP_OPERATION_MODE_SR BSP_BIT32(1)
-#define DMAGRP_OPERATION_MODE_OSF BSP_BIT32(2)
-#define DMAGRP_OPERATION_MODE_RTC(val) BSP_FLD32(val, 3, 4)
-#define DMAGRP_OPERATION_MODE_RTC_GET(reg) BSP_FLD32GET(reg, 3, 4)
-#define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
-#define DMAGRP_OPERATION_MODE_FUF BSP_BIT32(6)
-#define DMAGRP_OPERATION_MODE_FEF BSP_BIT32(7)
-#define DMAGRP_OPERATION_MODE_EFC BSP_BIT32(8)
-#define DMAGRP_OPERATION_MODE_RFA(val) BSP_FLD32(val, 9, 10)
-#define DMAGRP_OPERATION_MODE_RFA_GET(reg) BSP_FLD32GET(reg, 9, 10)
-#define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10)
-#define DMAGRP_OPERATION_MODE_RFD(val) BSP_FLD32(val, 11, 12)
-#define DMAGRP_OPERATION_MODE_RFD_GET(reg) BSP_FLD32GET(reg, 11, 12)
-#define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12)
-#define DMAGRP_OPERATION_MODE_ST BSP_BIT32(13)
-#define DMAGRP_OPERATION_MODE_TTC(val) BSP_FLD32(val, 14, 16)
-#define DMAGRP_OPERATION_MODE_TTC_GET(reg) BSP_FLD32GET(reg, 14, 16)
-#define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 16)
-#define DMAGRP_OPERATION_MODE_FTF BSP_BIT32(20)
-#define DMAGRP_OPERATION_MODE_TSF BSP_BIT32(21)
-#define DMAGRP_OPERATION_MODE_DFF BSP_BIT32(24)
-#define DMAGRP_OPERATION_MODE_RSF BSP_BIT32(25)
-#define DMAGRP_OPERATION_MODE_DT BSP_BIT32(26)
+#define DMAGRP_OPERATION_MODE_SR DWMAC_REGS_BIT32(1)
+#define DMAGRP_OPERATION_MODE_OSF DWMAC_REGS_BIT32(2)
+#define DMAGRP_OPERATION_MODE_RTC(val) DWMAC_REGS_FLD32(val, 3, 4)
+#define DMAGRP_OPERATION_MODE_RTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 3, 4)
+#define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 3, 4)
+#define DMAGRP_OPERATION_MODE_FUF DWMAC_REGS_BIT32(6)
+#define DMAGRP_OPERATION_MODE_FEF DWMAC_REGS_BIT32(7)
+#define DMAGRP_OPERATION_MODE_EFC DWMAC_REGS_BIT32(8)
+#define DMAGRP_OPERATION_MODE_RFA(val) DWMAC_REGS_FLD32(val, 9, 10)
+#define DMAGRP_OPERATION_MODE_RFA_GET(reg) DWMAC_REGS_FLD32GET(reg, 9, 10)
+#define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 9, 10)
+#define DMAGRP_OPERATION_MODE_RFD(val) DWMAC_REGS_FLD32(val, 11, 12)
+#define DMAGRP_OPERATION_MODE_RFD_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 12)
+#define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 12)
+#define DMAGRP_OPERATION_MODE_ST DWMAC_REGS_BIT32(13)
+#define DMAGRP_OPERATION_MODE_TTC(val) DWMAC_REGS_FLD32(val, 14, 16)
+#define DMAGRP_OPERATION_MODE_TTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 14, 16)
+#define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 14, 16)
+#define DMAGRP_OPERATION_MODE_FTF DWMAC_REGS_BIT32(20)
+#define DMAGRP_OPERATION_MODE_TSF DWMAC_REGS_BIT32(21)
+#define DMAGRP_OPERATION_MODE_DFF DWMAC_REGS_BIT32(24)
+#define DMAGRP_OPERATION_MODE_RSF DWMAC_REGS_BIT32(25)
+#define DMAGRP_OPERATION_MODE_DT DWMAC_REGS_BIT32(26)
 	uint32_t interrupt_enable;
-#define DMAGRP_INTERRUPT_ENABLE_TIE BSP_BIT32(0)
-#define DMAGRP_INTERRUPT_ENABLE_TSE BSP_BIT32(1)
-#define DMAGRP_INTERRUPT_ENABLE_TUE BSP_BIT32(2)
-#define DMAGRP_INTERRUPT_ENABLE_TJE BSP_BIT32(3)
-#define DMAGRP_INTERRUPT_ENABLE_OVE BSP_BIT32(4)
-#define DMAGRP_INTERRUPT_ENABLE_UNE BSP_BIT32(5)
-#define DMAGRP_INTERRUPT_ENABLE_RIE BSP_BIT32(6)
-#define DMAGRP_INTERRUPT_ENABLE_RUE BSP_BIT32(7)
-#define DMAGRP_INTERRUPT_ENABLE_RSE BSP_BIT32(8)
-#define DMAGRP_INTERRUPT_ENABLE_RWE BSP_BIT32(9)
-#define DMAGRP_INTERRUPT_ENABLE_ETE BSP_BIT32(10)
-#define DMAGRP_INTERRUPT_ENABLE_FBE BSP_BIT32(13)
-#define DMAGRP_INTERRUPT_ENABLE_ERE BSP_BIT32(14)
-#define DMAGRP_INTERRUPT_ENABLE_AIE BSP_BIT32(15)
-#define DMAGRP_INTERRUPT_ENABLE_NIE BSP_BIT32(16)
+#define DMAGRP_INTERRUPT_ENABLE_TIE DWMAC_REGS_BIT32(0)
+#define DMAGRP_INTERRUPT_ENABLE_TSE DWMAC_REGS_BIT32(1)
+#define DMAGRP_INTERRUPT_ENABLE_TUE DWMAC_REGS_BIT32(2)
+#define DMAGRP_INTERRUPT_ENABLE_TJE DWMAC_REGS_BIT32(3)
+#define DMAGRP_INTERRUPT_ENABLE_OVE DWMAC_REGS_BIT32(4)
+#define DMAGRP_INTERRUPT_ENABLE_UNE DWMAC_REGS_BIT32(5)
+#define DMAGRP_INTERRUPT_ENABLE_RIE DWMAC_REGS_BIT32(6)
+#define DMAGRP_INTERRUPT_ENABLE_RUE DWMAC_REGS_BIT32(7)
+#define DMAGRP_INTERRUPT_ENABLE_RSE DWMAC_REGS_BIT32(8)
+#define DMAGRP_INTERRUPT_ENABLE_RWE DWMAC_REGS_BIT32(9)
+#define DMAGRP_INTERRUPT_ENABLE_ETE DWMAC_REGS_BIT32(10)
+#define DMAGRP_INTERRUPT_ENABLE_FBE DWMAC_REGS_BIT32(13)
+#define DMAGRP_INTERRUPT_ENABLE_ERE DWMAC_REGS_BIT32(14)
+#define DMAGRP_INTERRUPT_ENABLE_AIE DWMAC_REGS_BIT32(15)
+#define DMAGRP_INTERRUPT_ENABLE_NIE DWMAC_REGS_BIT32(16)
 	uint32_t reserved_20[2];
 	uint32_t axi_bus_mode;
-#define DMAGRP_AXI_BUS_MODE_UNDEFINED BSP_BIT32(0)
-#define DMAGRP_AXI_BUS_MODE_BLEND4 BSP_BIT32(1)
-#define DMAGRP_AXI_BUS_MODE_BLEND8 BSP_BIT32(2)
-#define DMAGRP_AXI_BUS_MODE_BLEND16 BSP_BIT32(3)
-#define DMAGRP_AXI_BUS_MODE_AXI_AAL BSP_BIT32(12)
-#define DMAGRP_AXI_BUS_MODE_ONEKBBE BSP_BIT32(13)
-#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) BSP_FLD32(val, 16, 19)
-#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 16, 19)
-#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
-#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) BSP_FLD32(val, 20, 23)
-#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 20, 23)
-#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23)
-#define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM BSP_BIT32(30)
-#define DMAGRP_AXI_BUS_MODE_EN_LPI BSP_BIT32(31)
+#define DMAGRP_AXI_BUS_MODE_UNDEFINED DWMAC_REGS_BIT32(0)
+#define DMAGRP_AXI_BUS_MODE_BLEND4 DWMAC_REGS_BIT32(1)
+#define DMAGRP_AXI_BUS_MODE_BLEND8 DWMAC_REGS_BIT32(2)
+#define DMAGRP_AXI_BUS_MODE_BLEND16 DWMAC_REGS_BIT32(3)
+#define DMAGRP_AXI_BUS_MODE_AXI_AAL DWMAC_REGS_BIT32(12)
+#define DMAGRP_AXI_BUS_MODE_ONEKBBE DWMAC_REGS_BIT32(13)
+#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) DWMAC_REGS_FLD32(val, 16, 19)
+#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 16, 19)
+#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 16, 19)
+#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) DWMAC_REGS_FLD32(val, 20, 23)
+#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 23)
+#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 23)
+#define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM DWMAC_REGS_BIT32(30)
+#define DMAGRP_AXI_BUS_MODE_EN_LPI DWMAC_REGS_BIT32(31)
 	uint32_t reserved_2c[11];
 	uint32_t hw_feature;
-#define DMAGRP_HW_FEATURE_MIISEL BSP_BIT32(0)
-#define DMAGRP_HW_FEATURE_GMIISEL BSP_BIT32(1)
-#define DMAGRP_HW_FEATURE_HDSEL BSP_BIT32(2)
-#define DMAGRP_HW_FEATURE_HASHSEL BSP_BIT32(4)
-#define DMAGRP_HW_FEATURE_ADDMACADRSEL BSP_BIT32(5)
-#define DMAGRP_HW_FEATURE_PCSSEL BSP_BIT32(6)
-#define DMAGRP_HW_FEATURE_SMASEL BSP_BIT32(8)
-#define DMAGRP_HW_FEATURE_RWKSEL BSP_BIT32(9)
-#define DMAGRP_HW_FEATURE_MGKSEL BSP_BIT32(10)
-#define DMAGRP_HW_FEATURE_MMCSEL BSP_BIT32(11)
-#define DMAGRP_HW_FEATURE_TSVER1SEL BSP_BIT32(12)
-#define DMAGRP_HW_FEATURE_TSVER2SEL BSP_BIT32(13)
-#define DMAGRP_HW_FEATURE_EEESEL BSP_BIT32(14)
-#define DMAGRP_HW_FEATURE_AVSEL BSP_BIT32(15)
-#define DMAGRP_HW_FEATURE_TXOESEL BSP_BIT32(16)
-#define DMAGRP_HW_FEATURE_RXTYP1COE BSP_BIT32(17)
-#define DMAGRP_HW_FEATURE_RXTYP2COE BSP_BIT32(18)
-#define DMAGRP_HW_FEATURE_RXFIFOSIZE BSP_BIT32(19)
-#define DMAGRP_HW_FEATURE_RXCHCNT(val) BSP_FLD32(val, 20, 21)
-#define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) BSP_FLD32GET(reg, 20, 21)
-#define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21)
-#define DMAGRP_HW_FEATURE_TXCHCNT(val) BSP_FLD32(val, 22, 23)
-#define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) BSP_FLD32GET(reg, 22, 23)
-#define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 22, 23)
-#define DMAGRP_HW_FEATURE_ENHDESSEL BSP_BIT32(24)
-#define DMAGRP_HW_FEATURE_ACTPHYIF(val) BSP_FLD32(val, 28, 30)
-#define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) BSP_FLD32GET(reg, 28, 30)
-#define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) BSP_FLD32SET(reg, val, 28, 30)
+#define DMAGRP_HW_FEATURE_MIISEL DWMAC_REGS_BIT32(0)
+#define DMAGRP_HW_FEATURE_GMIISEL DWMAC_REGS_BIT32(1)
+#define DMAGRP_HW_FEATURE_HDSEL DWMAC_REGS_BIT32(2)
+#define DMAGRP_HW_FEATURE_HASHSEL DWMAC_REGS_BIT32(4)
+#define DMAGRP_HW_FEATURE_ADDMACADRSEL DWMAC_REGS_BIT32(5)
+#define DMAGRP_HW_FEATURE_PCSSEL DWMAC_REGS_BIT32(6)
+#define DMAGRP_HW_FEATURE_SMASEL DWMAC_REGS_BIT32(8)
+#define DMAGRP_HW_FEATURE_RWKSEL DWMAC_REGS_BIT32(9)
+#define DMAGRP_HW_FEATURE_MGKSEL DWMAC_REGS_BIT32(10)
+#define DMAGRP_HW_FEATURE_MMCSEL DWMAC_REGS_BIT32(11)
+#define DMAGRP_HW_FEATURE_TSVER1SEL DWMAC_REGS_BIT32(12)
+#define DMAGRP_HW_FEATURE_TSVER2SEL DWMAC_REGS_BIT32(13)
+#define DMAGRP_HW_FEATURE_EEESEL DWMAC_REGS_BIT32(14)
+#define DMAGRP_HW_FEATURE_AVSEL DWMAC_REGS_BIT32(15)
+#define DMAGRP_HW_FEATURE_TXOESEL DWMAC_REGS_BIT32(16)
+#define DMAGRP_HW_FEATURE_RXTYP1COE DWMAC_REGS_BIT32(17)
+#define DMAGRP_HW_FEATURE_RXTYP2COE DWMAC_REGS_BIT32(18)
+#define DMAGRP_HW_FEATURE_RXFIFOSIZE DWMAC_REGS_BIT32(19)
+#define DMAGRP_HW_FEATURE_RXCHCNT(val) DWMAC_REGS_FLD32(val, 20, 21)
+#define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 21)
+#define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 21)
+#define DMAGRP_HW_FEATURE_TXCHCNT(val) DWMAC_REGS_FLD32(val, 22, 23)
+#define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 22, 23)
+#define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 22, 23)
+#define DMAGRP_HW_FEATURE_ENHDESSEL DWMAC_REGS_BIT32(24)
+#define DMAGRP_HW_FEATURE_ACTPHYIF(val) DWMAC_REGS_FLD32(val, 28, 30)
+#define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) DWMAC_REGS_FLD32GET(reg, 28, 30)
+#define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 28, 30)
 } dmagrp;
 
 #endif /* MAC_REGS_H */