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authorSebastian Huber <sebastian.huber@embedded-brains.de>2017-07-04 14:15:03 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2017-07-07 13:27:24 +0200
commit7e91901303219f10cf865906931c07c31d2e37f4 (patch)
tree10a618b93e7ecc300bcd961c8ef14ac64e931f54 /c/src/lib
parentbsps/arm: Fix bit field offset in GIC support (diff)
downloadrtems-7e91901303219f10cf865906931c07c31d2e37f4.tar.bz2
arm: Fix ARMv7-M interrupt processing4.11.2
Right after a "msr basepri_max, %[basepri]" instruction an interrupt service may still take place (observed at least on Cortex-M7). However, pendable service calls that are activated during this interrupt service may be delayed until interrupts are enable again. The _ARMV7M_Pendable_service_call() did not check that a thread dispatch is allowed. Move this test from _ARMV7M_Interrupt_service_leave() to _ARMV7M_Pendable_service_call(). Close #3060.
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