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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-04-06 16:05:01 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-04-06 16:05:01 +0000
commitec1123229d85fd6e3ef67ed376c13f8ecdc4393b (patch)
tree16b4e257b507896cd6c2ed172009e55d64f8579b /c/src/lib/libcpu
parent82e87e943811c60e8dab96e151e462f785d944c3 (diff)
downloadrtems-ec1123229d85fd6e3ef67ed376c13f8ecdc4393b.tar.bz2
2001-03-30 Eric Valette <valette@crf.canon.fr>
* mpc8xx/vectors/.cvsignore, mpc8xx/vectors/Makefile.am, mpc8xx/vectors/README, mpc8xx/vectors/align_h.S mpc8xx/vectors/vectors.S: These files were removed in support of switching the mpc8xx to the use the "new exception processing model."
Diffstat (limited to 'c/src/lib/libcpu')
-rw-r--r--c/src/lib/libcpu/powerpc/ChangeLog8
-rw-r--r--c/src/lib/libcpu/powerpc/mpc8xx/vectors/.cvsignore2
-rw-r--r--c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am33
-rw-r--r--c/src/lib/libcpu/powerpc/mpc8xx/vectors/README23
-rw-r--r--c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S430
-rw-r--r--c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S1300
6 files changed, 8 insertions, 1788 deletions
diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog
index c931fe5b5a..6ba97dd7af 100644
--- a/c/src/lib/libcpu/powerpc/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/ChangeLog
@@ -1,5 +1,13 @@
2001-03-30 Eric Valette <valette@crf.canon.fr>
+ * mpc8xx/vectors/.cvsignore, mpc8xx/vectors/Makefile.am,
+ mpc8xx/vectors/README, mpc8xx/vectors/align_h.S
+ mpc8xx/vectors/vectors.S: These files were removed in
+ support of switching the mpc8xx to the use the "new exception
+ processing model."
+
+2001-03-30 Eric Valette <valette@crf.canon.fr>
+
* mpc8xx/exceptions/.cvsignore, mpc8xx/exceptions/Makefile.am,
mpc8xx/exceptions/asm_utils.S, mpc8xx/exceptions/raw_exception.c,
mpc8xx/exceptions/raw_exception.h: New files.
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/.cvsignore b/c/src/lib/libcpu/powerpc/mpc8xx/vectors/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am
deleted file mode 100644
index 7714e52c0c..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am
+++ /dev/null
@@ -1,33 +0,0 @@
-##
-## $Id$
-##
-
-AUTOMAKE_OPTIONS = foreign 1.4
-
-VPATH = @srcdir@:@srcdir@/../../ppc403/vectors
-
-## FIXME
-
-PGM = ${ARCH}/vectors.rel
-
-## Assembly sources
-S_FILES = vectors.S align_h.S
-
-vectors_rel_OBJECTS = $(S_FILES:%.S=${ARCH}/%.o)
-
-include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
-include $(top_srcdir)/../../../../../automake/compile.am
-include $(top_srcdir)/../../../../../automake/lib.am
-
-#
-# (OPTIONAL) Add local stuff here using +=
-#
-
-$(PGM): $(vectors_rel_OBJECTS)
- $(make-rel)
-
-all-local: ${ARCH} $(PGM)
-
-EXTRA_DIST = vectors.S README
-
-include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/README b/c/src/lib/libcpu/powerpc/mpc8xx/vectors/README
deleted file mode 100644
index 974c8bdd43..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/README
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# $Id$
-#
-
-The location of the vectors file object is critical.
-
-From the comments at the head of vectors.S:
-
- The issue with this file is getting it loaded at the right place.
- The first vector MUST be at address 0x????0100.
- How this is achieved is dependant on the tool chain.
-
-...
-
- The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
- offset from 0x????0000 to the first location in the file. This
- will be either 0x0000 or 0xfff0.
-
-The eth_comm BSP defines PPC_VECTOR_FILE_BASE to be 0x00000000.
-The MBX8xx BSP also defines PPC_VECTOR_FILE_BASE to be 0x00000000.
-Change these values to 0xFFF00000 if your are implementing an actual
-boot rom.
-
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S b/c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S
deleted file mode 100644
index ec8d11257c..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S
+++ /dev/null
@@ -1,430 +0,0 @@
-/* align_h.S 1.1 - 95/12/04
- *
- * This file contains the assembly code for the MPC860
- * alignment exception handler for RTEMS.
- *
- * Based upon IBM provided code for the PowerPC 403 with the following release:
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *
- * Modifications:
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Additional modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
- * Removed saving and restoring of PPC403-specific SRR2 and SRR3.
- * Access DAR instead of PPC403-specific DEAR.
- *
- * $Id$
- */
-
-#include "asm.h"
-#define ALIGN_REGS 0x0140
-
-.set CACHE_SIZE,16 # cache line size of 32 bytes
-.set CACHE_SIZE_L2,4 # cache line size, log 2
-
-.set Open_gpr0,0
-.set Open_gpr1,4
-.set Open_gpr2,8
-.set Open_gpr3,12
-.set Open_gpr4,16
-.set Open_gpr5,20
-.set Open_gpr6,24
-.set Open_gpr7,28
-.set Open_gpr8,32
-.set Open_gpr9,36
-.set Open_gpr10,40
-.set Open_gpr11,44
-.set Open_gpr12,48
-.set Open_gpr13,52
-.set Open_gpr14,56
-.set Open_gpr15,60
-.set Open_gpr16,64
-.set Open_gpr17,68
-.set Open_gpr18,72
-.set Open_gpr19,76
-.set Open_gpr20,80
-.set Open_gpr21,84
-.set Open_gpr22,88
-.set Open_gpr23,92
-.set Open_gpr24,96
-.set Open_gpr25,100
-.set Open_gpr26,104
-.set Open_gpr27,108
-.set Open_gpr28,112
-.set Open_gpr29,116
-.set Open_gpr30,120
-.set Open_gpr31,124
-.set Open_xer,128
-.set Open_lr,132
-.set Open_ctr,136
-.set Open_cr,140
-.set Open_srr0,144
-.set Open_srr1,148
-
-
-/*
- * This code makes several assumptions for processing efficiency
- * * General purpose registers are continuous in the image, beginning with
- * Open_gpr0
- * * Hash table is highly dependent on opcodes - opcode changes *will*
- * require rework of the instruction decode mechanism.
- */
-
- .text
- .globl align_h
-
- .align CACHE_SIZE_L2
-align_h:
- /*-----------------------------------------------------------------------
- * Store GPRs in Open Reg save area
- * Set up r2 as base reg, r1 pointing to Open Reg save area
- *----------------------------------------------------------------------*/
- stmw r0,ALIGN_REGS(r0)
- li r1,ALIGN_REGS
- /*-----------------------------------------------------------------------
- * Store special purpose registers in reg save area
- *----------------------------------------------------------------------*/
- mfxer r7
- mflr r8
- mfcr r9
- mfctr r10
- stw r7,Open_xer(r1)
- stw r8,Open_lr(r1)
- stw r9,Open_cr(r1)
- stw r10,Open_ctr(r1)
- mfspr r9, srr0 /* SRR 0 */
- mfspr r10, srr1 /* SRR 1 */
- stw r9,Open_srr0(r1)
- stw r10,Open_srr1(r1)
-
-/* Set up common registers */
- mfspr r5, dar /* DAR: R5 is data (exception) address */
- lwz r9,Open_srr0(r1) /* get faulting instruction */
- addi r7,r9,4 /* bump instruction */
- stw r7,Open_srr0(r1) /* restore to image */
- lwz r9, 0(r9) /* retrieve actual instruction */
- rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
- rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
- bl ref_point /* establish addressibility */
-ref_point:
- mflr r11 /* r11 is the anchor point for ref_point */
- addi r10, r7, -31 /* r10 = r7 - 31 */
- rlwinm r10,r10,2,2,31 /* r10 *= 4 */
- add r10, r10, r11 /* r10 += anchor point */
- lwz r10, primary_jt-ref_point(r10)
- mtlr r10
- rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
- la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
- blr
-primary_jt:
- .long xform
- .long lwz
- .long lwzu
- .long 0
- .long 0
- .long stw
- .long stwu
- .long 0
- .long 0
- .long lhz
- .long lhzu
- .long lha
- .long lhau
- .long sth
- .long sthu
- .long lmw
- .long stmw
-/*
- * handlers
- */
-/*
- * xform instructions require an additional decode. Fortunately, a relatively
- * simple hash step breaks the instructions out with no collisions
- */
-xform:
- rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
- rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
- add r10,r7,r10 /* r10 = r7 + r10 */
- rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
- add r10,r10,r11 /* r10 += anchor point */
- lwz r10, secondary_ht-ref_point(r10)
- mtlr r10
- la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
- rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
- blrl
-
-secondary_ht:
- .long lhzux /* b 0 0x137 */
- .long lhax /* b 1 0x157 */
- .long lhaux /* b 2 0x177 */
- .long sthx /* b 3 0x197 */
- .long sthux /* b 4 0x1b7 */
- .long 0 /* b 5 */
- .long lwbrx /* b 6 0x216 */
- .long 0 /* b 7 */
- .long 0 /* b 8 */
- .long 0 /* b 9 */
- .long stwbrx /* b A 0x296 */
- .long 0 /* b B */
- .long 0 /* b C */
- .long 0 /* b D */
- .long lhbrx /* b E 0x316 */
- .long 0 /* b F */
- .long 0 /* b 10 */
- .long 0 /* b 11 */
- .long sthbrx /* b 12 0x396 */
- .long 0 /* b 13 */
- .long lwarx /* b 14 0x014 */
- .long dcbz /* b 15 0x3f6 */
- .long 0 /* b 16 */
- .long lwzx /* b 17 0x017 */
- .long lwzux /* b 18 0x037 */
- .long 0 /* b 19 */
- .long stwcx /* b 1A 0x096 */
- .long stwx /* b 1B 0x097 */
- .long stwux /* b 1C 0x0B7 */
- .long 0 /* b 1D */
- .long 0 /* b 1E */
- .long lhzx /* b 1F 0x117 */
-
-/*
- * for all handlers
- * r4 - Addressability to interrupt context
- * r5 - DAR address (faulting data address)
- * r6 - RA field * 4
- * r7 - Address of GPR 0 in image
- * r8 - RD field * 4
- * r9 - Failing instruction
- */
-
-/* Load halfword algebraic with update */
-lhau:
-/* Load halfword algebraic with update indexed */
-lhaux:
- stwx r5,r7,r6 /* update RA with effective addr */
-
-/* Load halfword algebraic */
-lha:
-/* Load halfword algebraic indexed */
-lhax:
- lswi r10,r5,2 /* load two bytes into r10 */
- srawi r10,r10,16 /* shift right 2 bytes, extending sign */
- stwx r10,r7,r8 /* update reg image */
- b align_complete /* return */
-
-/* Load Half Word Byte-Reversed Indexed */
-lhbrx:
- lswi r10,r5,2 /* load two bytes from DEAR into r10 */
- rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
- stwbrx r10,r7,r8 /* store reversed in reg image */
- b align_complete /* return */
-
-/* Load Half Word and Zero with Update */
-lhzu:
-/* Load Half Word and Zero with Update Indexed */
-lhzux:
- stwx r5,r7,r6 /* update RA with effective addr */
-
-/* Load Half Word and Zero */
-lhz:
-/* Load Half Word and Zero Indexed */
-lhzx:
- lswi r10,r5,2 /* load two bytes from DEAR into r10 */
- rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
- stwx r10,r7,r8 /* update reg image */
- b align_complete /* return */
-
-/*
- * Load Multiple Word
- */
-lmw:
- lwzx r9,r6,r7 /* R9 contains saved value of RA */
- addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
- rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
- subfic r8,r8,32 /* r8 is reg count to load */
- mtctr r8 /* load counter */
- addi r8,r8,-1 /* r8-- */
- rlwinm r8,r8,2,2,31 /* r8 *= 4 */
- add r5,r5,r8 /* update DEAR to point to last reg */
-lwmloop:
- lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
- stwu r11,-4(r10) /* load image and decrement pointer */
- addi r5,r5,-4 /* decrement effective address */
- bdnz lwmloop
- stwx r9,r6,r7 /* restore RA (in case it was trashed) */
- b align_complete /* return */
-
-/*
- * Load Word and Reserve Indexed
- */
-lwarx:
- lswi r10,r5,4 /* load four bytes from DEAR into r10 */
- stwx r10,r7,r8 /* update reg image */
- rlwinm r5,r5,0,0,29 /* Word align address */
- lwarx r10,0,r5 /* Set reservation */
- b align_complete /* return */
-
-/*
- * Load Word Byte-Reversed Indexed
- */
-lwbrx:
- lswi r10,r5,4 /* load four bytes from DEAR into r10 */
- stwbrx r10,r7,r8 /* store reversed in reg image */
- b align_complete /* return */
-
-/* Load Word and Zero with Update */
-lwzu:
-/* Load Word and Zero with Update Indexed */
-lwzux:
- stwx r5,r7,r6 /* update RA with effective addr */
-
-/* Load Word and Zero */
-lwz:
-/* Load Word and Zero Indexed */
-lwzx:
- lswi r10,r5,4 /* load four bytes from DEAR into r10 */
- stwx r10,r7,r8 /* update reg image */
- b align_complete /* return */
-
-/* Store instructions */
-
-/* */
-/* Store Half Word and Update */
-sthu:
-/* Store Half Word and Update Indexed */
-sthux:
- stwx r5,r7,r6 /* Update RA with effective address */
-
-/* Store Half Word */
-sth:
-/* Store Half Word Indexed */
-sthx:
- lwzx r10,r8,r7 /* retrieve source register value */
- rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
- stswi r10,r5,2 /* store bytes to DEAR address */
- b align_complete /* return */
-
-/* */
-/* Store Half Word Byte-Reversed Indexed */
-sthbrx:
- lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
- stswi r10,r5,2 /* move two bytes to DEAR address */
- b align_complete /* return */
-
-/* */
-/* Store Multiple Word */
-stmw:
- addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
- rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
- subfic r8,r8,32 /* r8 is reg count to load */
- mtctr r8 /* load counter */
- addi r8,r8,-1 /* r8-- */
- rlwinm r8,r8,2,2,31 /* r8 *= 4 */
- add r5,r5,r8 /* update DEAR to point to last reg */
-stmloop:
- lwzu r11,-4(r10) /* get register value */
- stswi r11,r5,4 /* output to DEAR address */
- addi r5,r5,-4 /* decrement effective address */
- bdnz stmloop
- b align_complete /* return */
-
-/* */
-/* Store Word and Update */
-stwu:
-/* Store Word and Update Indexed */
-stwux:
- stwx r5,r7,r6 /* Update RA with effective address */
-
-/* Store Word */
-stw:
-/* Store Word Indexed */
-stwx:
- lwzx r10,r8,r7 /* retrieve source register value */
- stswi r10,r5,4 /* store bytes to DEAR address */
- b align_complete /* return */
-
-/* */
-/* Store Word Byte-Reversed Indexed */
-stwbrx:
- lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
- stswi r10,r5,4 /* move two bytes to DEAR address */
- b align_complete /* return */
-
-/* */
-/* Store Word Conditional Indexed */
-stwcx:
- rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
- lwz r11,0(r10) /* save original value of store */
- stwcx. r11,r0,r10 /* attempt store to address */
- bne stwcx_moveon /* store failed, move on */
- stw r11,0(r10) /* repair damage */
- lwzx r9,r7,r8 /* get register value */
- stswi r10,r5,4 /* store bytes to DEAR address */
-stwcx_moveon:
- mfcr r11 /* get condition reg */
- lwz r9,Open_cr(r1) /* get condition reg image */
- rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
- lwz r11,Open_xer(r1) /* get XER reg */
- rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
- stw r9,Open_cr(r1) /* store cr image */
- b align_complete /* return */
-
-/* */
-/* Data Cache Block Zero */
-dcbz:
- rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
- /* get address to nearest Cache line */
- addi r5,r5,-4 /* adjust by a word */
- addi r10,r0,CACHE_SIZE/4 /* set counter value */
- mtctr r10
- addi r11,r0,0 /* r11 = 0 */
-dcbz_loop:
- stwu r11,4(r5) /* store a word and update EA */
- bdnz dcbz_loop
- b align_complete /* return */
-
-align_complete:
- /*-----------------------------------------------------------------------
- * Restore regs and return from the interrupt
- *----------------------------------------------------------------------*/
- lmw r26,Open_xer+ALIGN_REGS(r0)
- mtxer r26
- mtlr r27
- mtctr r28
- mtcrf 0xFF, r29
- mtspr srr0, r30 /* SRR 0 */
- mtspr srr1, r31 /* SRR 1 */
- lmw r1,Open_gpr1+ALIGN_REGS(r0)
- lwz r0,Open_gpr0+ALIGN_REGS(r0)
- rfi
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S
deleted file mode 100644
index 43e6f1f056..0000000000
--- a/c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S
+++ /dev/null
@@ -1,1300 +0,0 @@
-/* vectors.S 1.1 - 95/12/04
- *
- * This file contains the assembly code for the PowerPC MPC8xx
- * interrupt veneers for RTEMS.
- *
- * Author: Jay Monkman (jmonkman@frasca.com)
- *
- * Copyright (C) 1998 by Frasca International, Inc.
- *
- * Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s:
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Dwarf debugging info added by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
- * Also, made changes to turn address translation back on.
- *
- * Modifications for to add DWARF debugging info, turn address translation on
- * and to coexist with EPPCBug:
- * Copyright (c) 1999, National Research Council of Canada
- *
- */
-
-/*
- * The issue with this file is getting it loaded at the right place.
- * The first vector MUST be at address 0x????0100.
- * How this is achieved is dependant on the tool chain.
- *
- * However the basic mechanism for ELF assemblers is to create a
- * section called ".vectors", which will be loaded to an address
- * between 0x????0000 and 0x????0100 (inclusive) via a link script.
- *
- * The basic mechanism for XCOFF assemblers is to place it in the
- * normal text section, and arrange for this file to be located
- * at an appropriate position on the linker command line.
- *
- * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
- * offset from 0x????0000 to the first location in the file. This
- * will be either 0x0000 or 0xfff0.
- *
- * If EPPCBUG_VECTORS is #defined, vectors 0x100 (system reset),
- * 0x700 (program), 0xC00 (system call) and 0xD00 (trace) are set
- * up identically to the EPPCBug vectors in order to preserve the
- * firmware runtime environment.
- *
- * THE FOUR ABOVE VECTORS MAY NEED TO BE MODIFIED TO MATCH YOUR
- * REVISION OF THE FIRMWARE.
- *
- * Coexisting with the firmware only makes sense when the
- * PPC_VECTOR_FILE_BASE is 0.
- *
- * $Id$
- */
-
-#include "asm.h"
-#include <mpc8xx.h>
-
-/* Location of your rtems source tree for source-level debugging purposes */
-#define PATH_PREFIX "/home/stewart"
-
-#ifndef PPC_VECTOR_FILE_BASE
-#error "PPC_VECTOR_FILE_BASE is not defined."
-#endif
-
- /* Where this file will be loaded */
- .set file_base, PPC_VECTOR_FILE_BASE
-
- /* Offset to store reg 0 */
-
- .set IP_LINK, 0
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
- .set IP_0, (IP_LINK + 56)
-#else
- .set IP_0, (IP_LINK + 8)
-#endif
- .set IP_2, (IP_0 + 4)
-
- .set IP_3, (IP_2 + 4)
- .set IP_4, (IP_3 + 4)
- .set IP_5, (IP_4 + 4)
- .set IP_6, (IP_5 + 4)
-
- .set IP_7, (IP_6 + 4)
- .set IP_8, (IP_7 + 4)
- .set IP_9, (IP_8 + 4)
- .set IP_10, (IP_9 + 4)
-
- .set IP_11, (IP_10 + 4)
- .set IP_12, (IP_11 + 4)
- .set IP_13, (IP_12 + 4)
- .set IP_28, (IP_13 + 4)
-
- .set IP_29, (IP_28 + 4)
- .set IP_30, (IP_29 + 4)
- .set IP_31, (IP_30 + 4)
- .set IP_CR, (IP_31 + 4)
-
- .set IP_CTR, (IP_CR + 4)
- .set IP_XER, (IP_CTR + 4)
- .set IP_LR, (IP_XER + 4)
- .set IP_PC, (IP_LR + 4)
-
- .set IP_MSR, (IP_PC + 4)
-
- .set IP_END, (IP_MSR + 16)
-
- /* Vector offsets */
- .set begin_vector, 0x0000
- .set reset_vector, 0x0100
- .set mach_vector, 0x0200
- .set dsi_vector, 0x0300
- .set isi_vector, 0x0400
- .set ext_vector, 0x0500
- .set align_vector, 0x0600
- .set prog_vector, 0x0700
- .set float_vector, 0x0800
- .set dec_vector, 0x0900
- .set sys_vector, 0x0C00
- .set trace_vector, 0x0d00
- .set syscall_vector, 0x0c00
- .set fpassist_vector, 0x0e00
- .set software_vector, 0x1000
- .set itlbm_vector, 0x1100
- .set dtlbm_vector, 0x1200
- .set itlbe_vector, 0x1300
- .set dtlbe_vector, 0x1400
- .set databkpt_vector, 0x1c00
- .set insbkpt_vector, 0x1d00
- .set perbkpt_vector, 0x1e00
- .set dev_vector, 0x1f00
- .set siu_vector, 0x2000
- .set cpm_vector, 0x2400
-
-/* Go to the right section */
-#if PPC_ASM == PPC_ASM_XCOFF
- .csect .text[PR]
-#elif PPC_ASM == PPC_ASM_ELF
- .section .vectors,"awx",@progbits
-.L_text_b:
-.L_LC1:
- .previous
-
-.section .debug_sfnames
-.L_sfnames_b:
- .byte PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
- .byte 0
-.L_F0:
- .byte "vectors.S"
- .byte 0
- .previous
-
-.section .line
-.L_line_b:
- .4byte .L_line_e-.L_line_b
- .4byte .L_text_b
-.L_LE1:
-.L_line_last:
- .4byte 0x0
- .2byte 0xffff
- .4byte .L_text_e-.L_text_b
-.L_line_e:
- .previous
-
-.section .debug_srcinfo
-.L_srcinfo_b:
- .4byte .L_line_b
- .4byte .L_sfnames_b
- .4byte .L_text_b
- .4byte .L_text_e
- .4byte 0xffffffff
- .4byte .L_LE1-.L_line_b
- .4byte .L_F0-.L_sfnames_b
- .4byte .L_line_last-.L_line_b
- .4byte 0xffffffff
- .previous
-
-.section .debug_pubnames
- .4byte .L_debug_b
- .4byte .L_P0
- .byte "__vectors"
- .byte 0
- .4byte 0x0
- .byte 0
- .previous
-
-.section .debug_aranges
- .4byte .L_debug_b
- .4byte .L_text_b
- .4byte .L_text_e-.L_text_b
- .4byte 0
- .4byte 0
- .4byte 0
- .4byte 0
- .4byte 0
- .4byte 0
- .4byte 0x0
- .4byte 0x0
- .previous
-
-.section .debug
-.L_debug_b:
-.L_D1:
- .4byte .L_D1_e-.L_D1
- .2byte 0x11 /* TAG_compile_unit */
- .2byte 0x12 /* AT_sibling */
- .4byte .L_D2
- .2byte 0x38 /* AT_name */
- .byte "vectors.S"
- .byte 0
- .2byte 0x258 /* AT_producer */
- .byte "GAS 2.5.2"
- .byte 0
- .2byte 0x111 /* AT_low_pc */
- .4byte .L_text_b
- .2byte 0x121 /* AT_high_pc */
- .4byte .L_text_e
- .2byte 0x106 /* AT_stmt_list */
- .4byte .L_line_b
- .2byte 0x1b8 /* AT_comp_dir */
- .byte PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
- .byte 0
- .2byte 0x8006 /* AT_sf_names */
- .4byte .L_sfnames_b
- .2byte 0x8016 /* AT_src_info */
- .4byte .L_srcinfo_b
-.L_D1_e:
-.L_P0:
-.L_D3:
- .4byte .L_D3_e-.L_D3
- .2byte 0x6 /* TAG_global_subroutine */
- .2byte 0x12 /* AT_sibling */
- .4byte .L_D4
- .2byte 0x38 /* AT_name */
- .byte "__vectors"
- .byte 0
- .2byte 0x278 /* AT_prototyped */
- .byte 0
- .2byte 0x111 /* AT_low_pc */
- .4byte .L_text_b
- .2byte 0x121 /* AT_high_pc */
- .4byte .L_text_e
- .2byte 0x8041 /* AT_body_begin */
- .4byte .L_text_b
- .2byte 0x8051 /* AT_body_end */
- .4byte .L_text_e
-.L_D3_e:
-
-.L_D4:
- .4byte .L_D4_e-.L_D4
- .align 2
-.L_D4_e:
-.L_D2:
- .previous
-
- .section .vectors
-#endif /* PPC_ASM_ELF */
-
- PUBLIC_VAR (__vectors)
-SYM (__vectors):
-
-
-/* 0x100 -- Critical error handling */
- .org reset_vector - file_base
-base_vectors:
-
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE003EF8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif /* PPC_HAS_FPU */
-#else
- stwu r1, -(IP_END)(r1)
-#endif /* PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27 */
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_SYSTEM_RESET
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x200 -- Machine check exception */
- .org mach_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE003DF8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_MCHECK
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x300 -- Protection exception */
- .org dsi_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE003CF8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_PROTECT
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x400 -- Instruction Storage exception */
- .org isi_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE003BF8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_ISI
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x500 -- External interrupt */
-/* When an external interrupt occurs, we must find out what caused it */
-/* before calling the RTEMS handler. First we use SIVEC to decide */
-/* what signalled the interrupt to the SIU. */
- .org ext_vector - file_base
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- stw r9, IP_9(r1) /* r9 will be restored in the next level */
- stw r10, IP_10(r1)
-
- lis r9, m8xx@ha
- addi r9, r9, m8xx@l
- lbz r10, 0x1c(r9) /* SIVEC */
- rlwinm r10, r10, 4, 0, 27 /* each psuedo vector will have */
- /* room for 16 instructions */
- addis r10, r10, siu_vectors@ha
- addi r10, r10, siu_vectors@l
- mflr r0
- mtlr r10
- lwz r10, IP_10(r1)
- blr
-
-
-/* 0x600 -- Align exception */
- .org align_vector - file_base
- .extern align_h
- b align_h
-
-
-/* 0x700 -- Program exception */
- .org prog_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0038F8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_PROGRAM
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x800 -- Float exception */
- .org float_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0037F8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_NOFP
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x900 -- Decrementer exception */
- .org dec_vector - file_base
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_DECREMENTER
- b PROC (_ISR_Handler)
-
-
-/* 0xC00 -- System call */
- .org sys_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0033F8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_SCALL
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0xD00 -- Trace interrupt */
- .org trace_vector - file_base
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0032F8 /* 0xFE004004 */
-#else
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
- stwu r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
- stwu r1, -(20*4 + IP_END)(r1)
-#endif
-#else
- stwu r1, -(IP_END)(r1)
-#endif
- stw r0, IP_0(r1)
-
- /* Turn address translation back on to re-enable the caches. */
- mfmsr r0
- ori r0, r0, 0x30
- mtmsr r0
-
- li r0, PPC_IRQ_TRACE
- b PROC (_ISR_Handler)
-#endif /* EPPCBUG_VECTORS */
-
-
-#ifdef EPPCBUG_VECTORS
-/* 0xE00 -- Floating Point Assist */
- .org fpassist_vector - file_base
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0031F8 /* 0xFE004004 */
-
-/* 0x1000 -- Software Emulation */
- .org software_vector - file_base
-software_vectors:
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE002FF8 /* 0xFE004004 */
-#endif
-
-
-/* 0x1100 -- Intruction TLB Miss */
- .org itlbm_vector - file_base
-itlbm_vectors:
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE002EF8 /* 0xFE004004 */
-#else
- mfspr r2, 784 /* MI_CTR */
- mfspr r3, 792 /* MD_CTR */
- mfspr r4, 787 /* MI_EPN */
- mfspr r5, 789 /* MI_TWC */
- mfspr r6, 797 /* MD_TWC */
- mfspr r7, 789 /* MI_TWC */
- mfspr r8, 790 /* MI_RPN */
- mfspr r9, 798 /* MD_RPN */
- mfspr r10, 796 /* M_TWB */
- mfspr r11, 793 /* M_CASID */
- mfspr r12, 786 /* MI_AP */
- mfspr r13, 794 /* MD_AP */
- mfspr r14, 799 /* M_TW */
- mfspr r15, 816 /* MI_CAM */
- mfspr r16, 817 /* MI_RAM0 */
- mfspr r17, 818 /* MI_RAM1 */
- mfspr r18, 824 /* MD_CAM */
- mfspr r19, 825 /* M_RAM0 */
- mfspr r20, 826 /* M_RAM1 */
- .long 0
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x1200 -- Data TLB Miss */
- .org dtlbm_vector - file_base
-dtlbm_vectors:
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE002DF8 /* 0xFE004004 */
-#else
- mfspr r1, 0x1a
- mfspr r2, 784 /* MI_CTR */
- mfspr r3, 792 /* MD_CTR */
- lis r3, 0x400
- mtspr 792, r3
- mfspr r4, 787 /* MI_EPN */
- mfspr r5, 789 /* MI_TWC */
- mfspr r6, 797 /* MD_TWC */
- mfspr r7, 789 /* MI_TWC */
- mfspr r8, 790 /* MI_RPN */
- mfspr r9, 798 /* MD_RPN */
- mfspr r10, 796 /* M_TWB */
- mfspr r11, 793 /* M_CASID */
- mfspr r12, 786 /* MI_AP */
- mfspr r13, 794 /* MD_AP */
- mfspr r14, 799 /* M_TW */
- mfspr r15, 816 /* MI_CAM */
- mfspr r16, 817 /* MI_RAM0 */
- mfspr r17, 818 /* MI_RAM1 */
- mtspr 824, r18
- mfspr r18, 824 /* MD_CAM */
- mfspr r19, 825 /* M_RAM0 */
- mfspr r20, 826 /* M_RAM1 */
- .long 0
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x1300 -- Instruction TLB Error */
- .org itlbe_vector - file_base
-itlbe_vectors:
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE002CF8 /* 0xFE004004 */
-#else
- mfspr r2, 784 /* MI_CTR */
- mfspr r3, 792 /* MD_CTR */
- mfspr r4, 787 /* MI_EPN */
- mfspr r5, 789 /* MI_TWC */
- mfspr r6, 797 /* MD_TWC */
- mfspr r7, 789 /* MI_TWC */
- mfspr r8, 790 /* MI_RPN */
- mfspr r9, 798 /* MD_RPN */
- mfspr r10, 796 /* M_TWB */
- mfspr r11, 793 /* M_CASID */
- mfspr r12, 786 /* MI_AP */
- mfspr r13, 794 /* MD_AP */
- mfspr r14, 799 /* M_TW */
- mfspr r15, 816 /* MI_CAM */
- mfspr r16, 817 /* MI_RAM0 */
- mfspr r17, 818 /* MI_RAM1 */
- mfspr r18, 824 /* MD_CAM */
- mfspr r19, 825 /* M_RAM0 */
- mfspr r20, 826 /* M_RAM1 */
- .long 0
-#endif /* EPPCBUG_VECTORS */
-
-
-/* 0x1400 -- Data TLB Error */
- .org dtlbe_vector - file_base
-dtlbe_vectors:
-#ifdef EPPCBUG_VECTORS
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE002BF8 /* 0xFE004004 */
-#else
- mfspr r2, 784 /* MI_CTR */
- mfspr r3, 792 /* MD_CTR */
- mfspr r4, 787 /* MI_EPN */
- mfspr r5, 789 /* MI_TWC */
- mfspr r6, 797 /* MD_TWC */
- mfspr r7, 789 /* MI_TWC */
- mfspr r8, 790 /* MI_RPN */
- mfspr r9, 798 /* MD_RPN */
- mfspr r10, 796 /* M_TWB */
- mfspr r11, 793 /* M_CASID */
- mfspr r12, 786 /* MI_AP */
- mfspr r13, 794 /* MD_AP */
- mfspr r14, 799 /* M_TW */
- mfspr r15, 816 /* MI_CAM */
- mfspr r16, 817 /* MI_RAM0 */
- mfspr r17, 818 /* MI_RAM1 */
- mfspr r18, 824 /* MD_CAM */
- mfspr r19, 825 /* M_RAM0 */
- mfspr r20, 826 /* M_RAM1 */
- .long 0
-#endif /* EPPCBUG_VECTORS */
-
-
-#ifdef EPPCBUG_VECTORS
-/* 0x1C00 -- Data Breakpoint */
- .org databkpt_vector - file_base
-databkpt_vectors:
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0023F8 /* 0xFE004004 */
-
-/* 0x1D00 -- Instruction Breakpoint */
- .org insbkpt_vector - file_base
-insbkpt_vectors:
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0022F8 /* 0xFE004004 */
-
-/* 0x1E00 -- Peripheral Breakpoint */
- .org perbkpt_vector - file_base
-perbkpt_vectors:
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0021F8 /* 0xFE004004 */
-
-/* 0x1F00 -- Non-Makable Development Port */
- .org dev_vector - file_base
-dev_vectors:
- mtsprg 0, r1
- mflr r1
- mtsprg 1, r1
- bl 0xFE0020F8 /* 0xFE004004 */
-#endif
-
-
-
-/* Now we look at what signaled the interrupt to the SIU. */
-/* I needed to do this in order to decode the CPM interrupts before */
-/* calling _ISR_Handler */
-
-/* *IRQ0 */
- .org siu_vector - file_base
-siu_vectors:
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ0
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 0 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL0
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ1
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* This is probably not the "correct" way to do this. I need to have a
- * way of calling _ISR_Handler for the CPM interrupts and this is the
- * simplest way I can think of. Since I have the CPM interrupt mapped
- * to the SIU interrupt level 1 on the eth-comm board, I put it here.
- * It would probably be ok if I moved this directory to under libbsp
- * instead of libcpu. For now, deal with it.
-*/
-/* Level 1 - CPM */
-/* Now we need to get the CPM interrupt vector */
- /* Registers: */
- /* R0 - has stored value of LR */
- /* R9 - pointer to m8xx struct */
- /* R10 has already been saved and restored */
- li r10, 1
- sth r10, 0x930(r9) /* CIVR */
- lbz r10, 0x930(r9) /* if we use this as an offset into a */
- rlwinm r10, r10, 1, 0, 31 /* table, each entry will have room */
- /* 4 instructions. */
- addis r10, r10, cpm_vectors@ha
- addi r10, r10, cpm_vectors@l
-
- mtlr r10
- lwz r10, IP_10(r1)
- blr
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-#if 0
-/* Level 1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL1
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-#endif
-
-/* *IRQ2 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ2
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 2 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL2
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ3 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ3
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 3 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL3
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ4 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ4
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 4 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL4
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ5 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ5
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 5 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL5
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ6 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ6
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 6 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL6
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* *IRQ7 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_IRQ7
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-/* Level 7 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_LVL7
- b PROC (_ISR_Handler)
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
-
-/* .org cpm_vector - file_base*/
-cpm_vectors:
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_ERROR
- b PROC (_ISR_Handler)
-
- /* PC4 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC4
- b PROC (_ISR_Handler)
-
- /* PC5 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC5
- b PROC (_ISR_Handler)
-
- /* SMC2 / PIP */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SMC2
- b PROC (_ISR_Handler)
-
- /* SMC1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SMC1
- b PROC (_ISR_Handler)
-
- /* SPI */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SPI
- b PROC (_ISR_Handler)
-
- /* PC6 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC6
- b PROC (_ISR_Handler)
-
- /* Timer 4 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_TIMER4
- b PROC (_ISR_Handler)
-
- /* Reserved - we should never see this */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_RESERVED_8
- .long 0
-
- /* PC7 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC7
- b PROC (_ISR_Handler)
-
- /* PC8 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC8
- b PROC (_ISR_Handler)
-
- /* PC9 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC9
- b PROC (_ISR_Handler)
-
- /* Timer 3 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_TIMER3
- b PROC (_ISR_Handler)
-
- /* Reserved - we should never get here */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_RESERVED_D
- .long 0
-
- /* PC10 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC10
- b PROC (_ISR_Handler)
-
- /* PC11 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC11
- b PROC (_ISR_Handler)
-
- /* I2C */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_I2C
- b PROC (_ISR_Handler)
-
- /* RISC Timer Table */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_RISC_TIMER
- b PROC (_ISR_Handler)
-
- /* Timer 2 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_TIMER2
- b PROC (_ISR_Handler)
-
- /* Reserved - we should never get here */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_RESERVED_13
- .long 0
-
- /* IDMA2 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_IDMA2
- b PROC (_ISR_Handler)
-
- /* IDMA1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_IDMA1
- b PROC (_ISR_Handler)
-
- /* SDMA Channel Bus Error */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SDMA_ERROR
- b PROC (_ISR_Handler)
-
- /* PC12 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC12
- b PROC (_ISR_Handler)
-
- /* PC13 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC13
- b PROC (_ISR_Handler)
-
- /* Timer 1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_TIMER1
- b PROC (_ISR_Handler)
-
- /* PC14 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC14
- b PROC (_ISR_Handler)
-
- /* SCC4 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SCC4
- b PROC (_ISR_Handler)
-
- /* SCC3 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SCC3
- b PROC (_ISR_Handler)
-
- /* SCC2 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SCC2
- b PROC (_ISR_Handler)
-
- /* SCC1 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_SCC1
- b PROC (_ISR_Handler)
-
- /* PC15 */
- mtlr r0
- lwz r9, IP_9(r1)
- li r0, PPC_IRQ_CPM_PC15
- b PROC (_ISR_Handler)
-
-.L_text_e:
-
-