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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-01-12 13:38:01 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-01-12 13:38:01 +0000
commit5c27c8053b0427266dea64705a4ddae763d19014 (patch)
tree77986fa2c7fe46bf4664e99092c284f90377594f /c/src/lib/libcpu
parent2001-01-12 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-5c27c8053b0427266dea64705a4ddae763d19014.tar.bz2
2001-01-12 Joel Sherrill <joel@OARcorp.com>
* r46xx/vectorisrs/vectorisrs.c (mips_get_cause): Corrected constraints from general to register. * tx39/vectorisrs/vectorisrs.c (mips_get_cause): Corrected constraints from general to register.
Diffstat (limited to 'c/src/lib/libcpu')
-rw-r--r--c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c2
-rw-r--r--c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
index 8f2a2f1c3c..31059e7d57 100644
--- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c
@@ -7,7 +7,7 @@
#define mips_get_cause( _cause ) \
do { \
- asm volatile( "mfc0 %0, $13; nop" : "=g" (_cause) : ); \
+ asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \
} while (0)
#define CALL_ISR(_vector) \
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
index db31d751e5..027e075119 100644
--- a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
@@ -8,7 +8,7 @@
#define mips_get_cause( _cause ) \
do { \
- asm volatile( "mfc0 %0, $13; nop" : "=g" (_cause) : ); \
+ asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) : ); \
} while (0)
#define CALL_ISR(_vector) \