diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 21:34:51 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-12 21:34:51 +0000 |
| commit | 3ab61f0a35a49fa26dde66047235935094582dd3 (patch) | |
| tree | c472b1a0c24736017a9158e91aea7cced1ad8482 /c/src/lib/libcpu | |
| parent | Fixed so hppa1.1 compiles with only problems in simhppa BSP. (diff) | |
| download | rtems-3ab61f0a35a49fa26dde66047235935094582dd3.tar.bz2 | |
Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860.
Diffstat (limited to 'c/src/lib/libcpu')
39 files changed, 0 insertions, 7242 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc821/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/Makefile.am deleted file mode 100644 index a5679c9061..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/Makefile.am +++ /dev/null @@ -1,10 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -SUBDIRS = include console-generic clock timer vectors - -include $(top_srcdir)/../../../../../automake/subdirs.am -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/clock/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/clock/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/clock/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/clock/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/clock/Makefile.am deleted file mode 100644 index f8b46ecc12..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/clock/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/clock.rel - -C_FILES = clock.c - -clock_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(clock_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(clock_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = clock.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc821/clock/clock.c deleted file mode 100644 index b380758970..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/clock/clock.c +++ /dev/null @@ -1,178 +0,0 @@ -/* clock.c - * - * This routine initializes the PIT on the MPC821. - * The tick frequency is specified by the bsp. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <clockdrv.h> -#include <rtems/libio.h> - -#include <stdlib.h> /* for atexit() */ -#include <mpc821.h> - -volatile rtems_unsigned32 Clock_driver_ticks; -extern volatile m821_t m821; - -void Clock_exit( void ); - -/* - * These are set by clock driver during its init - */ - -rtems_device_major_number rtems_clock_major = ~0; -rtems_device_minor_number rtems_clock_minor; - -/* - * ISR Handler - */ -rtems_isr Clock_isr(rtems_vector_number vector) -{ - m821.piscr |= M821_PISCR_PS; - Clock_driver_ticks++; - rtems_clock_tick(); -} - -void Install_clock(rtems_isr_entry clock_isr) -{ - rtems_isr_entry previous_isr; - rtems_unsigned32 pit_value; - - Clock_driver_ticks = 0; - - pit_value = rtems_configuration_get_microseconds_per_tick() / - rtems_cpu_configuration_get_clicks_per_usec(); - if (pit_value == 0) { - pit_value = 0xffff; - } else { - pit_value--; - } - - if (pit_value > 0xffff) { /* pit is only 16 bits long */ - rtems_fatal_error_occurred(-1); - } - - /* - * initialize the interval here - * First tick is set to right amount of time in the future - * Future ticks will be incremented over last value set - * in order to provide consistent clicks in the face of - * interrupt overhead - */ - - rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); - - m821.sccr &= ~(1<<24); - m821.pitc = pit_value; - - /* set PIT irq level, enable PIT, PIT interrupts */ - /* and clear int. status */ - m821.piscr = M821_PISCR_PIRQ(0) | - M821_PISCR_PTE | M821_PISCR_PS | M821_PISCR_PIE; - - m821.simask |= M821_SIMASK_LVM0; - atexit(Clock_exit); -} - -void -ReInstall_clock(rtems_isr_entry new_clock_isr) -{ - rtems_isr_entry previous_isr; - rtems_unsigned32 isrlevel = 0; - - rtems_interrupt_disable(isrlevel); - - rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr); - - rtems_interrupt_enable(isrlevel); -} - - -/* - * Called via atexit() - * Remove the clock interrupt handler by setting handler to NULL - */ -void -Clock_exit(void) -{ - /* disable PIT and PIT interrupts */ - m821.piscr &= ~(M821_PISCR_PTE | M821_PISCR_PIE); - - (void) set_vector(0, PPC_IRQ_LVL0, 1); -} - -rtems_device_driver Clock_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - Install_clock( Clock_isr ); - - /* - * make major/minor avail to others such as shared memory driver - */ - - rtems_clock_major = major; - rtems_clock_minor = minor; - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver Clock_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - rtems_libio_ioctl_args_t *args = pargp; - - if (args == 0) - goto done; - - /* - * This is hokey, but until we get a defined interface - * to do this, it will just be this simple... - */ - - if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { - Clock_isr(PPC_IRQ_LVL0); - } - else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); - } - - done: - return RTEMS_SUCCESSFUL; -} - diff --git a/c/src/lib/libcpu/powerpc/mpc821/console-generic/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/console-generic/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/console-generic/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/console-generic/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/console-generic/Makefile.am deleted file mode 100644 index b0c900fc7c..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/console-generic/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/console-generic.rel - -C_FILES = console-generic.c - -console_generic_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(console_generic_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(console_generic_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = console-generic.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc821/console-generic/console-generic.c deleted file mode 100644 index f93022f142..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/console-generic/console-generic.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - * General Serial I/O functions. - * - * This file contains the functions for performing serial I/O. - * The actual system calls (console_*) should be in the BSP part - * of the source tree. That way different BSPs can use whichever - * SMCs and SCCs they want. Originally, all the stuff was in - * this file, and it caused problems with one BSP using SCC2 - * as /dev/console, others using SMC1 for /dev/console, etc. - * - * On-chip resources used: - * resource minor note - * SMC1 0 - * SMC2 1 - * SCC1 2 (shared with ethernet driver) - * SCC2 3 - * BRG1 - * BRG2 - * BRG3 - * BRG4 - * Author: Jay Monkman (jmonkman@frasca.com) - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: - * - * Author: - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/libio.h> -#include <mpc821.h> -#include <mpc821/console.h> -#include <stdlib.h> -#include <unistd.h> -#include <termios.h> - -#define NIFACES 4 /* number of console devices (serial ports) */ - -static Buf_t *rxBufList[NIFACES]; -static Buf_t *rxBufListTail[NIFACES]; - -/* - * Interrupt-driven input buffer - */ -#define RXBUFSIZE 16 - - -/* - * I/O buffers and pointers to buffer descriptors - */ -static volatile char txBuf[NIFACES]; - -static volatile m821BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; - -/* - * Device-specific routines - */ -static int m821_get_brg_cd(int); -unsigned char m821_get_brg_clk(int); -unsigned char m821_get_brg_clk(int); - - -/* - * Compute baud-rate-generator configuration register value - */ -static int -m821_get_brg_cd (int baud) -{ - int divisor; - int div16 = 0; - - divisor = ((rtems_cpu_configuration_get_clock_speed() / 16) + - (baud / 2)) / baud; - if (divisor > 4096) { - div16 = 1; - divisor = (divisor + 8) / 16; - } - return M821_BRG_EN | M821_BRG_EXTC_BRGCLK | - ((divisor - 1) << 1) | div16; -} - - -/* this function will fail if more that 4 baud rates have been selected */ -/* at any time since the OS started. It needs to be fixed. FIXME */ -unsigned char m821_get_brg_clk(int baud) -{ - static int brg_spd[4]; - static char brg_used[4]; - int i; - - /* first try to find a BRG that is already at the right speed */ - for (i=0; i<4; i++) { - if (brg_spd[i] == baud) { - break; - } - } - - if (i==4) { /* I guess we didn't find one */ - for (i=0; i<4; i++) { - if (brg_used[i] == 0) { - break; - } - } - } - if (i != 4) { - brg_used[i]++; - brg_spd[i]=baud; - switch (i) { - case 0: - m821.brgc1 = M821_BRG_RST; - m821.brgc1 = m821_get_brg_cd(baud); - break; - case 1: - m821.brgc2 = M821_BRG_RST; - m821.brgc2 = m821_get_brg_cd(baud); - break; - case 2: - m821.brgc3 = M821_BRG_RST; - m821.brgc3 = m821_get_brg_cd(baud); - break; - case 3: - m821.brgc4 = M821_BRG_RST; - m821.brgc4 = m821_get_brg_cd(baud); - break; - } - return i; - } - - else - return 0xff; -} - -/* - * Hardware-dependent portion of tcsetattr(). - */ -int -m821_smc_set_attributes (int minor, const struct termios *t) -{ - /* - * minor must be 0 or 1 - */ - int baud; - int brg; - switch (t->c_cflag & CBAUD) { - default: baud = -1; break; - case B50: baud = 50; break; - case B75: baud = 75; break; - case B110: baud = 110; break; - case B134: baud = 134; break; - case B150: baud = 150; break; - case B200: baud = 200; break; - case B300: baud = 300; break; - case B600: baud = 600; break; - case B1200: baud = 1200; break; - case B1800: baud = 1800; break; - case B2400: baud = 2400; break; - case B4800: baud = 4800; break; - case B9600: baud = 9600; break; - case B19200: baud = 19200; break; - case B38400: baud = 38400; break; - case B57600: baud = 57600; break; - case B115200: baud = 115200; break; - case B230400: baud = 230400; break; - case B460800: baud = 460800; break; - } - if (baud > 0) { - brg = m821_get_brg_clk(baud); /* 4 BRGs, 4 serial ports - hopefully */ - /* at least 2 ports will be the same */ - m821.simode |= brg << (12 + ((minor) * 16)); - } - return 0; -} - -int -m821_scc_set_attributes (int minor, const struct termios *t) -{ - /* - * minor must be 2, or 3 - */ - int baud; - int brg; - switch (t->c_cflag & CBAUD) { - default: baud = -1; break; - case B50: baud = 50; break; - case B75: baud = 75; break; - case B110: baud = 110; break; - case B134: baud = 134; break; - case B150: baud = 150; break; - case B200: baud = 200; break; - case B300: baud = 300; break; - case B600: baud = 600; break; - case B1200: baud = 1200; break; - case B1800: baud = 1800; break; - case B2400: baud = 2400; break; - case B4800: baud = 4800; break; - case B9600: baud = 9600; break; - case B19200: baud = 19200; break; - case B38400: baud = 38400; break; - case B57600: baud = 57600; break; - case B115200: baud = 115200; break; - case B230400: baud = 230400; break; - case B460800: baud = 460800; break; - } - if (baud > 0) { - brg = m821_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - m821.sicr |= (brg << (3 + ((minor-2) * 8))) | - (brg << ((minor-2) * 8)); - } - return 0; -} - -void -m821_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ -{ - unsigned char brg; - volatile m821SCCparms_t *sccparms; - volatile m821SCCRegisters_t *sccregs; - - /* - * Allocate buffer descriptors - */ - RxBd[port+1] = M821AllocateBufferDescriptors(1); - TxBd[port+1] = M821AllocateBufferDescriptors(1); - - /* - * Configure ports A and B to enable TXDx and RXDx pins - */ - m821.papar |= (0xC << ((port-2) * 2)); - m821.padir &= ~(0xC << ((port-2) * 2)); - m821.pbdir |= (0x04 << (port-2)); - m821.paodr &= ~(0x8 << ((port-2) * 2)); - m821.pbdat &= ~(0x04 << (port-2)); - - /* SCC2 is the only one with handshaking lines */ - /* - if (port == 2) { - m821.pcpar |= (0x02); - m821.pcpar &= ~(0xc0); - m821.pcdir &= ~(0xc2); - m821.pcso |= (0xc0); - } - */ - - brg = m821_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - - /* - * Set up SDMA - */ - m821.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC821UM/AD */ - - - m821.sicr &= ~(0xff << ((port-1) * 8)); - m821.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); - - /* - * Set up SCC1 parameter RAM common to all protocols - */ - if (port == 1) { - sccparms = (m821SCCparms_t*)&m821.scc1p; - sccregs = &m821.scc1; - } - else if (port == 2) { - sccparms = &m821.scc2p; - sccregs = &m821.scc2; - } - - sccparms->rbase = (char *)RxBd[port+1] - (char *)&m821; - sccparms->tbase = (char *)TxBd[port+1] - (char *)&m821; - - if (port == 1) - M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SCC1); - else if (port == 2) - M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SCC2); - - sccparms->rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); - sccparms->tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); - sccparms->mrblr = RXBUFSIZE; - - sccparms->un.uart.max_idl = 10; - sccparms->un.uart.brklen = 0; - sccparms->un.uart.brkec = 0; - sccparms->un.uart.brkcr = 1; - - sccparms->un.uart.parec = 0; - sccparms->un.uart.frmec = 0; - sccparms->un.uart.nosec = 0; - - sccparms->un.uart.uaddr[0] = 0; - sccparms->un.uart.uaddr[1] = 0; - sccparms->un.uart.toseq = 0; - - sccparms->un.uart.character[0] = 0x8000; - sccparms->un.uart.character[1] = 0x8000; - sccparms->un.uart.character[2] = 0x8000; - sccparms->un.uart.character[3] = 0x8000; - sccparms->un.uart.character[4] = 0x8000; - sccparms->un.uart.character[5] = 0x8000; - sccparms->un.uart.character[6] = 0x8000; - sccparms->un.uart.character[7] = 0x8000; - - sccparms->un.uart.rccm = 0xc0ff; - - /* - * Set up the Receive Buffer Descriptor - */ - RxBd[port+1]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - RxBd[port+1]->length = 0; - RxBd[port+1]->buffer = malloc(RXBUFSIZE); - - /* - * Setup the Transmit Buffer Descriptor - */ - TxBd[port+1]->status = M821_BD_WRAP; - - /* - * Set up SCCx general and protocol-specific mode registers - */ - sccregs->scce = 0xffff; - sccregs->sccm = 0x0000; - sccregs->gsmr_h = 0x00000020; - sccregs->gsmr_l = 0x00028004; - sccregs->psmr = 0x3000; - sccregs->gsmr_l = 0x00028034; -} - -void -m821_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ -{ - unsigned char brg; - - /* - * Allocate buffer descriptors - */ - RxBd[port-1] = M821AllocateBufferDescriptors (1); - TxBd[port-1] = M821AllocateBufferDescriptors (1); - - /* - * Configure port B pins to enable SMTXDx and SMRXDx pins - */ - m821.pbpar |= (0xC0 << ((port-1) * 4)); - m821.pbdir &= ~(0xC0 << ((port-1) * 4)); - m821.pbdir |= (0x01 << (port-1)); - m821.pbodr &= ~(0xC0 << ((port-1) * 4)); - m821.pbdat &= ~(0x01 << (port-1)); - - /* - * Set up BRG1 (9,600 baud) - */ - brg = m821_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - - /* - * Put SMC in NMSI mode, connect SMC to BRG - */ - m860.simode &= ~(0x7000 << ((port-1) * 16)); - m860.simode |= brg << (12 + ((port-1) * 16)); - - /* - * Set up SMC1 parameter RAM common to all protocols - */ - if (port == 1) { - m821.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m821; - m821.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m821; - m821.smc1p.rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); - m821.smc1p.tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); - m821.smc1p.mrblr = RXBUFSIZE; - - /* - * Set up SMC1 parameter RAM UART-specific parameters - */ - m821.smc1p.un.uart.max_idl = 10; - m821.smc1p.un.uart.brklen = 0; - m821.smc1p.un.uart.brkec = 0; - m821.smc1p.un.uart.brkcr = 0; - - } - else { - m821.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m821; - m821.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m821; - m821.smc2p.rfcr = M821_RFCR_MOT | M821_RFCR_DMA_SPACE(0); - m821.smc2p.tfcr = M821_TFCR_MOT | M821_TFCR_DMA_SPACE(0); - m821.smc2p.mrblr = RXBUFSIZE; - - /* - * Set up SMC2 parameter RAM UART-specific parameters - */ - m821.smc2p.un.uart.max_idl = 10; - m821.smc2p.un.uart.brklen = 0; - m821.smc2p.un.uart.brkec = 0; - m821.smc2p.un.uart.brkcr = 0; - } - - /* - * Set up the Receive Buffer Descriptor - */ - RxBd[port-1]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - RxBd[port-1]->length = 0; - RxBd[port-1]->buffer = malloc(RXBUFSIZE); - - /* - * Setup the Transmit Buffer Descriptor - */ - TxBd[port-1]->status = M821_BD_WRAP; - - /* - * Set up SMCx general and protocol-specific mode registers - */ - if (port == 1) { - m821.smc1.smce = ~0; /* Clear any pending events */ - m821.smc1.smcm = 0; /* Mask all interrupt/event sources */ - m821.smc1.smcmr = M821_SMCMR_CLEN(9) | M821_SMCMR_SM_UART; - - /* - * Send "Init parameters" command - */ - M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SMC1); - - /* - * Enable receiver and transmitter - */ - m821.smc1.smcmr |= M821_SMCMR_TEN | M821_SMCMR_REN; - } - else { - m821.smc2.smce = ~0; /* Clear any pending events */ - m821.smc2.smcm = 0; /* Mask all interrupt/event sources */ - m821.smc2.smcmr = M821_SMCMR_CLEN(9) | M821_SMCMR_SM_UART; - - /* - * Send "Init parameters" command - */ - M821ExecuteRISC (M821_CR_OP_INIT_RX_TX | M821_CR_CHAN_SMC2); - - /* - * Enable receiver and transmitter - */ - m821.smc2.smcmr |= M821_SMCMR_TEN | M821_SMCMR_REN; - } -} - -int -m821_char_poll_read (int minor) -{ - unsigned char c; - rtems_unsigned32 level; - - _CPU_ISR_Disable(level); - if (RxBd[minor]->status & M821_BD_EMPTY) { - _CPU_ISR_Enable(level); - return -1; - } - c = ((char *)RxBd[minor]->buffer)[0]; - RxBd[minor]->status = M821_BD_EMPTY | M821_BD_WRAP; - _CPU_ISR_Enable(level); - return c; -} - -int -m821_char_poll_write (int minor, const char *buf, int len) -{ - while (len--) { - while (TxBd[minor]->status & M821_BD_READY) - continue; - txBuf[minor] = *buf++; - TxBd[minor]->buffer = &txBuf[minor]; - TxBd[minor]->length = 1; - TxBd[minor]->status = M821_BD_READY | M821_BD_WRAP; - } - return 0; -} - -/* - * Interrupt handler - */ -rtems_isr -m821_scc1_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m821.scc1.sccm & 0x1) && (m821.scc1.scce & 0x1)) { - m821.scc1.scce = 0x1; - /* m821.scc1.sccm &= ~0x1;*/ - - while ((RxBd[SCC1_MINOR]->status & M821_BD_EMPTY) == 0) { - rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC1_MINOR]->next) { - rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; - rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; - rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; - rxBufListTail[SCC1_MINOR]->pos = 0; - rxBufListTail[SCC1_MINOR]->next = 0; - - RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC1_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m821.smc1.smce & 0x2) { - m821.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m821.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ -} - -rtems_isr -m821_scc2_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m821.scc2.sccm & 0x1) && (m821.scc2.scce & 0x1)) { - m821.scc2.scce = 0x1; - /* m821.scc2.sccm &= ~0x1;*/ - - while ((RxBd[SCC2_MINOR]->status & M821_BD_EMPTY) == 0) { - rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC2_MINOR]->next) { - rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; - rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; - rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; - rxBufListTail[SCC2_MINOR]->pos = 0; - rxBufListTail[SCC2_MINOR]->next = 0; - - RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC2_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m821.smc1.smce & 0x2) { - m821.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m821.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ -} - -rtems_isr -m821_smc1_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if (m821.smc1.smce & 0x1) { - m821.smc1.smce = 0x1; - /* m821.scc2.sccm &= ~0x1;*/ - - while ((RxBd[SMC1_MINOR]->status & M821_BD_EMPTY) == 0) { - rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SMC1_MINOR]->next) { - rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; - rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; - rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; - rxBufListTail[SMC1_MINOR]->pos = 0; - rxBufListTail[SMC1_MINOR]->next = 0; - - RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SMC1_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m821.smc1.smce & 0x2) { - m821.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m821.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ -} - -rtems_isr -m821_smc2_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if (m821.smc2.smce & 0x1) { - m821.smc2.smce = 0x1; - - while ((RxBd[SMC2_MINOR]->status & M821_BD_EMPTY) == 0) { - rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SMC2_MINOR]->next) { - rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; - rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; - rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; - rxBufListTail[SMC2_MINOR]->pos = 0; - rxBufListTail[SMC2_MINOR]->next = 0; - - RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SMC2_MINOR]->status = M821_BD_EMPTY | M821_BD_WRAP | - M821_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m821.smc1.smce & 0x2) { - m821.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m821.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ -} - - -int -m821_buf_poll_read (int minor, char **buf) -{ - int len; - - if (RxBd[minor]->status & M821_BD_EMPTY) - return -1; - - RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ - len = RxBd[minor]->length; - RxBd[minor]->status = M821_BD_EMPTY | M821_BD_WRAP; - - return len; -} - -int -m821_buf_poll_write (int minor, char *buf, int len) -{ - static char *last_buf[6]; - - while (TxBd[minor]->status & M821_BD_READY) - continue; - if (last_buf[minor]) - free(last_buf[minor]); - last_buf[minor] = buf; - TxBd[minor]->buffer = buf; - TxBd[minor]->length = len; - TxBd[minor]->status = M821_BD_READY | M821_BD_WRAP; - return 0; -} - -void m821_console_initialize(void) -{ - int i; - - for (i=0; i < NIFACES; i++) { - rxBufList[i] = malloc(sizeof(Buf_t)); - rxBufListTail[i] = rxBufList[i]; - rxBufList[i]->buf = 0; - rxBufList[i]->len = 0; - rxBufList[i]->pos = 0; - rxBufList[i]->next = 0; - } -} - -rtems_device_driver m821_console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - rtems_libio_rw_args_t *rw_args; - char *buffer; - int maximum; - int count; - Buf_t *tmp_buf; - rtems_unsigned32 level; - - /* - * Set up interrupts - * FIXME: DANGER: WARNING: - * CICR and SIMASK must be set in any module that uses - * the CPM. Currently those are console-generic.c and - * network.c. If the registers are not set the same - * in both places, strange things may happen. - * If they are only set in one place, then an application - * that used the other module won't work correctly. - * Put this comment in each module that sets these 2 registers - */ - m821.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, - SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ - m821.simask |= M821_SIMASK_LVM1; - - rw_args = (rtems_libio_rw_args_t *) arg; - buffer = rw_args->buffer; - maximum = rw_args->count; - count = 0; - - while (count == 0) { - if (rxBufList[minor]->len) { - while ((count < maximum) && - (rxBufList[minor]->pos < rxBufList[minor]->len)) { - buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; - } - _CPU_ISR_Disable(level); - if (rxBufList[minor]->pos == rxBufList[minor]->len) { - if (rxBufList[minor]->next) { - tmp_buf=rxBufList[minor]->next; - free (rxBufList[minor]->buf); - free (rxBufList[minor]); - rxBufList[minor]=tmp_buf; - } - else { - free(rxBufList[minor]->buf); - rxBufList[minor]->buf=0; - rxBufList[minor]->len=0; - rxBufList[minor]->pos=0; - } - } - _CPU_ISR_Enable(level); - } - else - if(rxBufList[minor]->next && !rxBufList[minor]->len) { - tmp_buf = rxBufList[minor]; - rxBufList[minor] = rxBufList[minor]->next; - free(tmp_buf); - } - /* sleep(1);*/ - } - rw_args->bytes_moved = count; - return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; -} - -rtems_device_driver m821_console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - int count; - int maximum; - rtems_libio_rw_args_t *rw_args; - char *in_buffer; - char *out_buffer; - int n; - - /* - * Set up interrupts - * FIXME: DANGER: WARNING: - * CICR and SIMASK must be set in any module that uses - * the CPM. Currently those are console-generic.c and - * network.c. If the registers are not set the same - * in both places, strange things may happen. - * If they are only set in one place, then an application - * that used the other module won't work correctly. - * Put this comment in each module that sets these 2 registers - */ -/* m821.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, - SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ -/* m821.simask |= M821_SIMASK_LVM1; */ - - rw_args = (rtems_libio_rw_args_t *) arg; - - in_buffer = rw_args->buffer; - maximum = rw_args->count; - - out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ - /* be too small */ - - if (!out_buffer) { - rw_args->bytes_moved = 0; - return RTEMS_NO_MEMORY; - } - n=0; - for (count = 0; count < maximum; count++) { - if ( in_buffer[ count ] == '\n') { - out_buffer[count + n] = '\r'; - n++; - } - out_buffer[count + n] = in_buffer[count]; - } - m821_buf_poll_write(minor, out_buffer, maximum+n); - rw_args->bytes_moved = maximum; - return RTEMS_SUCCESSFUL; -} - - -/* - * How to use the console. - * In your BSP, have the following functions: - * - * rtems_device_driver console_initialize(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_open(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_close(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_read(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_write(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_control(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * - */ diff --git a/c/src/lib/libcpu/powerpc/mpc821/include/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/include/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/include/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/include/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/include/Makefile.am deleted file mode 100644 index 8a4dfbd74d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/include/Makefile.am +++ /dev/null @@ -1,21 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -H_FILES = console.h mpc821.h -noinst_HEADERS = $(H_FILES) - -TMPINSTALL_FILES += $(PROJECT_INCLUDE)/mpc821 \ - $(H_FILES:%=$(PROJECT_INCLUDE)/mpc821/%) - -$(PROJECT_INCLUDE)/mpc821: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/mpc821/%.h: %.h - $(INSTALL_DATA) $< $@ - -all-local: $(TMPINSTALL_FILES) - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/include/console.h b/c/src/lib/libcpu/powerpc/mpc821/include/console.h deleted file mode 100644 index 8885abeadc..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/include/console.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * $Id$ - */ - -#ifndef _M821_CONSOLE_H_ -#define _M821_CONSOLE_H_ - -#include <rtems/libio.h> - -int m821_smc_set_attributes(int, const struct termios*); -int m821_scc_set_attributes(int, const struct termios*); -void m821_scc_initialize(int); -void m821_smc_initialize(int); -int m821_char_poll_read(int); -int m821_char_poll_write(int, const char*, int); -rtems_isr m821_scc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m821_scc2_console_interrupt_handler(rtems_vector_number); -rtems_isr m821_smc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m821_smc2_console_interrupt_handler(rtems_vector_number); -int m821_buf_poll_read(int, char**); -int m821_buf_poll_write(int, char*, int); -void m821_console_initialize(void); -rtems_device_driver m821_console_read(rtems_device_major_number, - rtems_device_minor_number, - void*); -rtems_device_driver m821_console_write(rtems_device_major_number, - rtems_device_minor_number, - void*); - - -typedef struct Buf_t_ { - struct Buf_t_ *next; - volatile char *buf; - volatile int len; - int pos; -} Buf_t; - -#define SMC1_MINOR 0 -#define SMC2_MINOR 1 -#define SCC1_MINOR 2 -#define SCC2_MINOR 3 - - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc821/include/mpc821.h b/c/src/lib/libcpu/powerpc/mpc821/include/mpc821.h deleted file mode 100644 index aa8c271f47..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/include/mpc821.h +++ /dev/null @@ -1,1237 +0,0 @@ -/* -************************************************************************** -************************************************************************** -** ** -** MOTOROLA MPC21 PORTABLE SYSTEMS MICROPROCESSOR ** -** ** -** HARDWARE DECLARATIONS ** -** ** -** ** -** Submitted By: ** -** ** -** W. Eric Norum ** -** Saskatchewan Accelerator Laboratory ** -** University of Saskatchewan ** -** 107 North Road ** -** Saskatoon, Saskatchewan, CANADA ** -** S7N 5C6 ** -** ** -** eric@skatter.usask.ca ** -** ** -** Modified for use with the MPC860 (original code was for MC68360) ** -** by ** -** Jay Monkman ** -** Frasca International, Inc. ** -** 906 E. Airport Rd. ** -** Urbana, IL, 61801 ** -** ** -** jmonkman@frasca.com ** -** ** -** Modified further for use with the MPC821 by: ** -** Andrew Bray <andy@chaos.org.uk> ** -** ** -************************************************************************** -************************************************************************** -*/ - -#ifndef __MPC821_h -#define __MPC821_h - -#ifndef ASM -/* - Macros for SPRs -*/ - -#define M821_MI_CTR_GPM (1<<31) -#define M821_MI_CTR_PPM (1<<30) -#define M821_MI_CTR_CIDEF (1<<29) -#define M821_MI_CTR_RSV4I (1<<27) -#define M821_MI_CTR_PPCS (1<<25) - -#define M821_MD_CTR_GPM (1<<31) -#define M821_MD_CTR_PPM (1<<30) -#define M821_MD_CTR_CIDEF (1<<29) -#define M821_MD_CTR_WTDEF (1<<28) -#define M821_MD_CTR_RSV4D (1<<27) -#define M821_MD_CTR_TWAM (1<<26) -#define M821_MD_CTR_PPCS (1<<25) - -#define M821_MI_EPN_VALID (1<<9) - -#define M821_MD_EPN_VALID (1<<9) - -#define M821_MI_TWC_G (1<<4) -#define M821_MI_TWC_PSS (0<<2) -#define M821_MI_TWC_PS512 (1<<2) -#define M821_MI_TWC_PS8 (3<<2) -#define M821_MI_TWC_VALID (1) - -#define M821_MD_TWC_G (1<<4) -#define M821_MD_TWC_PSS (0<<2) -#define M821_MD_TWC_PS512 (1<<2) -#define M821_MD_TWC_PS8 (3<<2) -#define M821_MD_TWC_WT (1<<1) -#define M821_MD_TWC_VALID (1) - -#define M821_MI_RPN_F (0xf<<4) -#define M821_MI_RPN_16K (1<<3) -#define M821_MI_RPN_SHARED (1<<2) -#define M821_MI_RPN_CI (1<<1) -#define M821_MI_RPN_VALID (1) - -#define M821_MD_RPN_CHANGE (1<<8) -#define M821_MD_RPN_F (0xf<<4) -#define M821_MD_RPN_16K (1<<3) -#define M821_MD_RPN_SHARED (1<<2) -#define M821_MD_RPN_CI (1<<1) -#define M821_MD_RPN_VALID (1) - -#define M821_MI_AP_Kp (1) - -#define M821_MD_AP_Kp (1) - -#define M821_CACHE_CMD_SFWT (0x1<<24) -#define M821_CACHE_CMD_ENABLE (0x2<<24) -#define M821_CACHE_CMD_CFWT (0x3<<24) -#define M821_CACHE_CMD_DISABLE (0x4<<24) -#define M821_CACHE_CMD_STLES (0x5<<24) -#define M821_CACHE_CMD_LLCB (0x6<<24) -#define M821_CACHE_CMD_CLES (0x7<<24) -#define M821_CACHE_CMD_UNLOCK (0x8<<24) -#define M821_CACHE_CMD_UNLOCKALL (0xa<<24) -#define M821_CACHE_CMD_INVALIDATE (0xc<<24) -#define M821_CACHE_CMD_FLUSH (0xe<<24) - - - -/* -************************************************************************* -* REGISTER SUBBLOCKS * -************************************************************************* -*/ - -/* - * Memory controller registers - */ -typedef struct m821MEMCRegisters_ { - rtems_unsigned32 br; - rtems_unsigned32 or; -} m821MEMCRegisters_t; - -/* - * Serial Communications Controller registers - */ -typedef struct m821SCCRegisters_ { - rtems_unsigned32 gsmr_l; - rtems_unsigned32 gsmr_h; - rtems_unsigned16 psmr; - rtems_unsigned16 _pad0; - rtems_unsigned16 todr; - rtems_unsigned16 dsr; - rtems_unsigned16 scce; - rtems_unsigned16 _pad1; - rtems_unsigned16 sccm; - rtems_unsigned8 _pad2; - rtems_unsigned8 sccs; - rtems_unsigned32 _pad3[2]; -} m821SCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m821SMCRegisters_ { - rtems_unsigned16 _pad0; - rtems_unsigned16 smcmr; - rtems_unsigned16 _pad1; - rtems_unsigned8 smce; - rtems_unsigned8 _pad2; - rtems_unsigned16 _pad3; - rtems_unsigned8 smcm; - rtems_unsigned8 _pad4; - rtems_unsigned32 _pad5; -} m821SMCRegisters_t; - -/* -************************************************************************* -* Miscellaneous Parameters * -************************************************************************* -*/ -typedef struct m821MiscParms_ { - rtems_unsigned16 rev_num; - rtems_unsigned16 _res1; - rtems_unsigned32 _res2; - rtems_unsigned32 _res3; -} m821MiscParms_t; - -/* -************************************************************************* -* RISC Timers * -************************************************************************* -*/ -typedef struct m821TimerParms_ { - rtems_unsigned16 tm_base; - rtems_unsigned16 _tm_ptr; - rtems_unsigned16 _r_tmr; - rtems_unsigned16 _r_tmv; - rtems_unsigned32 tm_cmd; - rtems_unsigned32 tm_cnt; -} m821TimerParms_t; - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are reserved. - */ -#define M821_RCCR_TIME (1<<15) /* Enable timer */ -#define M821_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ -#define M821_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ -#define M821_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ -#define M821_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ -#define M821_RCCR_EIE (1<<3) /* External Interrupt Enable */ -#define M821_RCCR_SCD (1<<2) /* Scheduler Configuration */ -#define M821_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ - -/* - * Command register - * Set up this register before issuing a M821_CR_OP_SET_TIMER command. - */ -#define M821_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M821_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M821_TM_CMD_PWM (1<<29) /* Set for PWM operation */ -#define M821_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M821_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ - -/* -************************************************************************* -* DMA Controllers * -************************************************************************* -*/ -typedef struct m821IDMAparms_ { - rtems_unsigned16 ibase; - rtems_unsigned16 dcmr; - rtems_unsigned32 _sapr; - rtems_unsigned32 _dapr; - rtems_unsigned16 ibptr; - rtems_unsigned16 _write_sp; - rtems_unsigned32 _s_byte_c; - rtems_unsigned32 _d_byte_c; - rtems_unsigned32 _s_state; - rtems_unsigned32 _itemp[4]; - rtems_unsigned32 _sr_mem; - rtems_unsigned16 _read_sp; - rtems_unsigned16 _res0; - rtems_unsigned16 _res1; - rtems_unsigned16 _res2; - rtems_unsigned32 _d_state; -} m821IDMAparms_t; - - -/* -************************************************************************* -* DSP * -************************************************************************* -*/ -typedef struct m821DSPparms_ { - rtems_unsigned32 fdbase; - rtems_unsigned32 _fd_ptr; - rtems_unsigned32 _dstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _dstatus; - rtems_unsigned16 _i; - rtems_unsigned16 _tap; - rtems_unsigned16 _cbase; - rtems_unsigned16 _pad1; - rtems_unsigned16 _xptr; - rtems_unsigned16 _pad2; - rtems_unsigned16 _yptr; - rtems_unsigned16 _m; - rtems_unsigned16 _pad3; - rtems_unsigned16 _n; - rtems_unsigned16 _pad4; - rtems_unsigned16 _k; - rtems_unsigned16 _pad5; -} m821DSPparms_t; - -/* -************************************************************************* -* Serial Communication Controllers * -************************************************************************* -*/ -typedef struct m821SCCparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - rtems_unsigned32 _rcrc; - rtems_unsigned32 _tcrc; - union { - struct { - rtems_unsigned32 _res0; - rtems_unsigned32 _res1; - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brkcr; - rtems_unsigned16 parec; - rtems_unsigned16 frmec; - rtems_unsigned16 nosec; - rtems_unsigned16 brkec; - rtems_unsigned16 brklen; - rtems_unsigned16 uaddr[2]; - rtems_unsigned16 _rtemp; - rtems_unsigned16 toseq; - rtems_unsigned16 character[8]; - rtems_unsigned16 rccm; - rtems_unsigned16 rccr; - rtems_unsigned16 rlbc; - } uart; - } un; -} m821SCCparms_t; - -typedef struct m821SCCENparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - rtems_unsigned32 _rcrc; - rtems_unsigned32 _tcrc; - union { - struct { - rtems_unsigned32 _res0; - rtems_unsigned32 _res1; - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brkcr; - rtems_unsigned16 parec; - rtems_unsigned16 frmec; - rtems_unsigned16 nosec; - rtems_unsigned16 brkec; - rtems_unsigned16 brklen; - rtems_unsigned16 uaddr[2]; - rtems_unsigned16 _rtemp; - rtems_unsigned16 toseq; - rtems_unsigned16 character[8]; - rtems_unsigned16 rccm; - rtems_unsigned16 rccr; - rtems_unsigned16 rlbc; - } uart; - struct { - rtems_unsigned32 c_pres; - rtems_unsigned32 c_mask; - rtems_unsigned32 crcec; - rtems_unsigned32 alec; - rtems_unsigned32 disfc; - rtems_unsigned16 pads; - rtems_unsigned16 ret_lim; - rtems_unsigned16 _ret_cnt; - rtems_unsigned16 mflr; - rtems_unsigned16 minflr; - rtems_unsigned16 maxd1; - rtems_unsigned16 maxd2; - rtems_unsigned16 _maxd; - rtems_unsigned16 dma_cnt; - rtems_unsigned16 _max_b; - rtems_unsigned16 gaddr1; - rtems_unsigned16 gaddr2; - rtems_unsigned16 gaddr3; - rtems_unsigned16 gaddr4; - rtems_unsigned32 _tbuf0data0; - rtems_unsigned32 _tbuf0data1; - rtems_unsigned32 _tbuf0rba0; - rtems_unsigned32 _tbuf0crc; - rtems_unsigned16 _tbuf0bcnt; - rtems_unsigned16 paddr_h; - rtems_unsigned16 paddr_m; - rtems_unsigned16 paddr_l; - rtems_unsigned16 p_per; - rtems_unsigned16 _rfbd_ptr; - rtems_unsigned16 _tfbd_ptr; - rtems_unsigned16 _tlbd_ptr; - rtems_unsigned32 _tbuf1data0; - rtems_unsigned32 _tbuf1data1; - rtems_unsigned32 _tbuf1rba0; - rtems_unsigned32 _tbuf1crc; - rtems_unsigned16 _tbuf1bcnt; - rtems_unsigned16 _tx_len; - rtems_unsigned16 iaddr1; - rtems_unsigned16 iaddr2; - rtems_unsigned16 iaddr3; - rtems_unsigned16 iaddr4; - rtems_unsigned16 _boff_cnt; - rtems_unsigned16 taddr_l; - rtems_unsigned16 taddr_m; - rtems_unsigned16 taddr_h; - } ethernet; - } un; -} m821SCCENparms_t; - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M821_RFCR_BO(x) ((x)<<3) -#define M821_RFCR_MOT (2<<3) -#define M821_RFCR_DMA_SPACE(x) (x) -#define M821_TFCR_BO(x) ((x)<<3) -#define M821_TFCR_MOT (2<<3) -#define M821_TFCR_DMA_SPACE(x) (x) - -/* -************************************************************************* -* Serial Management Controllers * -************************************************************************* -*/ -typedef struct m821SMCparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - union { - struct { - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brklen; - rtems_unsigned16 brkec; - rtems_unsigned16 brkcr; - rtems_unsigned16 _r_mask; - } uart; - struct { - rtems_unsigned16 _pad0[5]; - } transparent; - } un; -} m821SMCparms_t; - -/* - * Mode register - */ -#define M821_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M821_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M821_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M821_SMCMR_EVEN (1<<8) /* Even parity */ -#define M821_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M821_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M821_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M821_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M821_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M821_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M821_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M821_SMCE_BRKE (1<<6) -#define M821_SMCE_BRK (1<<4) -#define M821_SMCE_BSY (1<<2) -#define M821_SMCE_TX (1<<1) -#define M821_SMCE_RX (1<<0) - -/* -************************************************************************* -* Serial Peripheral Interface * -************************************************************************* -*/ -typedef struct m821SPIparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; -} m821SPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M821_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M821_SPMODE_CI (1<<13) /* Clock invert */ -#define M821_SPMODE_CP (1<<12) /* Clock phase */ -#define M821_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M821_SPMODE_REV (1<<10) /* Reverse data */ -#define M821_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M821_SPMODE_EN (1<<8) /* Enable SPI */ -#define M821_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M821_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M821_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M821_SPIE_MME (1<<5) /* Multi-master error */ -#define M821_SPIE_TXE (1<<4) /* Tx error */ -#define M821_SPIE_BSY (1<<2) /* Busy condition*/ -#define M821_SPIE_TXB (1<<1) /* Tx buffer */ -#define M821_SPIE_RXB (1<<0) /* Rx buffer */ - -/* -************************************************************************* -* SDMA (SCC, SMC, SPI) Buffer Descriptors * -************************************************************************* -*/ -typedef struct m821BufferDescriptor_ { - rtems_unsigned16 status; - rtems_unsigned16 length; - volatile void *buffer; -} m821BufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M821_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M821_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M821_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M821_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M821_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M821_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M821_BD_ADDRESS (1<<10) /* SCC UART */ -#define M821_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M821_BD_MISS (1<<8) /* Ethernet */ -#define M821_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M821_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M821_BD_LONG (1<<5) /* Ethernet */ -#define M821_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M821_BD_NONALIGNED (1<<4) /* Ethernet */ -#define M821_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M821_BD_SHORT (1<<3) /* Ethernet */ -#define M821_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M821_BD_CRC_ERROR (1<<2) /* Ethernet */ -#define M821_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M821_BD_COLLISION (1<<0) /* Ethernet */ -#define M821_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ -#define M821_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M821_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M821_BD_PAD (1<<14) /* Ethernet */ -#define M821_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M821_BD_TX_CRC (1<<10) /* Ethernet */ -#define M821_BD_DEFER (1<<9) /* Ethernet */ -#define M821_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M821_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M821_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M821_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M821_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M821_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M821_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ -#define M821_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M821_BD_CTS_LOST (1<<0) /* SCC UART */ - -/* -************************************************************************* -* IDMA Buffer Descriptors * -************************************************************************* -*/ -typedef struct m821IDMABufferDescriptor_ { - rtems_unsigned16 status; - rtems_unsigned8 dfcr; - rtems_unsigned8 sfcr; - rtems_unsigned32 length; - void *source; - void *destination; -} m821IDMABufferDescriptor_t; - -/* -************************************************************************* -* RISC Communication Processor Module Command Register (CR) * -************************************************************************* -*/ -#define M821_CR_RST (1<<15) /* Reset communication processor */ -#define M821_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ -#define M821_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ -#define M821_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ -#define M821_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ -#define M821_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ -#define M821_CR_OP_GR_STOP_TX (5<<8) /* SCC */ -#define M821_CR_OP_INIT_IDMA (5<<8) /* IDMA */ -#define M821_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ -#define M821_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ -#define M821_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ -#define M821_CR_OP_SET_TIMER (8<<8) /* Timer */ -#define M821_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ -#define M821_CR_OP_RESERT_BCS (10<<8) /* SCC */ -#define M821_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ -#define M821_CR_OP_STOP_IDMA (11<<8) /* IDMA */ -#define M821_CR_OP_START_DSP (12<<8) /* DSP */ -#define M821_CR_OP_INIT_DSP (13<<8) /* DSP */ - -#define M821_CR_CHAN_SCC1 (0<<4) /* Channel selection */ -#define M821_CR_CHAN_I2C (1<<4) -#define M821_CR_CHAN_IDMA1 (1<<4) -#define M821_CR_CHAN_SCC2 (4<<4) -#define M821_CR_CHAN_SPI (5<<4) -#define M821_CR_CHAN_IDMA2 (5<<4) -#define M821_CR_CHAN_TIMER (5<<4) -#define M821_CR_CHAN_SCC3 (8<<4) -#define M821_CR_CHAN_SMC1 (9<<4) -#define M821_CR_CHAN_DSP1 (9<<4) -#define M821_CR_CHAN_SCC4 (12<<4) -#define M821_CR_CHAN_SMC2 (13<<4) -#define M821_CR_CHAN_DSP2 (13<<4) -#define M821_CR_FLG (1<<0) /* Command flag */ - -/* -************************************************************************* -* System Protection Control Register (SYPCR) * -************************************************************************* -*/ -#define M821_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ -#define M821_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define M821_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define M821_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define M821_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define M821_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define M821_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* -************************************************************************* -* Memory Control Registers * -************************************************************************* -*/ -#define M821_UPM_AMX_8col (0<<20) /* 8 column DRAM */ -#define M821_UPM_AMX_9col (1<<20) /* 9 column DRAM */ -#define M821_UPM_AMX_10col (2<<20) /* 10 column DRAM */ -#define M821_UPM_AMX_11col (3<<20) /* 11 column DRAM */ -#define M821_UPM_AMX_12col (4<<20) /* 12 column DRAM */ -#define M821_UPM_AMX_13col (5<<20) /* 13 column DRAM */ -#define M821_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ -#define M821_MSR_WPER (1<<7) /* Write protection error */ -#define M821_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ -#define M821_BR_BA(x) ((x)&0xffff8000) /* Base address */ -#define M821_BR_AT(x) ((x)<<12) /* Address type */ -#define M821_BR_PS8 (1<<10) /* 8 bit port */ -#define M821_BR_PS16 (2<<10) /* 16 bit port */ -#define M821_BR_PS32 (0<<10) /* 32 bit port */ -#define M821_BR_PARE (1<<9) /* Parity checking enable */ -#define M821_BR_WP (1<<8) /* Write protect */ -#define M821_BR_MS_GPCM (0<<6) /* GPCM */ -#define M821_BR_MS_UPMA (2<<6) /* UPM A */ -#define M821_BR_MS_UPMB (3<<6) /* UPM B */ -#define M821_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M821_MEMC_OR_32K 0xffff8000 /* Address range */ -#define M821_MEMC_OR_64K 0xffff0000 -#define M821_MEMC_OR_128K 0xfffe0000 -#define M821_MEMC_OR_256K 0xfffc0000 -#define M821_MEMC_OR_512K 0xfff80000 -#define M821_MEMC_OR_1M 0xfff00000 -#define M821_MEMC_OR_2M 0xffe00000 -#define M821_MEMC_OR_4M 0xffc00000 -#define M821_MEMC_OR_8M 0xff800000 -#define M821_MEMC_OR_16M 0xff000000 -#define M821_MEMC_OR_32M 0xfe000000 -#define M821_MEMC_OR_64M 0xfc000000 -#define M821_MEMC_OR_128 0xf8000000 -#define M821_MEMC_OR_256M 0xf0000000 -#define M821_MEMC_OR_512M 0xe0000000 -#define M821_MEMC_OR_1G 0xc0000000 -#define M821_MEMC_OR_2G 0x80000000 -#define M821_MEMC_OR_4G 0x00000000 -#define M821_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ -#define M821_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ -#define M821_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ -#define M821_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ -#define M821_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ -#define M821_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ -#define M821_MEMC_OR_BI (1<8) /* Burst inhibit */ -#define M821_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ -#define M821_MEMC_OR_SETA (1<<3) /* *TA generated externally */ -#define M821_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ -#define M821_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ - -/* -************************************************************************* -* UPM Registers (MxMR) * -************************************************************************* -*/ -#define M821_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ -#define M821_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ -#define M821_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ -#define M821_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ -#define M821_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ -#define M821_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ -#define M821_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ -#define M821_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ -/* -************************************************************************* -* Memory Command Register (MCR) * -************************************************************************* -*/ -#define M821_MEMC_MCR_WRITE (0<<30) /* WRITE command */ -#define M821_MEMC_MCR_READ (1<<30) /* READ command */ -#define M821_MEMC_MCR_RUN (2<<30) /* RUN command */ -#define M821_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ -#define M821_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ -#define M821_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ -#define M821_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ -#define M821_MEMC_MCR_MAD(x) (x) /* Machine address */ - - - -/* -************************************************************************* -* SI Mode Register (SIMODE) * -************************************************************************* -*/ -#define M821_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M821_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M821_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M821_SI_SMC2_BRG2 (1<<28) -#define M821_SI_SMC2_BRG3 (2<<28) -#define M821_SI_SMC2_BRG4 (3<<28) -#define M821_SI_SMC2_CLK5 (0<<28) -#define M821_SI_SMC2_CLK6 (1<<28) -#define M821_SI_SMC2_CLK7 (2<<28) -#define M821_SI_SMC2_CLK8 (3<<28) -#define M821_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M821_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M821_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M821_SI_SMC1_BRG2 (1<<12) -#define M821_SI_SMC1_BRG3 (2<<12) -#define M821_SI_SMC1_BRG4 (3<<12) -#define M821_SI_SMC1_CLK1 (0<<12) -#define M821_SI_SMC1_CLK2 (1<<12) -#define M821_SI_SMC1_CLK3 (2<<12) -#define M821_SI_SMC1_CLK4 (3<<12) - -/* -************************************************************************* -* SDMA Configuration Register (SDCR) * -************************************************************************* -*/ -#define M821_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M821_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ - -/* -************************************************************************* -* SDMA Status Register (SDSR) * -************************************************************************* -*/ -#define M821_SDSR_SBER (1<<7) /* SDMA Channel bus error */ -#define M821_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ -#define M821_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ - -/* -************************************************************************* -* Baud (sic) Rate Generators * -************************************************************************* -*/ -#define M821_BRG_RST (1<<17) /* Reset generator */ -#define M821_BRG_EN (1<<16) /* Enable generator */ -#define M821_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M821_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M821_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M821_BRG_ATB (1<<13) /* Autobaud */ -#define M821_BRG_115200 (21<<1) /* Assume 40 MHz clock */ -#define M821_BRG_57600 (32<<1) -#define M821_BRG_38400 (64<<1) -#define M821_BRG_19200 (129<<1) -#define M821_BRG_9600 (259<<1) -#define M821_BRG_4800 (520<<1) -#define M821_BRG_2400 (1040<<1) -#define M821_BRG_1200 (2082<<1) -#define M821_BRG_600 ((259<<1) | 1) -#define M821_BRG_300 ((520<<1) | 1) -#define M821_BRG_150 ((1040<<1) | 1) -#define M821_BRG_75 ((2080<<1) | 1) - -#define M821_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ -#define M821_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ -#define M821_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ -#define M821_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ -#define M821_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ -#define M821_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ -#define M821_TGCR_STP1 (1<<1) /* Stop timer */ -#define M821_TGCR_STP2 (1<<5) /* Stop timer */ -#define M821_TGCR_STP3 (1<<9) /* Stop timer */ -#define M821_TGCR_STP4 (1<<13) /* Stop timer */ -#define M821_TGCR_RST1 (1<<0) /* Enable timer */ -#define M821_TGCR_RST2 (1<<4) /* Enable timer */ -#define M821_TGCR_RST3 (1<<8) /* Enable timer */ -#define M821_TGCR_RST4 (1<<12) /* Enable timer */ -#define M821_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ -#define M821_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ - -#define M821_TMR_PS(x) ((x)<<8) /* Timer prescaler */ -#define M821_TMR_CE_RISE (1<<6) /* Capture on rising edge */ -#define M821_TMR_CE_FALL (2<<6) /* Capture on falling edge */ -#define M821_TMR_CE_ANY (3<<6) /* Capture on any edge */ -#define M821_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ -#define M821_TMR_ORI (1<<4) /* Interrupt on reaching reference */ -#define M821_TMR_RESTART (1<<3) /* Restart timer after reference */ -#define M821_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ -#define M821_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ -#define M821_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ -#define M821_TMR_TGATE (1<<0) /* TGATE controls timer */ - -#define M821_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ -#define M821_PISCR_PS (1<<7) /* PIT Interrupt state */ -#define M821_PISCR_PIE (1<<2) /* PIT interrupt enable */ -#define M821_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ -#define M821_PISCR_PTE (1<<0) /* PIT enable */ - -#define M821_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ -#define M821_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ -#define M821_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ -#define M821_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ -#define M821_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ -#define M821_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ -#define M821_TBSCR_TBE (1<<0) /* enable TB and decrementer */ - -#define M821_SIMASK_IRM0 (1<<31) -#define M821_SIMASK_LVM0 (1<<30) -#define M821_SIMASK_IRM1 (1<<29) -#define M821_SIMASK_LVM1 (1<<28) -#define M821_SIMASK_IRM2 (1<<27) -#define M821_SIMASK_LVM2 (1<<26) -#define M821_SIMASK_IRM3 (1<<25) -#define M821_SIMASK_LVM3 (1<<24) -#define M821_SIMASK_IRM4 (1<<23) -#define M821_SIMASK_LVM4 (1<<22) -#define M821_SIMASK_IRM5 (1<<21) -#define M821_SIMASK_LVM5 (1<<20) -#define M821_SIMASK_IRM6 (1<<19) -#define M821_SIMASK_LVM6 (1<<18) -#define M821_SIMASK_IRM7 (1<<17) -#define M821_SIMASK_LVM7 (1<<16) - -#define M821_SIUMCR_EARB (1<<31) -#define M821_SIUMCR_EARP0 (0<<28) -#define M821_SIUMCR_EARP1 (1<<28) -#define M821_SIUMCR_EARP2 (2<<28) -#define M821_SIUMCR_EARP3 (3<<28) -#define M821_SIUMCR_EARP4 (4<<28) -#define M821_SIUMCR_EARP5 (5<<28) -#define M821_SIUMCR_EARP6 (6<<28) -#define M821_SIUMCR_EARP7 (7<<28) -#define M821_SIUMCR_DSHW (1<<23) -#define M821_SIUMCR_DBGC0 (0<<21) -#define M821_SIUMCR_DBGC1 (1<<21) -#define M821_SIUMCR_DBGC2 (2<<21) -#define M821_SIUMCR_DBGC3 (3<<21) -#define M821_SIUMCR_DBPC0 (0<<19) -#define M821_SIUMCR_DBPC1 (1<<19) -#define M821_SIUMCR_DBPC2 (2<<19) -#define M821_SIUMCR_DBPC3 (3<<19) -#define M821_SIUMCR_FRC (1<<17) -#define M821_SIUMCR_DLK (1<<16) -#define M821_SIUMCR_PNCS (1<<15) -#define M821_SIUMCR_OPAR (1<<14) -#define M821_SIUMCR_DPC (1<<13) -#define M821_SIUMCR_MPRE (1<<12) -#define M821_SIUMCR_MLRC0 (0<<10) -#define M821_SIUMCR_MLRC1 (1<<10) -#define M821_SIUMCR_MLRC2 (2<<10) -#define M821_SIUMCR_MLRC3 (3<<10) -#define M821_SIUMCR_AEME (1<<9) -#define M821_SIUMCR_SEME (1<<8) -#define M821_SIUMCR_BSC (1<<7) -#define M821_SIUMCR_GB5E (1<<6) -#define M821_SIUMCR_B2DD (1<<5) -#define M821_SIUMCR_B3DD (1<<4) -/* -************************************************************************* -* MPC821 DUAL-PORT RAM AND REGISTERS * -************************************************************************* -*/ -typedef struct m821_ { - - /* - * SIU Block - */ - rtems_unsigned32 siumcr; - rtems_unsigned32 sypcr; - rtems_unsigned32 _pad70; - rtems_unsigned16 _pad0; - rtems_unsigned16 swsr; - rtems_unsigned32 sipend; - rtems_unsigned32 simask; - rtems_unsigned32 siel; - rtems_unsigned32 sivec; - rtems_unsigned32 tesr; - rtems_unsigned32 _pad1[3]; - rtems_unsigned32 sdcr; - rtems_unsigned8 _pad2[0x80-0x34]; - - /* - * PCMCIA Block - */ - rtems_unsigned32 pbr0; - rtems_unsigned32 por0; - rtems_unsigned32 pbr1; - rtems_unsigned32 por1; - rtems_unsigned32 pbr2; - rtems_unsigned32 por2; - rtems_unsigned32 pbr3; - rtems_unsigned32 por3; - rtems_unsigned32 pbr4; - rtems_unsigned32 por4; - rtems_unsigned32 pbr5; - rtems_unsigned32 por5; - rtems_unsigned32 pbr6; - rtems_unsigned32 por6; - rtems_unsigned32 pbr7; - rtems_unsigned32 por7; - rtems_unsigned8 _pad3[0xe0-0xc0]; - rtems_unsigned32 pgcra; - rtems_unsigned32 pgcrb; - rtems_unsigned32 pscr; - rtems_unsigned32 _pad4; - rtems_unsigned32 pipr; - rtems_unsigned32 _pad5; - rtems_unsigned32 per; - rtems_unsigned32 _pad6; - - /* - * MEMC Block - */ - m821MEMCRegisters_t memc[8]; - rtems_unsigned8 _pad7[0x164-0x140]; - rtems_unsigned32 mar; - rtems_unsigned32 mcr; - rtems_unsigned32 _pad8; - rtems_unsigned32 mamr; - rtems_unsigned32 mbmr; - rtems_unsigned16 mstat; - rtems_unsigned16 mptpr; - rtems_unsigned32 mdr; - rtems_unsigned8 _pad9[0x200-0x180]; - - /* - * System integration timers - */ - rtems_unsigned16 tbscr; - rtems_unsigned16 _pad10; - rtems_unsigned32 tbreff0; - rtems_unsigned32 tbreff1; - rtems_unsigned8 _pad11[0x220-0x20c]; - rtems_unsigned16 rtcsc; - rtems_unsigned16 _pad12; - rtems_unsigned32 rtc; - rtems_unsigned32 rtsec; - rtems_unsigned32 rtcal; - rtems_unsigned32 _pad13[4]; - rtems_unsigned16 piscr; - rtems_unsigned16 _pad14; - rtems_unsigned16 pitc; - rtems_unsigned16 _pad_14_1; - rtems_unsigned16 pitr; - rtems_unsigned16 _pad_14_2; - rtems_unsigned8 _pad15[0x280-0x24c]; - - - /* - * Clocks and Reset - */ - rtems_unsigned32 sccr; - rtems_unsigned32 plprcr; - rtems_unsigned32 rsr; - rtems_unsigned8 _pad16[0x300-0x28c]; - - - /* - * System integration timers keys - */ - rtems_unsigned32 tbscrk; - rtems_unsigned32 tbreff0k; - rtems_unsigned32 tbreff1k; - rtems_unsigned32 tbk; - rtems_unsigned32 _pad17[4]; - rtems_unsigned32 rtcsk; - rtems_unsigned32 rtck; - rtems_unsigned32 rtseck; - rtems_unsigned32 rtcalk; - rtems_unsigned32 _pad18[4]; - rtems_unsigned32 piscrk; - rtems_unsigned32 pitck; - rtems_unsigned8 _pad19[0x380-0x348]; - - /* - * Clocks and Reset Keys - */ - rtems_unsigned32 sccrk; - rtems_unsigned32 plprck; - rtems_unsigned32 rsrk; - rtems_unsigned8 _pad20[0x400-0x38c]; - rtems_unsigned8 _pad21[0x800-0x400]; - rtems_unsigned8 _pad22[0x860-0x800]; - - - /* - * I2C - */ - rtems_unsigned8 i2mod; - rtems_unsigned8 _pad23[3]; - rtems_unsigned8 i2add; - rtems_unsigned8 _pad24[3]; - rtems_unsigned8 i2brg; - rtems_unsigned8 _pad25[3]; - rtems_unsigned8 i2com; - rtems_unsigned8 _pad26[3]; - rtems_unsigned8 i2cer; - rtems_unsigned8 _pad27[3]; - rtems_unsigned8 i2cmr; - rtems_unsigned8 _pad28[0x900-0x875]; - - /* - * DMA Block - */ - rtems_unsigned32 _pad29; - rtems_unsigned32 sdar; - rtems_unsigned8 sdsr; - rtems_unsigned8 _pad30[3]; - rtems_unsigned8 sdmr; - rtems_unsigned8 _pad31[3]; - rtems_unsigned8 idsr1; - rtems_unsigned8 _pad32[3]; - rtems_unsigned8 idmr1; - rtems_unsigned8 _pad33[3]; - rtems_unsigned8 idsr2; - rtems_unsigned8 _pad34[3]; - rtems_unsigned8 idmr2; - rtems_unsigned8 _pad35[0x930-0x91d]; - - - - /* - * CPM Interrupt Control Block - */ - rtems_unsigned16 civr; - rtems_unsigned8 _pad36[14]; - rtems_unsigned32 cicr; - rtems_unsigned32 cipr; - rtems_unsigned32 cimr; - rtems_unsigned32 cisr; - - /* - * I/O Port Block - */ - rtems_unsigned16 padir; - rtems_unsigned16 papar; - rtems_unsigned16 paodr; - rtems_unsigned16 padat; - rtems_unsigned8 _pad37[8]; - rtems_unsigned16 pcdir; - rtems_unsigned16 pcpar; - rtems_unsigned16 pcso; - rtems_unsigned16 pcdat; - rtems_unsigned16 pcint; - rtems_unsigned8 _pad39[6]; - rtems_unsigned16 pddir; - rtems_unsigned16 pdpar; - rtems_unsigned16 _pad40; - rtems_unsigned16 pddat; - rtems_unsigned8 _pad41[8]; - - /* - * CPM Timers Block - */ - rtems_unsigned16 tgcr; - rtems_unsigned8 _pad42[14]; - rtems_unsigned16 tmr1; - rtems_unsigned16 tmr2; - rtems_unsigned16 trr1; - rtems_unsigned16 trr2; - rtems_unsigned16 tcr1; - rtems_unsigned16 tcr2; - rtems_unsigned16 tcn1; - rtems_unsigned16 tcn2; - rtems_unsigned16 tmr3; - rtems_unsigned16 tmr4; - rtems_unsigned16 trr3; - rtems_unsigned16 trr4; - rtems_unsigned16 tcr3; - rtems_unsigned16 tcr4; - rtems_unsigned16 tcn3; - rtems_unsigned16 tcn4; - rtems_unsigned16 ter1; - rtems_unsigned16 ter2; - rtems_unsigned16 ter3; - rtems_unsigned16 ter4; - rtems_unsigned8 _pad43[8]; - - - - /* - * CPM Block - */ - rtems_unsigned16 cpcr; - rtems_unsigned16 _pad44; - rtems_unsigned16 rccr; - rtems_unsigned8 _pad45; - rtems_unsigned8 rmds; - rtems_unsigned32 rmdr; - rtems_unsigned16 rctr1; - rtems_unsigned16 rctr2; - rtems_unsigned16 rctr3; - rtems_unsigned16 rctr4; - rtems_unsigned16 _pad46; - rtems_unsigned16 rter; - rtems_unsigned16 _pad47; - rtems_unsigned16 rtmr; - rtems_unsigned8 _pad48[0x9f0-0x9dc]; - - /* - * BRG Block - */ - rtems_unsigned32 brgc1; - rtems_unsigned32 brgc2; - rtems_unsigned32 brgc3; - rtems_unsigned32 brgc4; - - /* - * SCC Block - */ - m821SCCRegisters_t scc1; - m821SCCRegisters_t scc2; - rtems_unsigned8 _pad72[0xa80-0xa40]; - - /* - * SMC Block - */ - m821SMCRegisters_t smc1; - m821SMCRegisters_t smc2; - - /* - * SPI Block - */ - rtems_unsigned16 spmode; - rtems_unsigned16 _pad49[2]; - rtems_unsigned8 spie; - rtems_unsigned8 _pad50; - rtems_unsigned16 _pad51; - rtems_unsigned8 spim; - rtems_unsigned8 _pad52[2]; - rtems_unsigned8 spcom; - rtems_unsigned16 _pad53[2]; - - /* - * PIP Block - */ - rtems_unsigned16 pipc; - rtems_unsigned16 _pad54; - rtems_unsigned16 ptpr; - rtems_unsigned32 pbdir; - rtems_unsigned32 pbpar; - rtems_unsigned16 _pad55; - rtems_unsigned16 pbodr; - rtems_unsigned32 pbdat; - rtems_unsigned32 _pad56[6]; - - /* - * SI Block - */ - rtems_unsigned32 simode; - rtems_unsigned8 sigmr; - rtems_unsigned8 _pad57; - rtems_unsigned8 sistr; - rtems_unsigned8 sicmr; - rtems_unsigned32 _pad58; - rtems_unsigned32 sicr; - rtems_unsigned16 sirp[2]; - rtems_unsigned32 _pad59[3]; - rtems_unsigned8 _pad60[0xc00-0xb00]; - rtems_unsigned8 siram[512]; - rtems_unsigned8 lcdram[512]; - - rtems_unsigned8 _pad62[0x2000-0x1000]; - /* - * Dual-port RAM - */ - rtems_unsigned8 dpram0[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram1[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram2[0x400]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram3[0x600]; /* BD/DATA*/ - rtems_unsigned8 dpram4[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 _pad63[0x3c00-0x3000]; - - /* When using SCC1 for ethernet, we lose the use of I2C since - * their parameters would overlap. Motorola has a microcode - * patch to move parameters around so that both can be used - * together. It is available on their web site somewhere - * under http://www.mot.com/mpc821. If ethernet is used on - * one (or more) of the other SCCs, then other CPM features - * will be unavailable: - * SCC2 -> lose SPI - * However, Ethernet only works on SCC1 on the 821. - */ - m821SCCENparms_t scc1p; - rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m821SCCENparms_t)]; - m821MiscParms_t miscp; - rtems_unsigned8 _rsv2[0xcc0-0xCB0-sizeof(m821MiscParms_t)]; - m821IDMAparms_t idma1p; - rtems_unsigned8 _rsv3[0xd00-0xcc0-sizeof(m821IDMAparms_t)]; - - m821SCCparms_t scc2p; - rtems_unsigned8 _rsv4[0xD80-0xD00-sizeof(m821SCCparms_t)]; - m821SPIparms_t spip; - rtems_unsigned8 _rsv5[0xDB0-0xD80-sizeof(m821SPIparms_t)]; - m821TimerParms_t tmp; - rtems_unsigned8 _rsv6[0xDC0-0xDB0-sizeof(m821TimerParms_t)]; - m821IDMAparms_t idma2p; - rtems_unsigned8 _rsv7[0xE00-0xDC0-sizeof(m821IDMAparms_t)]; - - m821SCCparms_t scc3p; /* Not used */ - rtems_unsigned8 _rsv8[0xE80-0xE00-sizeof(m821SCCparms_t)]; - m821SMCparms_t smc1p; - rtems_unsigned8 _rsv9[0xEC0-0xE80-sizeof(m821SMCparms_t)]; - m821DSPparms_t dsp1p; - rtems_unsigned8 _rsv10[0xF00-0xEC0-sizeof(m821DSPparms_t)]; - - m821SCCparms_t scc4p; /* Not used */ - rtems_unsigned8 _rsv11[0xF80-0xF00-sizeof(m821SCCparms_t)]; - m821SMCparms_t smc2p; - rtems_unsigned8 _rsv12[0xFC0-0xF80-sizeof(m821SMCparms_t)]; - m821DSPparms_t dsp2p; - rtems_unsigned8 _rsv13[0x1000-0xFC0-sizeof(m821DSPparms_t)]; -} m821_t; - -extern volatile m821_t m821; -#endif /* ASM */ - -#endif /* __MPC821_h */ diff --git a/c/src/lib/libcpu/powerpc/mpc821/timer/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/timer/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/timer/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/timer/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/timer/Makefile.am deleted file mode 100644 index 65edc98d9f..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/timer/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/timer.rel - -C_FILES = timer.c - -timer_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(timer_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(timer_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = timer.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc821/timer/timer.c deleted file mode 100644 index eefadb9079..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/timer/timer.c +++ /dev/null @@ -1,100 +0,0 @@ -/* timer.c - * - * This file manages the interval timer on the PowerPC MPC821. - * NOTE: This is not the PIT, but rather the RTEMS interval - * timer - * We shall use the bottom 32 bits of the timebase register, - * - * The following was in the 403 version of this file. I don't - * know what it means. JTM 5/19/98 - * NOTE: It is important that the timer start/stop overhead be - * determined when porting or modifying this code. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * Copywright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/timer/timer.c: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libcpu/hppa1_1/timer/timer.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <mpc821.h> - -static volatile rtems_unsigned32 Timer_starting; -static rtems_boolean Timer_driver_Find_average_overhead; - -/* - * This is so small that this code will be reproduced where needed. - */ -static inline rtems_unsigned32 get_itimer(void) -{ - rtems_unsigned32 ret; - - asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */ - - return ret; -} - -void Timer_initialize(void) -{ - /* set interrupt level and enable timebase. This should never */ - /* generate an interrupt however. */ - m821.tbscr |= M821_TBSCR_TBIRQ(4) | M821_TBSCR_TBE; - - Timer_starting = get_itimer(); -} - -int Read_timer(void) -{ - rtems_unsigned32 clicks; - rtems_unsigned32 total; - - clicks = get_itimer(); - - total = clicks - Timer_starting; - - if ( Timer_driver_Find_average_overhead == 1 ) - return total; /* in XXX microsecond units */ - - else { - if ( total < rtems_cpu_configuration_get_timer_least_valid() ) { - return 0; /* below timer resolution */ - } - return (total - rtems_cpu_configuration_get_timer_average_overhead()); - } -} - -rtems_status_code Empty_function(void) -{ - return RTEMS_SUCCESSFUL; -} - -void Set_find_average_overhead(rtems_boolean find_flag) -{ - Timer_driver_Find_average_overhead = find_flag; -} diff --git a/c/src/lib/libcpu/powerpc/mpc821/vectors/.cvsignore b/c/src/lib/libcpu/powerpc/mpc821/vectors/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/vectors/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc821/vectors/Makefile.am b/c/src/lib/libcpu/powerpc/mpc821/vectors/Makefile.am deleted file mode 100644 index 8d8bce2c1d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/vectors/Makefile.am +++ /dev/null @@ -1,32 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -VPATH = @srcdir@:@srcdir@/../../ppc403/vectors - -## FIXME - -PGM = ${ARCH}/vectors.rel - -## Assembly sources -S_FILES = vectors.S align_h.S - -vectors_rel_OBJECTS = $(S_FILES:%.S=${ARCH}/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(vectors_rel_OBJECTS) - $(make-rel) - -all-local: ${ARCH} $(PGM) - -EXTRA_DIST = vectors.S README - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc821/vectors/README b/c/src/lib/libcpu/powerpc/mpc821/vectors/README deleted file mode 100644 index 536e221f43..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/vectors/README +++ /dev/null @@ -1,20 +0,0 @@ -# -# $Id$ -# - -The location of the vectors file object is critical. - -From the comments at the head of vectors.s: - - The issue with this file is getting it loaded at the right place. - The first vector MUST be at address 0x????0100. - How this is achieved is dependant on the tool chain. - -... - - The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - offset from 0x????0000 to the first location in the file. This - will be either 0x0000 or 0xfff0. - -The eth_comm BSP defines PPC_VECTOR_FILE_BASE to be 0x00000000 - diff --git a/c/src/lib/libcpu/powerpc/mpc821/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc821/vectors/vectors.S deleted file mode 100644 index 9b6acc56ee..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc821/vectors/vectors.S +++ /dev/null @@ -1,952 +0,0 @@ -/* vectors.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC MPC821 - * interrupt veneers for RTEMS. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - */ - -/* - * The issue with this file is getting it loaded at the right place. - * The first vector MUST be at address 0x????0100. - * How this is achieved is dependant on the tool chain. - * - * However the basic mechanism for ELF assemblers is to create a - * section called ".vectors", which will be loaded to an address - * between 0x????0000 and 0x????0100 (inclusive) via a link script. - * - * The basic mechanism for XCOFF assemblers is to place it in the - * normal text section, and arrange for this file to be located - * at an appropriate position on the linker command line. - * - * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - * offset from 0x????0000 to the first location in the file. This - * will be either 0x0000 or 0xfff0. - * - * $Id$ - */ - -#include "asm.h" -#include <mpc821.h> - -#ifndef PPC_VECTOR_FILE_BASE -#error "PPC_VECTOR_FILE_BASE is not defined." -#endif - - /* Where this file will be loaded */ - .set file_base, PPC_VECTOR_FILE_BASE - - /* Offset to store reg 0 */ - - .set IP_LINK, 0 -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - .set IP_0, (IP_LINK + 56) -#else - .set IP_0, (IP_LINK + 8) -#endif - .set IP_2, (IP_0 + 4) - - .set IP_3, (IP_2 + 4) - .set IP_4, (IP_3 + 4) - .set IP_5, (IP_4 + 4) - .set IP_6, (IP_5 + 4) - - .set IP_7, (IP_6 + 4) - .set IP_8, (IP_7 + 4) - .set IP_9, (IP_8 + 4) - .set IP_10, (IP_9 + 4) - - .set IP_11, (IP_10 + 4) - .set IP_12, (IP_11 + 4) - .set IP_13, (IP_12 + 4) - .set IP_28, (IP_13 + 4) - - .set IP_29, (IP_28 + 4) - .set IP_30, (IP_29 + 4) - .set IP_31, (IP_30 + 4) - .set IP_CR, (IP_31 + 4) - - .set IP_CTR, (IP_CR + 4) - .set IP_XER, (IP_CTR + 4) - .set IP_LR, (IP_XER + 4) - .set IP_PC, (IP_LR + 4) - - .set IP_MSR, (IP_PC + 4) - - .set IP_END, (IP_MSR + 16) - - /* Vector offsets */ - .set begin_vector, 0x0000 - .set reset_vector, 0x0100 - .set mach_vector, 0x0200 - .set dsi_vector, 0x0300 - .set isi_vector, 0x0400 - .set ext_vector, 0x0500 - .set align_vector, 0x0600 - .set prog_vector, 0x0700 - .set float_vector, 0x0800 - .set dec_vector, 0x0900 - .set sys_vector, 0x0C00 - .set trace_vector, 0x0d00 - .set syscall_vector, 0x0c00 - .set fpassist_vector, 0x0e00 - .set software_vector, 0x1000 - .set itlbm_vector, 0x1100 - .set dtlbm_vector, 0x1200 - .set itlbe_vector, 0x1300 - .set dtlbe_vector, 0x1400 - .set databkpt_vector, 0x1c00 - .set insbkpt_vector, 0x1d00 - .set perbkpt_vector, 0x1e00 - .set dev_vector, 0x1f00 - .set siu_vector, 0x2000 - .set cpm_vector, 0x2400 - -/* Go to the right section */ -#if PPC_ASM == PPC_ASM_ELF - .section .vectors,"awx",@progbits -#elif PPC_ASM == PPC_ASM_XCOFF - .csect .text[PR] -#endif - - PUBLIC_VAR (__vectors) -SYM (__vectors): - -/* Critical error handling */ - .org reset_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_SYSTEM_RESET - b PROC (_ISR_Handler) - -/* Machine check exception */ - .org mach_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_MCHECK - b PROC (_ISR_Handler) - -/* Protection exception */ - .org dsi_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROTECT - b PROC (_ISR_Handler) - -/* Instruction Storage exception */ - .org isi_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_ISI - b PROC (_ISR_Handler) - -/* External interrupt */ -/* When an external interrupt occurs, we must find out what caused it */ -/* before calling the RTEMS handler. First we use SIVEC to decide */ -/* what signalled the interrupt to the SIU. */ - .org ext_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - stw r9, IP_9(r1) /* r9 will be restored in the next level */ - stw r10, IP_10(r1) - - lis r9, m821@ha - addi r9, r9, m821@l - lbz r10, 0x1c(r9) /* SIVEC */ - rlwinm r10, r10, 4, 0, 27 /* each psuedo vector will have */ - /* room for 16 instructions */ - addis r10, r10, siu_vectors@ha - addi r10, r10, siu_vectors@l - mflr r0 - mtlr r10 - lwz r10, IP_10(r1) - blr - -/* Align exception */ - .org align_vector - file_base - .extern align_h - b align_h - -/* Program exception */ - .org prog_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROGRAM - b PROC (_ISR_Handler) - -/* Float exception */ - .org float_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_NOFP - b PROC (_ISR_Handler) - -/* Decrementer exception */ - .org dec_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROGRAM - b PROC (_ISR_Handler) - -/* System call */ - .org sys_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_SCALL - b PROC (_ISR_Handler) - -/* Trace interrupt */ - .org trace_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_TRACE - b PROC (_ISR_Handler) - - .org itlbm_vector - file_base -itlbm_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org dtlbm_vector - file_base -dtlbm_vectors: - mfspr r1, 0x1a - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - lis r3, 0x400 - mtspr 792, r3 - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mtspr 824, r18 - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org itlbe_vector - file_base -itlbe_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org dtlbe_vector - file_base -dtlbe_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - - -/* Now we look at what signaled the interrupt to the SIU. */ -/* I needed to do this in order to decode the CPM interrupts before */ -/* calling _ISR_Handler */ - -/* *IRQ0 */ - .org siu_vector - file_base -siu_vectors: - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ0 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 0 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL0 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ1 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* This is probably not the "correct" way to do this. I need to have a - * way of calling _ISR_Handler for the CPM interrupts and this is the - * simplest way I can think of. Since I have the CPM interrupt mapped - * to the SIU interrupt level 1 on the eth-comm board, I put it here. - * It would probably be ok if I moved this directory to under libbsp - * instead of libcpu. For now, deal with it. -*/ -/* Level 1 - CPM */ -/* Now we need to get the CPM interrupt vector */ - /* Registers: */ - /* R0 - has stored value of LR */ - /* R9 - pointer to m821 struct */ - /* R10 has already been saved and restored */ - li r10, 1 - sth r10, 0x930(r9) /* CIVR */ - lbz r10, 0x930(r9) /* if we use this as an offset into a */ - rlwinm r10, r10, 1, 0, 31 /* table, each entry will have room */ - /* 4 instructions. */ - addis r10, r10, cpm_vectors@ha - addi r10, r10, cpm_vectors@l - - mtlr r10 - lwz r10, IP_10(r1) - blr - - nop - nop - nop - nop - nop - nop - nop - -#if 0 -/* Level 1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL1 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -#endif - -/* *IRQ2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ2 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL2 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ3 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL3 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ4 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL4 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ5 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL5 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ6 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL6 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ7 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL7 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - -/* .org cpm_vector - file_base*/ -cpm_vectors: - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_0 - .long 0 - - /* PC4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC4 - b PROC (_ISR_Handler) - - /* PC5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC5 - b PROC (_ISR_Handler) - - /* SMC2 / PIP */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SMC2 - b PROC (_ISR_Handler) - - /* SMC1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SMC1 - b PROC (_ISR_Handler) - - /* SPI */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SPI - b PROC (_ISR_Handler) - - /* PC6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC6 - b PROC (_ISR_Handler) - - /* Timer 4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER4 - b PROC (_ISR_Handler) - - /* Reserved - we should never see this */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_8 - .long 0 - - /* PC7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC7 - b PROC (_ISR_Handler) - - /* PC8 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC8 - b PROC (_ISR_Handler) - - /* PC9 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC9 - b PROC (_ISR_Handler) - - /* Timer 3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER3 - b PROC (_ISR_Handler) - - /* Reserved - we should never get here */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_D - .long 0 - - /* PC10 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC10 - b PROC (_ISR_Handler) - - /* PC11 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC11 - b PROC (_ISR_Handler) - - /* I2C */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_I2C - b PROC (_ISR_Handler) - - /* RISC Timer Table */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RISC_TIMER - b PROC (_ISR_Handler) - - /* Timer 2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER2 - b PROC (_ISR_Handler) - - /* Reserved - we should never get here */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_13 - .long 0 - - /* IDMA2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_IDMA2 - b PROC (_ISR_Handler) - - /* IDMA1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_IDMA1 - b PROC (_ISR_Handler) - - /* SDMA Channel Bus Error */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SDMA_ERROR - b PROC (_ISR_Handler) - - /* PC12 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC12 - b PROC (_ISR_Handler) - - /* PC13 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC13 - b PROC (_ISR_Handler) - - /* Timer 1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER1 - b PROC (_ISR_Handler) - - /* PC14 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC14 - b PROC (_ISR_Handler) - - /* SCC4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC4 - b PROC (_ISR_Handler) - - /* SCC3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC3 - b PROC (_ISR_Handler) - - /* SCC2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC2 - b PROC (_ISR_Handler) - - /* SCC1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC1 - b PROC (_ISR_Handler) - - /* PC15 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC15 - b PROC (_ISR_Handler) - - - diff --git a/c/src/lib/libcpu/powerpc/mpc860/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/Makefile.am deleted file mode 100644 index a5679c9061..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/Makefile.am +++ /dev/null @@ -1,10 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -SUBDIRS = include console-generic clock timer vectors - -include $(top_srcdir)/../../../../../automake/subdirs.am -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/README b/c/src/lib/libcpu/powerpc/mpc860/README deleted file mode 100644 index 211916489d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/README +++ /dev/null @@ -1,19 +0,0 @@ -# -# $Id$ -# - -Various non BSP dependant support routines. - -clock - Uses the MPC860 PITPIT (Programmable interval timer) to - generate RTEMS clock ticks. - -console_generic - Uses the MPC860 SCCs and SMCs to to serial I/O - -include - console.h: function declarations for console related functions - -timer - Uses the MPC860 timebase register for timing - tests. It only uses the lower 32 bits - -vectors - MPC860 specific vector entry points. - Includes CPU dependant, application independant - handlers: alignment. diff --git a/c/src/lib/libcpu/powerpc/mpc860/clock/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/clock/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/clock/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.am deleted file mode 100644 index f8b46ecc12..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/clock.rel - -C_FILES = clock.c - -clock_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(clock_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(clock_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = clock.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c deleted file mode 100644 index 73a586aa6a..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c +++ /dev/null @@ -1,179 +0,0 @@ -/* clock.c - * - * This routine initializes the PIT on the MPC860. - * The tick frequency is specified by the bsp. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <clockdrv.h> -#include <rtems/libio.h> - -#include <stdlib.h> /* for atexit() */ -#include <mpc860.h> - -volatile rtems_unsigned32 Clock_driver_ticks; -extern volatile m860_t m860; - -void Clock_exit( void ); - -/* - * These are set by clock driver during its init - */ - -rtems_device_major_number rtems_clock_major = ~0; -rtems_device_minor_number rtems_clock_minor; - -/* - * ISR Handler - */ -rtems_isr Clock_isr(rtems_vector_number vector) -{ - m860.piscr |= M860_PISCR_PS; - Clock_driver_ticks++; - rtems_clock_tick(); -} - -void Install_clock(rtems_isr_entry clock_isr) -{ - rtems_isr_entry previous_isr; - rtems_unsigned32 pit_value; - - Clock_driver_ticks = 0; - - pit_value = rtems_configuration_get_microseconds_per_tick() / - rtems_cpu_configuration_get_clicks_per_usec(); - if (pit_value == 0) { - pit_value = 0xffff; - } else { - pit_value--; - } - - if (pit_value > 0xffff) { /* pit is only 16 bits long */ - rtems_fatal_error_occurred(-1); - } - - /* - * initialize the interval here - * First tick is set to right amount of time in the future - * Future ticks will be incremented over last value set - * in order to provide consistent clicks in the face of - * interrupt overhead - */ - - rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); - - m860.sccr &= ~(1<<24); - m860.pitc = pit_value; - - /* set PIT irq level, enable PIT, PIT interrupts */ - /* and clear int. status */ - m860.piscr = M860_PISCR_PIRQ(0) | - M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE; - - m860.simask |= M860_SIMASK_LVM0; - atexit(Clock_exit); -} - -void -ReInstall_clock(rtems_isr_entry new_clock_isr) -{ - rtems_isr_entry previous_isr; - rtems_unsigned32 isrlevel = 0; - - rtems_interrupt_disable(isrlevel); - - rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr); - - rtems_interrupt_enable(isrlevel); -} - - -/* - * Called via atexit() - * Remove the clock interrupt handler by setting handler to NULL - */ -void -Clock_exit(void) -{ - /* disable PIT and PIT interrupts */ - m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE); - - (void) set_vector(0, PPC_IRQ_LVL0, 1); -} - -rtems_device_driver Clock_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - Install_clock( Clock_isr ); - - /* - * make major/minor avail to others such as shared memory driver - */ - - rtems_clock_major = major; - rtems_clock_minor = minor; - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver Clock_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *pargp -) -{ - rtems_libio_ioctl_args_t *args = pargp; - - if (args == 0) - goto done; - - /* - * This is hokey, but until we get a defined interface - * to do this, it will just be this simple... - */ - - if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { - Clock_isr(PPC_IRQ_LVL0); - } - else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { - ReInstall_clock(args->buffer); - } - - done: - return RTEMS_SUCCESSFUL; -} - diff --git a/c/src/lib/libcpu/powerpc/mpc860/console-generic/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/console-generic/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/console-generic/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.am deleted file mode 100644 index b0c900fc7c..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/console-generic.rel - -C_FILES = console-generic.c - -console_generic_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(console_generic_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(console_generic_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = console-generic.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c deleted file mode 100644 index 76c1cb0314..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c +++ /dev/null @@ -1,929 +0,0 @@ -/* - * General Serial I/O functions. - * - * This file contains the functions for performing serial I/O. - * The actual system calls (console_*) should be in the BSP part - * of the source tree. That way different BSPs can use whichever - * SMCs and SCCs they want. Originally, all the stuff was in - * this file, and it caused problems with one BSP using SCC2 - * as /dev/console, others using SMC1 for /dev/console, etc. - * - * On-chip resources used: - * resource minor note - * SMC1 0 - * SMC2 1 - * SCC1 2 (shared with ethernet driver) - * SCC2 3 - * SCC3 4 - * SCC4 5 - * BRG1 - * BRG2 - * BRG3 - * BRG4 - * Author: Jay Monkman (jmonkman@frasca.com) - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: - * - * Author: - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <rtems/libio.h> -#include <mpc860.h> -#include <mpc860/console.h> -#include <stdlib.h> -#include <unistd.h> -#include <termios.h> - -#define NIFACES 6 /* number of console devices (serial ports) */ - -static Buf_t *rxBufList[NIFACES]; -static Buf_t *rxBufListTail[NIFACES]; - -/* - * Interrupt-driven input buffer - */ -#define RXBUFSIZE 16 - - -/* - * I/O buffers and pointers to buffer descriptors - */ -static volatile char txBuf[NIFACES]; - -static volatile m860BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; - -/* - * Device-specific routines - */ -static int m860_get_brg_cd(int); -unsigned char m860_get_brg_clk(int); -unsigned char m860_get_brg_clk(int); - - -/* - * Compute baud-rate-generator configuration register value - */ -static int -m860_get_brg_cd (int baud) -{ - int divisor; - int div16 = 0; - - divisor = ((rtems_cpu_configuration_get_clock_speed() / 16) + - (baud / 2)) / baud; - if (divisor > 4096) { - div16 = 1; - divisor = (divisor + 8) / 16; - } - return M860_BRG_EN | M860_BRG_EXTC_BRGCLK | - ((divisor - 1) << 1) | div16; -} - - -/* this function will fail if more that 4 baud rates have been selected */ -/* at any time since the OS started. It needs to be fixed. FIXME */ -unsigned char m860_get_brg_clk(int baud) -{ - static int brg_spd[4]; - static char brg_used[4]; - int i; - - /* first try to find a BRG that is already at the right speed */ - for (i=0; i<4; i++) { - if (brg_spd[i] == baud) { - break; - } - } - - if (i==4) { /* I guess we didn't find one */ - for (i=0; i<4; i++) { - if (brg_used[i] == 0) { - break; - } - } - } - if (i != 4) { - brg_used[i]++; - brg_spd[i]=baud; - switch (i) { - case 0: - m860.brgc1 = M860_BRG_RST; - m860.brgc1 = m860_get_brg_cd(baud); - break; - case 1: - m860.brgc2 = M860_BRG_RST; - m860.brgc2 = m860_get_brg_cd(baud); - break; - case 2: - m860.brgc3 = M860_BRG_RST; - m860.brgc3 = m860_get_brg_cd(baud); - break; - case 3: - m860.brgc4 = M860_BRG_RST; - m860.brgc4 = m860_get_brg_cd(baud); - break; - } - return i; - } - - else - return 0xff; -} - -/* - * Hardware-dependent portion of tcsetattr(). - */ -int -m860_smc_set_attributes (int minor, const struct termios *t) -{ - /* - * minor must be 0 or 1 - */ - int baud; - int brg; - switch (t->c_cflag & CBAUD) { - default: baud = -1; break; - case B50: baud = 50; break; - case B75: baud = 75; break; - case B110: baud = 110; break; - case B134: baud = 134; break; - case B150: baud = 150; break; - case B200: baud = 200; break; - case B300: baud = 300; break; - case B600: baud = 600; break; - case B1200: baud = 1200; break; - case B1800: baud = 1800; break; - case B2400: baud = 2400; break; - case B4800: baud = 4800; break; - case B9600: baud = 9600; break; - case B19200: baud = 19200; break; - case B38400: baud = 38400; break; - case B57600: baud = 57600; break; - case B115200: baud = 115200; break; - case B230400: baud = 230400; break; - case B460800: baud = 460800; break; - } - if (baud > 0) { - brg = m860_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ - /* at least 2 ports will be the same */ - m860.simode |= brg << (12 + ((minor) * 16)); - } - return 0; -} - -int -m860_scc_set_attributes (int minor, const struct termios *t) -{ - /* - * minor must be 2, 3, 4 or 5 - */ - int baud; - int brg; - switch (t->c_cflag & CBAUD) { - default: baud = -1; break; - case B50: baud = 50; break; - case B75: baud = 75; break; - case B110: baud = 110; break; - case B134: baud = 134; break; - case B150: baud = 150; break; - case B200: baud = 200; break; - case B300: baud = 300; break; - case B600: baud = 600; break; - case B1200: baud = 1200; break; - case B1800: baud = 1800; break; - case B2400: baud = 2400; break; - case B4800: baud = 4800; break; - case B9600: baud = 9600; break; - case B19200: baud = 19200; break; - case B38400: baud = 38400; break; - case B57600: baud = 57600; break; - case B115200: baud = 115200; break; - case B230400: baud = 230400; break; - case B460800: baud = 460800; break; - } - if (baud > 0) { - brg = m860_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - m860.sicr |= (brg << (3 + ((minor-2) * 8))) | - (brg << ((minor-2) * 8)); - } - return 0; -} - -void -m860_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ -{ - unsigned char brg; - volatile m860SCCparms_t *sccparms; - volatile m860SCCRegisters_t *sccregs; - - /* - * Allocate buffer descriptors - */ - RxBd[port+1] = M860AllocateBufferDescriptors(1); - TxBd[port+1] = M860AllocateBufferDescriptors(1); - - /* - * Configure ports A and B to enable TXDx and RXDx pins - */ - m860.papar |= (0xC << ((port-2) * 2)); - m860.padir &= ~(0xC << ((port-2) * 2)); - m860.pbdir |= (0x04 << (port-2)); - m860.paodr &= ~(0x8 << ((port-2) * 2)); - m860.pbdat &= ~(0x04 << (port-2)); - - /* SCC2 is the only one with handshaking lines */ - /* - if (port == 2) { - m860.pcpar |= (0x02); - m860.pcpar &= ~(0xc0); - m860.pcdir &= ~(0xc2); - m860.pcso |= (0xc0); - } - */ - - brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - - /* - * Set up SDMA - */ - m860.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC860UM/AD */ - - - m860.sicr &= ~(0xff << ((port-1) * 8)); - m860.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); - - /* - * Set up SMC1 parameter RAM common to all protocols - */ - if (port == 1) { - sccparms = (m860SCCparms_t*)&m860.scc1p; - sccregs = &m860.scc1; - } - else if (port == 2) { - sccparms = &m860.scc2p; - sccregs = &m860.scc2; - } - else if (port == 3) { - sccparms = &m860.scc3p; - sccregs = &m860.scc3; - } - else { - sccparms = &m860.scc4p; - sccregs = &m860.scc4; - } - - sccparms->rbase = (char *)RxBd[port+1] - (char *)&m860; - sccparms->tbase = (char *)TxBd[port+1] - (char *)&m860; - - if (port == 1) - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1); - else if (port == 2) - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC2); - else if (port == 3) - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC3); - else if (port == 4) - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC4); - - sccparms->rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); - sccparms->tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); - sccparms->mrblr = RXBUFSIZE; - - sccparms->un.uart.max_idl = 10; - sccparms->un.uart.brklen = 0; - sccparms->un.uart.brkec = 0; - sccparms->un.uart.brkcr = 1; - - sccparms->un.uart.parec = 0; - sccparms->un.uart.frmec = 0; - sccparms->un.uart.nosec = 0; - - sccparms->un.uart.uaddr[0] = 0; - sccparms->un.uart.uaddr[1] = 0; - sccparms->un.uart.toseq = 0; - - sccparms->un.uart.character[0] = 0x8000; - sccparms->un.uart.character[1] = 0x8000; - sccparms->un.uart.character[2] = 0x8000; - sccparms->un.uart.character[3] = 0x8000; - sccparms->un.uart.character[4] = 0x8000; - sccparms->un.uart.character[5] = 0x8000; - sccparms->un.uart.character[6] = 0x8000; - sccparms->un.uart.character[7] = 0x8000; - - sccparms->un.uart.rccm = 0xc0ff; - - /* - * Set up the Receive Buffer Descriptor - */ - RxBd[port+1]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - RxBd[port+1]->length = 0; - RxBd[port+1]->buffer = malloc(RXBUFSIZE); - - /* - * Setup the Transmit Buffer Descriptor - */ - TxBd[port+1]->status = M860_BD_WRAP; - - /* - * Set up SCCx general and protocol-specific mode registers - */ - sccregs->scce = 0xffff; - sccregs->sccm = 0x0000; - sccregs->gsmr_h = 0x00000020; - sccregs->gsmr_l = 0x00028004; - sccregs->psmr = 0x3000; - sccregs->gsmr_l = 0x00028034; -} - -void -m860_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ -{ - unsigned char brg; - - /* - * Allocate buffer descriptors - */ - RxBd[port-1] = M860AllocateBufferDescriptors (1); - TxBd[port-1] = M860AllocateBufferDescriptors (1); - - /* - * Configure port B pins to enable SMTXDx and SMRXDx pins - */ - m860.pbpar |= (0xC0 << ((port-1) * 4)); - m860.pbdir &= ~(0xC0 << ((port-1) * 4)); - m860.pbdir |= (0x01 << (port-1)); - m860.pbodr &= ~(0xC0 << ((port-1) * 4)); - m860.pbdat &= ~(0x01 << (port-1)); - - /* - * Set up BRG1 (9,600 baud) - */ - brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ - /* at least 2 ports will be the same */ - - /* - * Put SMC in NMSI mode, connect SMC to BRG - */ - m860.simode &= ~(0x7000 << ((port-1) * 16)); - m860.simode |= brg << (12 + ((port-1) * 16)); - - /* - * Set up SMC1 parameter RAM common to all protocols - */ - if (port == 1) { - m860.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m860; - m860.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m860; - m860.smc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); - m860.smc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); - m860.smc1p.mrblr = RXBUFSIZE; - - /* - * Set up SMC1 parameter RAM UART-specific parameters - */ - m860.smc1p.un.uart.max_idl = 10; - m860.smc1p.un.uart.brklen = 0; - m860.smc1p.un.uart.brkec = 0; - m860.smc1p.un.uart.brkcr = 0; - - } - else { - m860.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m860; - m860.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m860; - m860.smc2p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); - m860.smc2p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); - m860.smc2p.mrblr = RXBUFSIZE; - - /* - * Set up SMC2 parameter RAM UART-specific parameters - */ - m860.smc2p.un.uart.max_idl = 10; - m860.smc2p.un.uart.brklen = 0; - m860.smc2p.un.uart.brkec = 0; - m860.smc2p.un.uart.brkcr = 0; - } - - /* - * Set up the Receive Buffer Descriptor - */ - RxBd[port-1]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - RxBd[port-1]->length = 0; - RxBd[port-1]->buffer = malloc(RXBUFSIZE); - - /* - * Setup the Transmit Buffer Descriptor - */ - TxBd[port-1]->status = M860_BD_WRAP; - - /* - * Set up SMCx general and protocol-specific mode registers - */ - if (port == 1) { - m860.smc1.smce = ~0; /* Clear any pending events */ - m860.smc1.smcm = 0; /* Mask all interrupt/event sources */ - m860.smc1.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; - - /* - * Send "Init parameters" command - */ - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC1); - - /* - * Enable receiver and transmitter - */ - m860.smc1.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; - } - else { - m860.smc2.smce = ~0; /* Clear any pending events */ - m860.smc2.smcm = 0; /* Mask all interrupt/event sources */ - m860.smc2.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; - - /* - * Send "Init parameters" command - */ - M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC2); - - /* - * Enable receiver and transmitter - */ - m860.smc2.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; - } -} - -int -m860_char_poll_read (int minor) -{ - unsigned char c; - rtems_unsigned32 level; - - _CPU_ISR_Disable(level); - if (RxBd[minor]->status & M860_BD_EMPTY) { - _CPU_ISR_Enable(level); - return -1; - } - c = ((char *)RxBd[minor]->buffer)[0]; - RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; - _CPU_ISR_Enable(level); - return c; -} - -int -m860_char_poll_write (int minor, const char *buf, int len) -{ - while (len--) { - while (TxBd[minor]->status & M860_BD_READY) - continue; - txBuf[minor] = *buf++; - TxBd[minor]->buffer = &txBuf[minor]; - TxBd[minor]->length = 1; - TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; - } - return 0; -} - -/* - * Interrupt handler - */ -rtems_isr -m860_scc1_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m860.scc1.sccm & 0x1) && (m860.scc1.scce & 0x1)) { - m860.scc1.scce = 0x1; - /* m860.scc1.sccm &= ~0x1;*/ - - while ((RxBd[SCC1_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC1_MINOR]->next) { - rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; - rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; - rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; - rxBufListTail[SCC1_MINOR]->pos = 0; - rxBufListTail[SCC1_MINOR]->next = 0; - - RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ -} - -rtems_isr -m860_scc2_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m860.scc2.sccm & 0x1) && (m860.scc2.scce & 0x1)) { - m860.scc2.scce = 0x1; - /* m860.scc2.sccm &= ~0x1;*/ - - while ((RxBd[SCC2_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC2_MINOR]->next) { - rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; - rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; - rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; - rxBufListTail[SCC2_MINOR]->pos = 0; - rxBufListTail[SCC2_MINOR]->next = 0; - - RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ -} - -rtems_isr -m860_scc3_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m860.scc3.sccm & 0x1) && (m860.scc3.scce & 0x1)) { - m860.scc3.scce = 0x1; - /* m860.scc3.sccm &= ~0x1;*/ - - while ((RxBd[SCC3_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SCC3_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC3_MINOR]->next) { - rxBufListTail[SCC3_MINOR] = rxBufListTail[SCC3_MINOR]->next; - rxBufListTail[SCC3_MINOR]->buf = RxBd[SCC3_MINOR]->buffer; - rxBufListTail[SCC3_MINOR]->len = RxBd[SCC3_MINOR]->length; - rxBufListTail[SCC3_MINOR]->pos = 0; - rxBufListTail[SCC3_MINOR]->next = 0; - - RxBd[SCC3_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC3_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 28; /* Clear SCC3 interrupt-in-service bit */ -} - -rtems_isr -m860_scc4_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if ((m860.scc4.sccm & 0x1) && (m860.scc4.scce & 0x1)) { - m860.scc4.scce = 0x1; - /* m860.scc4.sccm &= ~0x1;*/ - - while ((RxBd[SCC4_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SCC4_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SCC4_MINOR]->next) { - rxBufListTail[SCC4_MINOR] = rxBufListTail[SCC4_MINOR]->next; - rxBufListTail[SCC4_MINOR]->buf = RxBd[SCC4_MINOR]->buffer; - rxBufListTail[SCC4_MINOR]->len = RxBd[SCC4_MINOR]->length; - rxBufListTail[SCC4_MINOR]->pos = 0; - rxBufListTail[SCC4_MINOR]->next = 0; - - RxBd[SCC4_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SCC4_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 27; /* Clear SCC4 interrupt-in-service bit */ -} - -rtems_isr -m860_smc1_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if (m860.smc1.smce & 0x1) { - m860.smc1.smce = 0x1; - /* m860.scc2.sccm &= ~0x1;*/ - - while ((RxBd[SMC1_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SMC1_MINOR]->next) { - rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; - rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; - rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; - rxBufListTail[SMC1_MINOR]->pos = 0; - rxBufListTail[SMC1_MINOR]->next = 0; - - RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SMC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ -} - -rtems_isr -m860_smc2_console_interrupt_handler (rtems_vector_number v) -{ - /* - * Buffer received? - */ - if (m860.smc2.smce & 0x1) { - m860.smc2.smce = 0x1; - - while ((RxBd[SMC2_MINOR]->status & M860_BD_EMPTY) == 0) { - rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); - if (rxBufListTail[SMC2_MINOR]->next) { - rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; - rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; - rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; - rxBufListTail[SMC2_MINOR]->pos = 0; - rxBufListTail[SMC2_MINOR]->next = 0; - - RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); - } - RxBd[SMC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | - M860_BD_INTERRUPT; - } - } - - /* - * Buffer transmitted? - */ -#if 0 - if (m860.smc1.smce & 0x2) { - m860.smc1.smce = 0x2; - if ((smcTxBd->status & M360_BD_READY) == 0) - rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); - } -#endif - m860.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ -} - - -int -m860_buf_poll_read (int minor, char **buf) -{ - int len; - - if (RxBd[minor]->status & M860_BD_EMPTY) - return -1; - - RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ - len = RxBd[minor]->length; - RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; - - return len; -} - -int -m860_buf_poll_write (int minor, char *buf, int len) -{ - static char *last_buf[6]; - - while (TxBd[minor]->status & M860_BD_READY) - continue; - if (last_buf[minor]) - free(last_buf[minor]); - last_buf[minor] = buf; - TxBd[minor]->buffer = buf; - TxBd[minor]->length = len; - TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; - return 0; -} - -void m860_console_initialize(void) -{ - int i; - - for (i=0; i < NIFACES; i++) { - rxBufList[i] = malloc(sizeof(Buf_t)); - rxBufListTail[i] = rxBufList[i]; - rxBufList[i]->buf = 0; - rxBufList[i]->len = 0; - rxBufList[i]->pos = 0; - rxBufList[i]->next = 0; - } -} - -rtems_device_driver m860_console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - rtems_libio_rw_args_t *rw_args; - char *buffer; - int maximum; - int count; - Buf_t *tmp_buf; - rtems_unsigned32 level; - - /* - * Set up interrupts - * FIXME: DANGER: WARNING: - * CICR and SIMASK must be set in any module that uses - * the CPM. Currently those are console-generic.c and - * network.c. If the registers are not set the same - * in both places, strange things may happen. - * If they are only set in one place, then an application - * that used the other module won't work correctly. - * Put this comment in each module that sets these 2 registers - */ - m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, - SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ - m860.simask |= M860_SIMASK_LVM1; - - rw_args = (rtems_libio_rw_args_t *) arg; - buffer = rw_args->buffer; - maximum = rw_args->count; - count = 0; - - while (count == 0) { - if (rxBufList[minor]->len) { - while ((count < maximum) && - (rxBufList[minor]->pos < rxBufList[minor]->len)) { - buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; - } - _CPU_ISR_Disable(level); - if (rxBufList[minor]->pos == rxBufList[minor]->len) { - if (rxBufList[minor]->next) { - tmp_buf=rxBufList[minor]->next; - free ((void *) rxBufList[minor]->buf); - free ((void *) rxBufList[minor]); - rxBufList[minor]=tmp_buf; - } - else { - free(rxBufList[minor]->buf); - rxBufList[minor]->buf=0; - rxBufList[minor]->len=0; - rxBufList[minor]->pos=0; - } - } - _CPU_ISR_Enable(level); - } - else - if(rxBufList[minor]->next && !rxBufList[minor]->len) { - tmp_buf = rxBufList[minor]; - rxBufList[minor] = rxBufList[minor]->next; - free(tmp_buf); - } - /* sleep(1);*/ - } - rw_args->bytes_moved = count; - return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; -} - -rtems_device_driver m860_console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - int count; - int maximum; - rtems_libio_rw_args_t *rw_args; - char *in_buffer; - char *out_buffer; - int n; - - /* - * Set up interrupts - * FIXME: DANGER: WARNING: - * CICR and SIMASK must be set in any module that uses - * the CPM. Currently those are console-generic.c and - * network.c. If the registers are not set the same - * in both places, strange things may happen. - * If they are only set in one place, then an application - * that used the other module won't work correctly. - * Put this comment in each module that sets these 2 registers - */ -#if 0 - m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, - SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ - m860.simask |= M860_SIMASK_LVM1; -#endif - - rw_args = (rtems_libio_rw_args_t *) arg; - - in_buffer = rw_args->buffer; - maximum = rw_args->count; - - out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ - /* be too small */ - - if (!out_buffer) { - rw_args->bytes_moved = 0; - return RTEMS_NO_MEMORY; - } - n=0; - for (count = 0; count < maximum; count++) { - if ( in_buffer[ count ] == '\n') { - out_buffer[count + n] = '\r'; - n++; - } - out_buffer[count + n] = in_buffer[count]; - } - m860_buf_poll_write(minor, out_buffer, maximum+n); - rw_args->bytes_moved = maximum; - return RTEMS_SUCCESSFUL; -} - - -/* - * How to use the console. - * In your BSP, have the following functions: - * - * rtems_device_driver console_initialize(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_open(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_close(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_read(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_write(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * rtems_device_driver console_control(rtems_device_major_number major, - * rtems_device_minor_number minor, - * void *arg) - * - */ diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/include/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/include/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.am deleted file mode 100644 index ebbb1a1e51..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -H_FILES = mpc860.h -MPC860_H_FILES = console.h - -noinst_HEADERS = $(H_FILES) $(MPC860_H_FILES) - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc860 \ - $(H_FILES:%.h=$(PROJECT_INCLUDE)/%.h) \ - $(MPC860_H_FILES:%.h=$(PROJECT_INCLUDE)/mpc860/%.h) - -$(PROJECT_INCLUDE)/mpc860: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE)/mpc860/%.h: %.h - $(INSTALL_DATA) $< $@ - -all-local: $(PREINSTALL_FILES) - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/console.h b/c/src/lib/libcpu/powerpc/mpc860/include/console.h deleted file mode 100644 index 27a6a36377..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/include/console.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * $Id$ - */ - -#ifndef _M860_CONSOLE_H_ -#define _M860_CONSOLE_H_ - -#include <rtems/libio.h> - -int m860_smc_set_attributes(int, const struct termios*); -int m860_scc_set_attributes(int, const struct termios*); -void m860_scc_initialize(int); -void m860_smc_initialize(int); -int m860_char_poll_read(int); -int m860_char_poll_write(int, const char*, int); -rtems_isr m860_scc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m860_scc2_console_interrupt_handler(rtems_vector_number); -rtems_isr m860_scc3_console_interrupt_handler(rtems_vector_number); -rtems_isr m860_scc4_console_interrupt_handler(rtems_vector_number); -rtems_isr m860_smc1_console_interrupt_handler(rtems_vector_number); -rtems_isr m860_smc2_console_interrupt_handler(rtems_vector_number); -int m860_buf_poll_read(int, char**); -int m860_buf_poll_write(int, char*, int); -void m860_console_initialize(void); -rtems_device_driver m860_console_read(rtems_device_major_number, - rtems_device_minor_number, - void*); -rtems_device_driver m860_console_write(rtems_device_major_number, - rtems_device_minor_number, - void*); - - -typedef struct Buf_t_ { - struct Buf_t_ *next; - volatile char *buf; - volatile int len; - int pos; -} Buf_t; - -#define SMC1_MINOR 0 -#define SMC2_MINOR 1 -#define SCC1_MINOR 2 -#define SCC2_MINOR 3 -#define SCC3_MINOR 4 -#define SCC4_MINOR 5 - - -#endif diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/mpc860.h b/c/src/lib/libcpu/powerpc/mpc860/include/mpc860.h deleted file mode 100644 index 4a9c20f049..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/include/mpc860.h +++ /dev/null @@ -1,1300 +0,0 @@ -/* -************************************************************************** -************************************************************************** -** ** -** MOTOROLA MPC860 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** -** POWERQUICC ** -** ** -** HARDWARE DECLARATIONS ** -** ** -** ** -** Submitted By: ** -** ** -** W. Eric Norum ** -** Saskatchewan Accelerator Laboratory ** -** University of Saskatchewan ** -** 107 North Road ** -** Saskatoon, Saskatchewan, CANADA ** -** S7N 5C6 ** -** ** -** eric@skatter.usask.ca ** -** ** -** Modified for use with the MPC860 (original code was for MC68360) ** -** by ** -** Jay Monkman ** -** Frasca International, Inc. ** -** 906 E. Airport Rd. ** -** Urbana, IL, 61801 ** -** ** -** jmonkman@frasca.com ** -** ** -************************************************************************** -************************************************************************** -*/ - -#ifndef __MPC860_h -#define __MPC860_h - -#ifndef ASM -/* - Macros for SPRs -*/ - -#define M860_MI_CTR_GPM (1<<31) -#define M860_MI_CTR_PPM (1<<30) -#define M860_MI_CTR_CIDEF (1<<29) -#define M860_MI_CTR_RSV4I (1<<27) -#define M860_MI_CTR_PPCS (1<<25) - -#define M860_MD_CTR_GPM (1<<31) -#define M860_MD_CTR_PPM (1<<30) -#define M860_MD_CTR_CIDEF (1<<29) -#define M860_MD_CTR_WTDEF (1<<28) -#define M860_MD_CTR_RSV4D (1<<27) -#define M860_MD_CTR_TWAM (1<<26) -#define M860_MD_CTR_PPCS (1<<25) - -#define M860_MI_EPN_VALID (1<<9) - -#define M860_MD_EPN_VALID (1<<9) - -#define M860_MI_TWC_G (1<<4) -#define M860_MI_TWC_PSS (0<<2) -#define M860_MI_TWC_PS512 (1<<2) -#define M860_MI_TWC_PS8 (3<<2) -#define M860_MI_TWC_VALID (1) - -#define M860_MD_TWC_G (1<<4) -#define M860_MD_TWC_PSS (0<<2) -#define M860_MD_TWC_PS512 (1<<2) -#define M860_MD_TWC_PS8 (3<<2) -#define M860_MD_TWC_WT (1<<1) -#define M860_MD_TWC_VALID (1) - -#define M860_MI_RPN_F (0xf<<4) -#define M860_MI_RPN_16K (1<<3) -#define M860_MI_RPN_SHARED (1<<2) -#define M860_MI_RPN_CI (1<<1) -#define M860_MI_RPN_VALID (1) - -#define M860_MD_RPN_CHANGE (1<<8) -#define M860_MD_RPN_F (0xf<<4) -#define M860_MD_RPN_16K (1<<3) -#define M860_MD_RPN_SHARED (1<<2) -#define M860_MD_RPN_CI (1<<1) -#define M860_MD_RPN_VALID (1) - -#define M860_MI_AP_Kp (1) - -#define M860_MD_AP_Kp (1) - -#define M860_CACHE_CMD_SFWT (0x1<<24) -#define M860_CACHE_CMD_ENABLE (0x2<<24) -#define M860_CACHE_CMD_CFWT (0x3<<24) -#define M860_CACHE_CMD_DISABLE (0x4<<24) -#define M860_CACHE_CMD_STLES (0x5<<24) -#define M860_CACHE_CMD_LLCB (0x6<<24) -#define M860_CACHE_CMD_CLES (0x7<<24) -#define M860_CACHE_CMD_UNLOCK (0x8<<24) -#define M860_CACHE_CMD_UNLOCKALL (0xa<<24) -#define M860_CACHE_CMD_INVALIDATE (0xc<<24) -#define M860_CACHE_CMD_FLUSH (0xe<<24) - - - -/* -************************************************************************* -* REGISTER SUBBLOCKS * -************************************************************************* -*/ - -/* - * Memory controller registers - */ -typedef struct m860MEMCRegisters_ { - rtems_unsigned32 _br; - rtems_unsigned32 _or; -} m860MEMCRegisters_t; - -/* - * Serial Communications Controller registers - */ -typedef struct m860SCCRegisters_ { - rtems_unsigned32 gsmr_l; - rtems_unsigned32 gsmr_h; - rtems_unsigned16 psmr; - rtems_unsigned16 _pad0; - rtems_unsigned16 todr; - rtems_unsigned16 dsr; - rtems_unsigned16 scce; - rtems_unsigned16 _pad1; - rtems_unsigned16 sccm; - rtems_unsigned8 _pad2; - rtems_unsigned8 sccs; - rtems_unsigned32 _pad3[2]; -} m860SCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m860SMCRegisters_ { - rtems_unsigned16 _pad0; - rtems_unsigned16 smcmr; - rtems_unsigned16 _pad1; - rtems_unsigned8 smce; - rtems_unsigned8 _pad2; - rtems_unsigned16 _pad3; - rtems_unsigned8 smcm; - rtems_unsigned8 _pad4; - rtems_unsigned32 _pad5; -} m860SMCRegisters_t; - -/* - * Fast Ethernet Controller registers (Only on MPC860T) - */ -typedef struct m860FECRegisters_ { - rtems_unsigned32 addr_low; - rtems_unsigned32 addr_high; - rtems_unsigned32 hash_table_high; - rtems_unsigned32 hash_table_low; - rtems_unsigned32 r_des_start; - rtems_unsigned32 x_des_start; - rtems_unsigned32 r_buf_size; - rtems_unsigned32 _pad0[9]; - rtems_unsigned32 ecntrl; - rtems_unsigned32 ievent; - rtems_unsigned32 imask; - rtems_unsigned32 ivec; - rtems_unsigned32 r_des_active; - rtems_unsigned32 x_des_active; - rtems_unsigned32 _pad1[10]; - rtems_unsigned32 mii_data; - rtems_unsigned32 mii_speed; - rtems_unsigned32 _pad2[17]; - rtems_unsigned32 r_bound; - rtems_unsigned32 r_fstart; - rtems_unsigned32 _pad3[6]; - rtems_unsigned32 x_fstart; - rtems_unsigned32 _pad4[17]; - rtems_unsigned32 fun_code; - rtems_unsigned32 _pad5[3]; - rtems_unsigned32 r_cntrl; - rtems_unsigned32 r_hash; - rtems_unsigned32 _pad6[14]; - rtems_unsigned32 x_cntrl; - rtems_unsigned32 _pad7[30]; - -} m860FECRegisters_t; - -#define M860_FEC_IEVENT_HBERR (1 << 31) -#define M860_FEC_IEVENT_BABR (1 << 30) -#define M860_FEC_IEVENT_BABT (1 << 29) -#define M860_FEC_IEVENT_GRA (1 << 28) -#define M860_FEC_IEVENT_TFINT (1 << 27) -#define M860_FEC_IEVENT_TXB (1 << 26) -#define M860_FEC_IEVENT_RFINT (1 << 25) -#define M860_FEC_IEVENT_RXB (1 << 24) -#define M860_FEC_IEVENT_MII (1 << 23) -#define M860_FEC_IEVENT_EBERR (1 << 22) -#define M860_FEC_IMASK_HBEEN (1 << 31) -#define M860_FEC_IMASK_BREEN (1 << 30) -#define M860_FEC_IMASK_BTEN (1 << 29) -#define M860_FEC_IMASK_GRAEN (1 << 28) -#define M860_FEC_IMASK_TFIEN (1 << 27) -#define M860_FEC_IMASK_TBIEN (1 << 26) -#define M860_FEC_IMASK_RFIEN (1 << 25) -#define M860_FEC_IMASK_RBIEN (1 << 24) -#define M860_FEC_IMASK_MIIEN (1 << 23) -#define M860_FEC_IMASK_EBERREN (1 << 22) - - -/* -************************************************************************* -* Miscellaneous Parameters * -************************************************************************* -*/ -typedef struct m860MiscParms_ { - rtems_unsigned16 rev_num; - rtems_unsigned16 _res1; - rtems_unsigned32 _res2; - rtems_unsigned32 _res3; -} m860MiscParms_t; - -/* -************************************************************************* -* RISC Timers * -************************************************************************* -*/ -typedef struct m860TimerParms_ { - rtems_unsigned16 tm_base; - rtems_unsigned16 _tm_ptr; - rtems_unsigned16 _r_tmr; - rtems_unsigned16 _r_tmv; - rtems_unsigned32 tm_cmd; - rtems_unsigned32 tm_cnt; -} m860TimerParms_t; - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are reserved. - */ -#define M860_RCCR_TIME (1<<15) /* Enable timer */ -#define M860_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ -#define M860_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ -#define M860_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ -#define M860_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ -#define M860_RCCR_EIE (1<<3) /* External Interrupt Enable */ -#define M860_RCCR_SCD (1<<2) /* Scheduler Configuration */ -#define M860_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ - -/* - * Command register - * Set up this register before issuing a M860_CR_OP_SET_TIMER command. - */ -#define M860_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M860_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M860_TM_CMD_PWM (1<<29) /* Set for PWM operation */ -#define M860_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M860_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ - -/* -************************************************************************* -* DMA Controllers * -************************************************************************* -*/ -typedef struct m860IDMAparms_ { - rtems_unsigned16 ibase; - rtems_unsigned16 dcmr; - rtems_unsigned32 _sapr; - rtems_unsigned32 _dapr; - rtems_unsigned16 ibptr; - rtems_unsigned16 _write_sp; - rtems_unsigned32 _s_byte_c; - rtems_unsigned32 _d_byte_c; - rtems_unsigned32 _s_state; - rtems_unsigned32 _itemp[4]; - rtems_unsigned32 _sr_mem; - rtems_unsigned16 _read_sp; - rtems_unsigned16 _res0; - rtems_unsigned16 _res1; - rtems_unsigned16 _res2; - rtems_unsigned32 _d_state; -} m860IDMAparms_t; - - -/* -************************************************************************* -* DSP * -************************************************************************* -*/ -typedef struct m860DSPparms_ { - rtems_unsigned32 fdbase; - rtems_unsigned32 _fd_ptr; - rtems_unsigned32 _dstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _dstatus; - rtems_unsigned16 _i; - rtems_unsigned16 _tap; - rtems_unsigned16 _cbase; - rtems_unsigned16 _pad1; - rtems_unsigned16 _xptr; - rtems_unsigned16 _pad2; - rtems_unsigned16 _yptr; - rtems_unsigned16 _m; - rtems_unsigned16 _pad3; - rtems_unsigned16 _n; - rtems_unsigned16 _pad4; - rtems_unsigned16 _k; - rtems_unsigned16 _pad5; -} m860DSPparms_t; - -/* -************************************************************************* -* Serial Communication Controllers * -************************************************************************* -*/ -typedef struct m860SCCparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - rtems_unsigned32 _rcrc; - rtems_unsigned32 _tcrc; - union { - struct { - rtems_unsigned32 _res0; - rtems_unsigned32 _res1; - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brkcr; - rtems_unsigned16 parec; - rtems_unsigned16 frmec; - rtems_unsigned16 nosec; - rtems_unsigned16 brkec; - rtems_unsigned16 brklen; - rtems_unsigned16 uaddr[2]; - rtems_unsigned16 _rtemp; - rtems_unsigned16 toseq; - rtems_unsigned16 character[8]; - rtems_unsigned16 rccm; - rtems_unsigned16 rccr; - rtems_unsigned16 rlbc; - } uart; - } un; -} m860SCCparms_t; - -typedef struct m860SCCENparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - rtems_unsigned32 _rcrc; - rtems_unsigned32 _tcrc; - union { - struct { - rtems_unsigned32 _res0; - rtems_unsigned32 _res1; - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brkcr; - rtems_unsigned16 parec; - rtems_unsigned16 frmec; - rtems_unsigned16 nosec; - rtems_unsigned16 brkec; - rtems_unsigned16 brklen; - rtems_unsigned16 uaddr[2]; - rtems_unsigned16 _rtemp; - rtems_unsigned16 toseq; - rtems_unsigned16 character[8]; - rtems_unsigned16 rccm; - rtems_unsigned16 rccr; - rtems_unsigned16 rlbc; - } uart; - struct { - rtems_unsigned32 c_pres; - rtems_unsigned32 c_mask; - rtems_unsigned32 crcec; - rtems_unsigned32 alec; - rtems_unsigned32 disfc; - rtems_unsigned16 pads; - rtems_unsigned16 ret_lim; - rtems_unsigned16 _ret_cnt; - rtems_unsigned16 mflr; - rtems_unsigned16 minflr; - rtems_unsigned16 maxd1; - rtems_unsigned16 maxd2; - rtems_unsigned16 _maxd; - rtems_unsigned16 dma_cnt; - rtems_unsigned16 _max_b; - rtems_unsigned16 gaddr1; - rtems_unsigned16 gaddr2; - rtems_unsigned16 gaddr3; - rtems_unsigned16 gaddr4; - rtems_unsigned32 _tbuf0data0; - rtems_unsigned32 _tbuf0data1; - rtems_unsigned32 _tbuf0rba0; - rtems_unsigned32 _tbuf0crc; - rtems_unsigned16 _tbuf0bcnt; - rtems_unsigned16 paddr_h; - rtems_unsigned16 paddr_m; - rtems_unsigned16 paddr_l; - rtems_unsigned16 p_per; - rtems_unsigned16 _rfbd_ptr; - rtems_unsigned16 _tfbd_ptr; - rtems_unsigned16 _tlbd_ptr; - rtems_unsigned32 _tbuf1data0; - rtems_unsigned32 _tbuf1data1; - rtems_unsigned32 _tbuf1rba0; - rtems_unsigned32 _tbuf1crc; - rtems_unsigned16 _tbuf1bcnt; - rtems_unsigned16 _tx_len; - rtems_unsigned16 iaddr1; - rtems_unsigned16 iaddr2; - rtems_unsigned16 iaddr3; - rtems_unsigned16 iaddr4; - rtems_unsigned16 _boff_cnt; - rtems_unsigned16 taddr_l; - rtems_unsigned16 taddr_m; - rtems_unsigned16 taddr_h; - } ethernet; - } un; -} m860SCCENparms_t; - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M860_RFCR_BO(x) ((x)<<3) -#define M860_RFCR_MOT (2<<3) -#define M860_RFCR_DMA_SPACE(x) (x) -#define M860_TFCR_BO(x) ((x)<<3) -#define M860_TFCR_MOT (2<<3) -#define M860_TFCR_DMA_SPACE(x) (x) - -/* -************************************************************************* -* Serial Management Controllers * -************************************************************************* -*/ -typedef struct m860SMCparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; - union { - struct { - rtems_unsigned16 max_idl; - rtems_unsigned16 _idlc; - rtems_unsigned16 brklen; - rtems_unsigned16 brkec; - rtems_unsigned16 brkcr; - rtems_unsigned16 _r_mask; - } uart; - struct { - rtems_unsigned16 _pad0[5]; - } transparent; - } un; -} m860SMCparms_t; - -/* - * Mode register - */ -#define M860_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M860_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M860_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M860_SMCMR_EVEN (1<<8) /* Even parity */ -#define M860_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M860_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M860_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M860_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M860_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M860_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M860_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M860_SMCE_BRKE (1<<6) -#define M860_SMCE_BRK (1<<4) -#define M860_SMCE_BSY (1<<2) -#define M860_SMCE_TX (1<<1) -#define M860_SMCE_RX (1<<0) - -/* -************************************************************************* -* Serial Peripheral Interface * -************************************************************************* -*/ -typedef struct m860SPIparms_ { - rtems_unsigned16 rbase; - rtems_unsigned16 tbase; - rtems_unsigned8 rfcr; - rtems_unsigned8 tfcr; - rtems_unsigned16 mrblr; - rtems_unsigned32 _rstate; - rtems_unsigned32 _pad0; - rtems_unsigned16 _rbptr; - rtems_unsigned16 _pad1; - rtems_unsigned32 _pad2; - rtems_unsigned32 _tstate; - rtems_unsigned32 _pad3; - rtems_unsigned16 _tbptr; - rtems_unsigned16 _pad4; - rtems_unsigned32 _pad5; -} m860SPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M860_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M860_SPMODE_CI (1<<13) /* Clock invert */ -#define M860_SPMODE_CP (1<<12) /* Clock phase */ -#define M860_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M860_SPMODE_REV (1<<10) /* Reverse data */ -#define M860_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M860_SPMODE_EN (1<<8) /* Enable SPI */ -#define M860_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M860_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M860_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M860_SPIE_MME (1<<5) /* Multi-master error */ -#define M860_SPIE_TXE (1<<4) /* Tx error */ -#define M860_SPIE_BSY (1<<2) /* Busy condition*/ -#define M860_SPIE_TXB (1<<1) /* Tx buffer */ -#define M860_SPIE_RXB (1<<0) /* Rx buffer */ - -/* -************************************************************************* -* SDMA (SCC, SMC, SPI) Buffer Descriptors * -************************************************************************* -*/ -typedef struct m860BufferDescriptor_ { - rtems_unsigned16 status; - rtems_unsigned16 length; - volatile void *buffer; -} m860BufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M860_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M860_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M860_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M860_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M860_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M860_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M860_BD_ADDRESS (1<<10) /* SCC UART */ -#define M860_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M860_BD_MISS (1<<8) /* Ethernet */ -#define M860_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M860_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M860_BD_LONG (1<<5) /* Ethernet */ -#define M860_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M860_BD_NONALIGNED (1<<4) /* Ethernet */ -#define M860_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M860_BD_SHORT (1<<3) /* Ethernet */ -#define M860_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M860_BD_CRC_ERROR (1<<2) /* Ethernet */ -#define M860_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M860_BD_COLLISION (1<<0) /* Ethernet */ -#define M860_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ -#define M860_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M860_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M860_BD_PAD (1<<14) /* Ethernet */ -#define M860_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M860_BD_TX_CRC (1<<10) /* Ethernet */ -#define M860_BD_DEFER (1<<9) /* Ethernet */ -#define M860_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M860_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M860_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M860_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M860_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M860_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M860_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ -#define M860_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M860_BD_CTS_LOST (1<<0) /* SCC UART */ - -/* -************************************************************************* -* IDMA Buffer Descriptors * -************************************************************************* -*/ -typedef struct m860IDMABufferDescriptor_ { - rtems_unsigned16 status; - rtems_unsigned8 dfcr; - rtems_unsigned8 sfcr; - rtems_unsigned32 length; - void *source; - void *destination; -} m860IDMABufferDescriptor_t; - -/* -************************************************************************* -* RISC Communication Processor Module Command Register (CR) * -************************************************************************* -*/ -#define M860_CR_RST (1<<15) /* Reset communication processor */ -#define M860_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ -#define M860_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ -#define M860_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ -#define M860_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ -#define M860_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ -#define M860_CR_OP_GR_STOP_TX (5<<8) /* SCC */ -#define M860_CR_OP_INIT_IDMA (5<<8) /* IDMA */ -#define M860_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ -#define M860_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ -#define M860_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ -#define M860_CR_OP_SET_TIMER (8<<8) /* Timer */ -#define M860_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ -#define M860_CR_OP_RESERT_BCS (10<<8) /* SCC */ -#define M860_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ -#define M860_CR_OP_STOP_IDMA (11<<8) /* IDMA */ -#define M860_CR_OP_START_DSP (12<<8) /* DSP */ -#define M860_CR_OP_INIT_DSP (13<<8) /* DSP */ - -#define M860_CR_CHAN_SCC1 (0<<4) /* Channel selection */ -#define M860_CR_CHAN_I2C (1<<4) -#define M860_CR_CHAN_IDMA1 (1<<4) -#define M860_CR_CHAN_SCC2 (4<<4) -#define M860_CR_CHAN_SPI (5<<4) -#define M860_CR_CHAN_IDMA2 (5<<4) -#define M860_CR_CHAN_TIMER (5<<4) -#define M860_CR_CHAN_SCC3 (8<<4) -#define M860_CR_CHAN_SMC1 (9<<4) -#define M860_CR_CHAN_DSP1 (9<<4) -#define M860_CR_CHAN_SCC4 (12<<4) -#define M860_CR_CHAN_SMC2 (13<<4) -#define M860_CR_CHAN_DSP2 (13<<4) -#define M860_CR_FLG (1<<0) /* Command flag */ - -/* -************************************************************************* -* System Protection Control Register (SYPCR) * -************************************************************************* -*/ -#define M860_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ -#define M860_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ -#define M860_SYPCR_BME (1<<7) /* Bus monitor enable */ -#define M860_SYPCR_SWF (1<<3) /* Software watchdog freeze */ -#define M860_SYPCR_SWE (1<<2) /* Software watchdog enable */ -#define M860_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ -#define M860_SYPCR_SWP (1<<0) /* Software watchdog prescale */ - -/* -************************************************************************* -* Memory Control Registers * -************************************************************************* -*/ -#define M860_UPM_AMX_8col (0<<20) /* 8 column DRAM */ -#define M860_UPM_AMX_9col (1<<20) /* 9 column DRAM */ -#define M860_UPM_AMX_10col (2<<20) /* 10 column DRAM */ -#define M860_UPM_AMX_11col (3<<20) /* 11 column DRAM */ -#define M860_UPM_AMX_12col (4<<20) /* 12 column DRAM */ -#define M860_UPM_AMX_13col (5<<20) /* 13 column DRAM */ -#define M860_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ -#define M860_MSR_WPER (1<<7) /* Write protection error */ -#define M860_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ -#define M860_BR_BA(x) ((x)&0xffff8000) /* Base address */ -#define M860_BR_AT(x) ((x)<<12) /* Address type */ -#define M860_BR_PS8 (1<<10) /* 8 bit port */ -#define M860_BR_PS16 (2<<10) /* 16 bit port */ -#define M860_BR_PS32 (0<<10) /* 32 bit port */ -#define M860_BR_PARE (1<<9) /* Parity checking enable */ -#define M860_BR_WP (1<<8) /* Write protect */ -#define M860_BR_MS_GPCM (0<<6) /* GPCM */ -#define M860_BR_MS_UPMA (2<<6) /* UPM A */ -#define M860_BR_MS_UPMB (3<<6) /* UPM B */ -#define M860_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M860_MEMC_OR_32K 0xffff8000 /* Address range */ -#define M860_MEMC_OR_64K 0xffff0000 -#define M860_MEMC_OR_128K 0xfffe0000 -#define M860_MEMC_OR_256K 0xfffc0000 -#define M860_MEMC_OR_512K 0xfff80000 -#define M860_MEMC_OR_1M 0xfff00000 -#define M860_MEMC_OR_2M 0xffe00000 -#define M860_MEMC_OR_4M 0xffc00000 -#define M860_MEMC_OR_8M 0xff800000 -#define M860_MEMC_OR_16M 0xff000000 -#define M860_MEMC_OR_32M 0xfe000000 -#define M860_MEMC_OR_64M 0xfc000000 -#define M860_MEMC_OR_128 0xf8000000 -#define M860_MEMC_OR_256M 0xf0000000 -#define M860_MEMC_OR_512M 0xe0000000 -#define M860_MEMC_OR_1G 0xc0000000 -#define M860_MEMC_OR_2G 0x80000000 -#define M860_MEMC_OR_4G 0x00000000 -#define M860_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ -#define M860_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ -#define M860_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ -#define M860_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ -#define M860_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ -#define M860_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ -#define M860_MEMC_OR_BI (1<8) /* Burst inhibit */ -#define M860_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ -#define M860_MEMC_OR_SETA (1<<3) /* *TA generated externally */ -#define M860_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ -#define M860_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ - -/* -************************************************************************* -* UPM Registers (MxMR) * -************************************************************************* -*/ -#define M860_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ -#define M860_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ -#define M860_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ -#define M860_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ -#define M860_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ -#define M860_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ -#define M860_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ -#define M860_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ -/* -************************************************************************* -* Memory Command Register (MCR) * -************************************************************************* -*/ -#define M860_MEMC_MCR_WRITE (0<<30) /* WRITE command */ -#define M860_MEMC_MCR_READ (1<<30) /* READ command */ -#define M860_MEMC_MCR_RUN (2<<30) /* RUN command */ -#define M860_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ -#define M860_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ -#define M860_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ -#define M860_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ -#define M860_MEMC_MCR_MAD(x) (x) /* Machine address */ - - - -/* -************************************************************************* -* SI Mode Register (SIMODE) * -************************************************************************* -*/ -#define M860_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M860_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M860_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M860_SI_SMC2_BRG2 (1<<28) -#define M860_SI_SMC2_BRG3 (2<<28) -#define M860_SI_SMC2_BRG4 (3<<28) -#define M860_SI_SMC2_CLK5 (0<<28) -#define M860_SI_SMC2_CLK6 (1<<28) -#define M860_SI_SMC2_CLK7 (2<<28) -#define M860_SI_SMC2_CLK8 (3<<28) -#define M860_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M860_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M860_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M860_SI_SMC1_BRG2 (1<<12) -#define M860_SI_SMC1_BRG3 (2<<12) -#define M860_SI_SMC1_BRG4 (3<<12) -#define M860_SI_SMC1_CLK1 (0<<12) -#define M860_SI_SMC1_CLK2 (1<<12) -#define M860_SI_SMC1_CLK3 (2<<12) -#define M860_SI_SMC1_CLK4 (3<<12) - -/* -************************************************************************* -* SDMA Configuration Register (SDCR) * -************************************************************************* -*/ -#define M860_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M860_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ - -/* -************************************************************************* -* SDMA Status Register (SDSR) * -************************************************************************* -*/ -#define M860_SDSR_SBER (1<<7) /* SDMA Channel bus error */ -#define M860_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ -#define M860_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ - -/* -************************************************************************* -* Baud (sic) Rate Generators * -************************************************************************* -*/ -#define M860_BRG_RST (1<<17) /* Reset generator */ -#define M860_BRG_EN (1<<16) /* Enable generator */ -#define M860_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M860_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M860_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M860_BRG_ATB (1<<13) /* Autobaud */ -#define M860_BRG_115200 (21<<1) /* Assume 40 MHz clock */ -#define M860_BRG_57600 (32<<1) -#define M860_BRG_38400 (64<<1) -#define M860_BRG_19200 (129<<1) -#define M860_BRG_9600 (259<<1) -#define M860_BRG_4800 (520<<1) -#define M860_BRG_2400 (1040<<1) -#define M860_BRG_1200 (2082<<1) -#define M860_BRG_600 ((259<<1) | 1) -#define M860_BRG_300 ((520<<1) | 1) -#define M860_BRG_150 ((1040<<1) | 1) -#define M860_BRG_75 ((2080<<1) | 1) - -#define M860_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ -#define M860_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ -#define M860_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ -#define M860_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ -#define M860_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ -#define M860_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ -#define M860_TGCR_STP1 (1<<1) /* Stop timer */ -#define M860_TGCR_STP2 (1<<5) /* Stop timer */ -#define M860_TGCR_STP3 (1<<9) /* Stop timer */ -#define M860_TGCR_STP4 (1<<13) /* Stop timer */ -#define M860_TGCR_RST1 (1<<0) /* Enable timer */ -#define M860_TGCR_RST2 (1<<4) /* Enable timer */ -#define M860_TGCR_RST3 (1<<8) /* Enable timer */ -#define M860_TGCR_RST4 (1<<12) /* Enable timer */ -#define M860_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ -#define M860_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ - -#define M860_TMR_PS(x) ((x)<<8) /* Timer prescaler */ -#define M860_TMR_CE_RISE (1<<6) /* Capture on rising edge */ -#define M860_TMR_CE_FALL (2<<6) /* Capture on falling edge */ -#define M860_TMR_CE_ANY (3<<6) /* Capture on any edge */ -#define M860_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ -#define M860_TMR_ORI (1<<4) /* Interrupt on reaching reference */ -#define M860_TMR_RESTART (1<<3) /* Restart timer after reference */ -#define M860_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ -#define M860_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ -#define M860_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ -#define M860_TMR_TGATE (1<<0) /* TGATE controls timer */ - -#define M860_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ -#define M860_PISCR_PS (1<<7) /* PIT Interrupt state */ -#define M860_PISCR_PIE (1<<2) /* PIT interrupt enable */ -#define M860_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ -#define M860_PISCR_PTE (1<<0) /* PIT enable */ - -#define M860_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ -#define M860_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ -#define M860_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ -#define M860_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ -#define M860_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ -#define M860_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ -#define M860_TBSCR_TBE (1<<0) /* enable TB and decrementer */ - -#define M860_SIMASK_IRM0 (1<<31) -#define M860_SIMASK_LVM0 (1<<30) -#define M860_SIMASK_IRM1 (1<<29) -#define M860_SIMASK_LVM1 (1<<28) -#define M860_SIMASK_IRM2 (1<<27) -#define M860_SIMASK_LVM2 (1<<26) -#define M860_SIMASK_IRM3 (1<<25) -#define M860_SIMASK_LVM3 (1<<24) -#define M860_SIMASK_IRM4 (1<<23) -#define M860_SIMASK_LVM4 (1<<22) -#define M860_SIMASK_IRM5 (1<<21) -#define M860_SIMASK_LVM5 (1<<20) -#define M860_SIMASK_IRM6 (1<<19) -#define M860_SIMASK_LVM6 (1<<18) -#define M860_SIMASK_IRM7 (1<<17) -#define M860_SIMASK_LVM7 (1<<16) - -#define M860_SIUMCR_EARB (1<<31) -#define M860_SIUMCR_EARP0 (0<<28) -#define M860_SIUMCR_EARP1 (1<<28) -#define M860_SIUMCR_EARP2 (2<<28) -#define M860_SIUMCR_EARP3 (3<<28) -#define M860_SIUMCR_EARP4 (4<<28) -#define M860_SIUMCR_EARP5 (5<<28) -#define M860_SIUMCR_EARP6 (6<<28) -#define M860_SIUMCR_EARP7 (7<<28) -#define M860_SIUMCR_DSHW (1<<23) -#define M860_SIUMCR_DBGC0 (0<<21) -#define M860_SIUMCR_DBGC1 (1<<21) -#define M860_SIUMCR_DBGC2 (2<<21) -#define M860_SIUMCR_DBGC3 (3<<21) -#define M860_SIUMCR_DBPC0 (0<<19) -#define M860_SIUMCR_DBPC1 (1<<19) -#define M860_SIUMCR_DBPC2 (2<<19) -#define M860_SIUMCR_DBPC3 (3<<19) -#define M860_SIUMCR_FRC (1<<17) -#define M860_SIUMCR_DLK (1<<16) -#define M860_SIUMCR_PNCS (1<<15) -#define M860_SIUMCR_OPAR (1<<14) -#define M860_SIUMCR_DPC (1<<13) -#define M860_SIUMCR_MPRE (1<<12) -#define M860_SIUMCR_MLRC0 (0<<10) -#define M860_SIUMCR_MLRC1 (1<<10) -#define M860_SIUMCR_MLRC2 (2<<10) -#define M860_SIUMCR_MLRC3 (3<<10) -#define M860_SIUMCR_AEME (1<<9) -#define M860_SIUMCR_SEME (1<<8) -#define M860_SIUMCR_BSC (1<<7) -#define M860_SIUMCR_GB5E (1<<6) -#define M860_SIUMCR_B2DD (1<<5) -#define M860_SIUMCR_B3DD (1<<4) -/* -************************************************************************* -* MPC860 DUAL-PORT RAM AND REGISTERS * -************************************************************************* -*/ -typedef struct m860_ { - - /* - * SIU Block - */ - rtems_unsigned32 siumcr; - rtems_unsigned32 sypcr; - rtems_unsigned32 swt; - rtems_unsigned16 _pad0; - rtems_unsigned16 swsr; - rtems_unsigned32 sipend; - rtems_unsigned32 simask; - rtems_unsigned32 siel; - rtems_unsigned32 sivec; - rtems_unsigned32 tesr; - rtems_unsigned32 _pad1[3]; - rtems_unsigned32 sdcr; - rtems_unsigned8 _pad2[0x80-0x34]; - - /* - * PCMCIA Block - */ - rtems_unsigned32 pbr0; - rtems_unsigned32 por0; - rtems_unsigned32 pbr1; - rtems_unsigned32 por1; - rtems_unsigned32 pbr2; - rtems_unsigned32 por2; - rtems_unsigned32 pbr3; - rtems_unsigned32 por3; - rtems_unsigned32 pbr4; - rtems_unsigned32 por4; - rtems_unsigned32 pbr5; - rtems_unsigned32 por5; - rtems_unsigned32 pbr6; - rtems_unsigned32 por6; - rtems_unsigned32 pbr7; - rtems_unsigned32 por7; - rtems_unsigned8 _pad3[0xe0-0xc0]; - rtems_unsigned32 pgcra; - rtems_unsigned32 pgcrb; - rtems_unsigned32 pscr; - rtems_unsigned32 _pad4; - rtems_unsigned32 pipr; - rtems_unsigned32 _pad5; - rtems_unsigned32 per; - rtems_unsigned32 _pad6; - - /* - * MEMC Block - */ - m860MEMCRegisters_t memc[8]; - rtems_unsigned8 _pad7[0x164-0x140]; - rtems_unsigned32 mar; - rtems_unsigned32 mcr; - rtems_unsigned32 _pad8; - rtems_unsigned32 mamr; - rtems_unsigned32 mbmr; - rtems_unsigned16 mstat; - rtems_unsigned16 mptpr; - rtems_unsigned32 mdr; - rtems_unsigned8 _pad9[0x200-0x180]; - - /* - * System integration timers - */ - rtems_unsigned16 tbscr; - rtems_unsigned16 _pad10; - rtems_unsigned32 tbreff0; - rtems_unsigned32 tbreff1; - rtems_unsigned8 _pad11[0x220-0x20c]; - rtems_unsigned16 rtcsc; - rtems_unsigned16 _pad12; - rtems_unsigned32 rtc; - rtems_unsigned32 rtsec; - rtems_unsigned32 rtcal; - rtems_unsigned32 _pad13[4]; - rtems_unsigned16 piscr; - rtems_unsigned16 _pad14; - rtems_unsigned16 pitc; - rtems_unsigned16 _pad_14_1; - rtems_unsigned16 pitr; - rtems_unsigned16 _pad_14_2; - rtems_unsigned8 _pad15[0x280-0x24c]; - - - /* - * Clocks and Reset - */ - rtems_unsigned32 sccr; - rtems_unsigned32 plprcr; - rtems_unsigned32 rsr; - rtems_unsigned8 _pad16[0x300-0x28c]; - - - /* - * System integration timers keys - */ - rtems_unsigned32 tbscrk; - rtems_unsigned32 tbreff0k; - rtems_unsigned32 tbreff1k; - rtems_unsigned32 tbk; - rtems_unsigned32 _pad17[4]; - rtems_unsigned32 rtcsk; - rtems_unsigned32 rtck; - rtems_unsigned32 rtseck; - rtems_unsigned32 rtcalk; - rtems_unsigned32 _pad18[4]; - rtems_unsigned32 piscrk; - rtems_unsigned32 pitck; - rtems_unsigned8 _pad19[0x380-0x348]; - - /* - * Clocks and Reset Keys - */ - rtems_unsigned32 sccrk; - rtems_unsigned32 plprck; - rtems_unsigned32 rsrk; - rtems_unsigned8 _pad20[0x400-0x38c]; - rtems_unsigned8 _pad21[0x800-0x400]; - rtems_unsigned8 _pad22[0x860-0x800]; - - - /* - * I2C - */ - rtems_unsigned8 i2mod; - rtems_unsigned8 _pad23[3]; - rtems_unsigned8 i2add; - rtems_unsigned8 _pad24[3]; - rtems_unsigned8 i2brg; - rtems_unsigned8 _pad25[3]; - rtems_unsigned8 i2com; - rtems_unsigned8 _pad26[3]; - rtems_unsigned8 i2cer; - rtems_unsigned8 _pad27[3]; - rtems_unsigned8 i2cmr; - rtems_unsigned8 _pad28[0x900-0x875]; - - /* - * DMA Block - */ - rtems_unsigned32 _pad29; - rtems_unsigned32 sdar; - rtems_unsigned8 sdsr; - rtems_unsigned8 _pad30[3]; - rtems_unsigned8 sdmr; - rtems_unsigned8 _pad31[3]; - rtems_unsigned8 idsr1; - rtems_unsigned8 _pad32[3]; - rtems_unsigned8 idmr1; - rtems_unsigned8 _pad33[3]; - rtems_unsigned8 idsr2; - rtems_unsigned8 _pad34[3]; - rtems_unsigned8 idmr2; - rtems_unsigned8 _pad35[0x930-0x91d]; - - - - /* - * CPM Interrupt Control Block - */ - rtems_unsigned16 civr; - rtems_unsigned8 _pad36[14]; - rtems_unsigned32 cicr; - rtems_unsigned32 cipr; - rtems_unsigned32 cimr; - rtems_unsigned32 cisr; - - /* - * I/O Port Block - */ - rtems_unsigned16 padir; - rtems_unsigned16 papar; - rtems_unsigned16 paodr; - rtems_unsigned16 padat; - rtems_unsigned8 _pad37[8]; - rtems_unsigned16 pcdir; - rtems_unsigned16 pcpar; - rtems_unsigned16 pcso; - rtems_unsigned16 pcdat; - rtems_unsigned16 pcint; - rtems_unsigned8 _pad39[6]; - rtems_unsigned16 pddir; - rtems_unsigned16 pdpar; - rtems_unsigned16 _pad40; - rtems_unsigned16 pddat; - rtems_unsigned8 _pad41[8]; - - /* - * CPM Timers Block - */ - rtems_unsigned16 tgcr; - rtems_unsigned8 _pad42[14]; - rtems_unsigned16 tmr1; - rtems_unsigned16 tmr2; - rtems_unsigned16 trr1; - rtems_unsigned16 trr2; - rtems_unsigned16 tcr1; - rtems_unsigned16 tcr2; - rtems_unsigned16 tcn1; - rtems_unsigned16 tcn2; - rtems_unsigned16 tmr3; - rtems_unsigned16 tmr4; - rtems_unsigned16 trr3; - rtems_unsigned16 trr4; - rtems_unsigned16 tcr3; - rtems_unsigned16 tcr4; - rtems_unsigned16 tcn3; - rtems_unsigned16 tcn4; - rtems_unsigned16 ter1; - rtems_unsigned16 ter2; - rtems_unsigned16 ter3; - rtems_unsigned16 ter4; - rtems_unsigned8 _pad43[8]; - - - - /* - * CPM Block - */ - rtems_unsigned16 cpcr; - rtems_unsigned16 _pad44; - rtems_unsigned16 rccr; - rtems_unsigned8 _pad45; - rtems_unsigned8 rmds; - rtems_unsigned32 rmdr; - rtems_unsigned16 rctr1; - rtems_unsigned16 rctr2; - rtems_unsigned16 rctr3; - rtems_unsigned16 rctr4; - rtems_unsigned16 _pad46; - rtems_unsigned16 rter; - rtems_unsigned16 _pad47; - rtems_unsigned16 rtmr; - rtems_unsigned8 _pad48[0x9f0-0x9dc]; - - /* - * BRG Block - */ - rtems_unsigned32 brgc1; - rtems_unsigned32 brgc2; - rtems_unsigned32 brgc3; - rtems_unsigned32 brgc4; - - /* - * SCC Block - */ - m860SCCRegisters_t scc1; - m860SCCRegisters_t scc2; - m860SCCRegisters_t scc3; - m860SCCRegisters_t scc4; - - /* - * SMC Block - */ - m860SMCRegisters_t smc1; - m860SMCRegisters_t smc2; - - /* - * SPI Block - */ - rtems_unsigned16 spmode; - rtems_unsigned16 _pad49[2]; - rtems_unsigned8 spie; - rtems_unsigned8 _pad50; - rtems_unsigned16 _pad51; - rtems_unsigned8 spim; - rtems_unsigned8 _pad52[2]; - rtems_unsigned8 spcom; - rtems_unsigned16 _pad53[2]; - - /* - * PIP Block - */ - rtems_unsigned16 pipc; - rtems_unsigned16 _pad54; - rtems_unsigned16 ptpr; - rtems_unsigned32 pbdir; - rtems_unsigned32 pbpar; - rtems_unsigned16 _pad55; - rtems_unsigned16 pbodr; - rtems_unsigned32 pbdat; - rtems_unsigned32 _pad56[6]; - - /* - * SI Block - */ - rtems_unsigned32 simode; - rtems_unsigned8 sigmr; - rtems_unsigned8 _pad57; - rtems_unsigned8 sistr; - rtems_unsigned8 sicmr; - rtems_unsigned32 _pad58; - rtems_unsigned32 sicr; - rtems_unsigned16 sirp[2]; - rtems_unsigned32 _pad59[3]; - rtems_unsigned8 _pad60[0xc00-0xb00]; - rtems_unsigned8 siram[512]; - - /* - * This is only used on the MPC860T - for the Fast Ethernet Controller (FEC) - */ - m860FECRegisters_t fec; - - rtems_unsigned8 _pad62[0x2000-0x1000]; - /* - * Dual-port RAM - */ - rtems_unsigned8 dpram0[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram1[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram2[0x400]; /* BD/DATA/UCODE */ - rtems_unsigned8 dpram3[0x600]; /* BD/DATA*/ - rtems_unsigned8 dpram4[0x200]; /* BD/DATA/UCODE */ - rtems_unsigned8 _pad63[0x3c00-0x3000]; - - /* When using SCC1 for ethernet, we lose the use of I2C since - * their parameters would overlap. Motorola has a microcode - * patch to move parameters around so that both can be used - * together. It is available on their web site somewhere - * under http://www.mot.com/mpc860. If ethernet is used on - * one (or more) of the other SCCs, then other CPM features - * will be unavailable: - * SCC2 -> lose SPI - * SCC3 -> lose SMC1 - * SCC4 -> lose SMC2 - */ - m860SCCENparms_t scc1p; - rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m860SCCENparms_t)]; - m860MiscParms_t miscp; - rtems_unsigned8 _rsv2[0xcc0-0xCB0-sizeof(m860MiscParms_t)]; - m860IDMAparms_t idma1p; - rtems_unsigned8 _rsv3[0xd00-0xcc0-sizeof(m860IDMAparms_t)]; - - m860SCCparms_t scc2p; - rtems_unsigned8 _rsv4[0xD80-0xD00-sizeof(m860SCCparms_t)]; - m860SPIparms_t spip; - rtems_unsigned8 _rsv5[0xDB0-0xD80-sizeof(m860SPIparms_t)]; - m860TimerParms_t tmp; - rtems_unsigned8 _rsv6[0xDC0-0xDB0-sizeof(m860TimerParms_t)]; - m860IDMAparms_t idma2p; - rtems_unsigned8 _rsv7[0xE00-0xDC0-sizeof(m860IDMAparms_t)]; - - m860SCCparms_t scc3p; - rtems_unsigned8 _rsv8[0xE80-0xE00-sizeof(m860SCCparms_t)]; - m860SMCparms_t smc1p; - rtems_unsigned8 _rsv9[0xEC0-0xE80-sizeof(m860SMCparms_t)]; - m860DSPparms_t dsp1p; - rtems_unsigned8 _rsv10[0xF00-0xEC0-sizeof(m860DSPparms_t)]; - - m860SCCparms_t scc4p; - rtems_unsigned8 _rsv11[0xF80-0xF00-sizeof(m860SCCparms_t)]; - m860SMCparms_t smc2p; - rtems_unsigned8 _rsv12[0xFC0-0xF80-sizeof(m860SMCparms_t)]; - m860DSPparms_t dsp2p; - rtems_unsigned8 _rsv13[0x1000-0xFC0-sizeof(m860DSPparms_t)]; -} m860_t; - -extern volatile m860_t m860; -#endif /* ASM */ - -#endif /* __MPC860_h */ diff --git a/c/src/lib/libcpu/powerpc/mpc860/timer/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/timer/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/timer/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.am deleted file mode 100644 index 65edc98d9f..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.am +++ /dev/null @@ -1,29 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -PGM = $(ARCH)/timer.rel - -C_FILES = timer.c - -timer_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(timer_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(timer_rel_OBJECTS) $(PGM) - -.PRECIOUS: $(PGM) - -EXTRA_DIST = timer.c - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c deleted file mode 100644 index d5cb561c48..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c +++ /dev/null @@ -1,100 +0,0 @@ -/* timer.c - * - * This file manages the interval timer on the PowerPC MPC860. - * NOTE: This is not the PIT, but rather the RTEMS interval - * timer - * We shall use the bottom 32 bits of the timebase register, - * - * The following was in the 403 version of this file. I don't - * know what it means. JTM 5/19/98 - * NOTE: It is important that the timer start/stop overhead be - * determined when porting or modifying this code. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * Copywright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/timer/timer.c: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libcpu/hppa1_1/timer/timer.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <mpc860.h> - -static volatile rtems_unsigned32 Timer_starting; -static rtems_boolean Timer_driver_Find_average_overhead; - -/* - * This is so small that this code will be reproduced where needed. - */ -static inline rtems_unsigned32 get_itimer(void) -{ - rtems_unsigned32 ret; - - asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */ - - return ret; -} - -void Timer_initialize(void) -{ - /* set interrupt level and enable timebase. This should never */ - /* generate an interrupt however. */ - m860.tbscr |= M860_TBSCR_TBIRQ(4) | M860_TBSCR_TBE; - - Timer_starting = get_itimer(); -} - -int Read_timer(void) -{ - rtems_unsigned32 clicks; - rtems_unsigned32 total; - - clicks = get_itimer(); - - total = clicks - Timer_starting; - - if ( Timer_driver_Find_average_overhead == 1 ) - return total; /* in XXX microsecond units */ - - else { - if ( total < rtems_cpu_configuration_get_timer_least_valid() ) { - return 0; /* below timer resolution */ - } - return (total - rtems_cpu_configuration_get_timer_average_overhead()); - } -} - -rtems_status_code Empty_function(void) -{ - return RTEMS_SUCCESSFUL; -} - -void Set_find_average_overhead(rtems_boolean find_flag) -{ - Timer_driver_Find_average_overhead = find_flag; -} diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/.cvsignore b/c/src/lib/libcpu/powerpc/mpc860/vectors/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/vectors/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.am b/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.am deleted file mode 100644 index 8d8bce2c1d..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.am +++ /dev/null @@ -1,32 +0,0 @@ -## -## $Id$ -## - -AUTOMAKE_OPTIONS = foreign 1.4 - -VPATH = @srcdir@:@srcdir@/../../ppc403/vectors - -## FIXME - -PGM = ${ARCH}/vectors.rel - -## Assembly sources -S_FILES = vectors.S align_h.S - -vectors_rel_OBJECTS = $(S_FILES:%.S=${ARCH}/%.o) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(top_srcdir)/../../../../../automake/lib.am - -# -# (OPTIONAL) Add local stuff here using += -# - -$(PGM): $(vectors_rel_OBJECTS) - $(make-rel) - -all-local: ${ARCH} $(PGM) - -EXTRA_DIST = vectors.S README - -include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/README b/c/src/lib/libcpu/powerpc/mpc860/vectors/README deleted file mode 100644 index 536e221f43..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/vectors/README +++ /dev/null @@ -1,20 +0,0 @@ -# -# $Id$ -# - -The location of the vectors file object is critical. - -From the comments at the head of vectors.s: - - The issue with this file is getting it loaded at the right place. - The first vector MUST be at address 0x????0100. - How this is achieved is dependant on the tool chain. - -... - - The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - offset from 0x????0000 to the first location in the file. This - will be either 0x0000 or 0xfff0. - -The eth_comm BSP defines PPC_VECTOR_FILE_BASE to be 0x00000000 - diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S deleted file mode 100644 index 5bb5ea526b..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S +++ /dev/null @@ -1,952 +0,0 @@ -/* vectors.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC MPC860 - * interrupt veneers for RTEMS. - * - * Author: Jay Monkman (jmonkman@frasca.com) - * - * Copyright (C) 1998 by Frasca International, Inc. - * - * Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s: - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - */ - -/* - * The issue with this file is getting it loaded at the right place. - * The first vector MUST be at address 0x????0100. - * How this is achieved is dependant on the tool chain. - * - * However the basic mechanism for ELF assemblers is to create a - * section called ".vectors", which will be loaded to an address - * between 0x????0000 and 0x????0100 (inclusive) via a link script. - * - * The basic mechanism for XCOFF assemblers is to place it in the - * normal text section, and arrange for this file to be located - * at an appropriate position on the linker command line. - * - * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - * offset from 0x????0000 to the first location in the file. This - * will be either 0x0000 or 0xfff0. - * - * $Id$ - */ - -#include "asm.h" -#include <mpc860.h> - -#ifndef PPC_VECTOR_FILE_BASE -#error "PPC_VECTOR_FILE_BASE is not defined." -#endif - - /* Where this file will be loaded */ - .set file_base, PPC_VECTOR_FILE_BASE - - /* Offset to store reg 0 */ - - .set IP_LINK, 0 -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - .set IP_0, (IP_LINK + 56) -#else - .set IP_0, (IP_LINK + 8) -#endif - .set IP_2, (IP_0 + 4) - - .set IP_3, (IP_2 + 4) - .set IP_4, (IP_3 + 4) - .set IP_5, (IP_4 + 4) - .set IP_6, (IP_5 + 4) - - .set IP_7, (IP_6 + 4) - .set IP_8, (IP_7 + 4) - .set IP_9, (IP_8 + 4) - .set IP_10, (IP_9 + 4) - - .set IP_11, (IP_10 + 4) - .set IP_12, (IP_11 + 4) - .set IP_13, (IP_12 + 4) - .set IP_28, (IP_13 + 4) - - .set IP_29, (IP_28 + 4) - .set IP_30, (IP_29 + 4) - .set IP_31, (IP_30 + 4) - .set IP_CR, (IP_31 + 4) - - .set IP_CTR, (IP_CR + 4) - .set IP_XER, (IP_CTR + 4) - .set IP_LR, (IP_XER + 4) - .set IP_PC, (IP_LR + 4) - - .set IP_MSR, (IP_PC + 4) - - .set IP_END, (IP_MSR + 16) - - /* Vector offsets */ - .set begin_vector, 0x0000 - .set reset_vector, 0x0100 - .set mach_vector, 0x0200 - .set dsi_vector, 0x0300 - .set isi_vector, 0x0400 - .set ext_vector, 0x0500 - .set align_vector, 0x0600 - .set prog_vector, 0x0700 - .set float_vector, 0x0800 - .set dec_vector, 0x0900 - .set sys_vector, 0x0C00 - .set trace_vector, 0x0d00 - .set syscall_vector, 0x0c00 - .set fpassist_vector, 0x0e00 - .set software_vector, 0x1000 - .set itlbm_vector, 0x1100 - .set dtlbm_vector, 0x1200 - .set itlbe_vector, 0x1300 - .set dtlbe_vector, 0x1400 - .set databkpt_vector, 0x1c00 - .set insbkpt_vector, 0x1d00 - .set perbkpt_vector, 0x1e00 - .set dev_vector, 0x1f00 - .set siu_vector, 0x2000 - .set cpm_vector, 0x2400 - -/* Go to the right section */ -#if PPC_ASM == PPC_ASM_ELF - .section .vectors,"awx",@progbits -#elif PPC_ASM == PPC_ASM_XCOFF - .csect .text[PR] -#endif - - PUBLIC_VAR (__vectors) -SYM (__vectors): - -/* Critical error handling */ - .org reset_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_SYSTEM_RESET - b PROC (_ISR_Handler) - -/* Machine check exception */ - .org mach_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_MCHECK - b PROC (_ISR_Handler) - -/* Protection exception */ - .org dsi_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROTECT - b PROC (_ISR_Handler) - -/* Instruction Storage exception */ - .org isi_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_ISI - b PROC (_ISR_Handler) - -/* External interrupt */ -/* When an external interrupt occurs, we must find out what caused it */ -/* before calling the RTEMS handler. First we use SIVEC to decide */ -/* what signalled the interrupt to the SIU. */ - .org ext_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - stw r9, IP_9(r1) /* r9 will be restored in the next level */ - stw r10, IP_10(r1) - - lis r9, m860@ha - addi r9, r9, m860@l - lbz r10, 0x1c(r9) /* SIVEC */ - rlwinm r10, r10, 4, 0, 27 /* each psuedo vector will have */ - /* room for 16 instructions */ - addis r10, r10, siu_vectors@ha - addi r10, r10, siu_vectors@l - mflr r0 - mtlr r10 - lwz r10, IP_10(r1) - blr - -/* Align exception */ - .org align_vector - file_base - .extern align_h - b align_h - -/* Program exception */ - .org prog_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROGRAM - b PROC (_ISR_Handler) - -/* Float exception */ - .org float_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_NOFP - b PROC (_ISR_Handler) - -/* Decrementer exception */ - .org dec_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_PROGRAM - b PROC (_ISR_Handler) - -/* System call */ - .org sys_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_SCALL - b PROC (_ISR_Handler) - -/* Trace interrupt */ - .org trace_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_TRACE - b PROC (_ISR_Handler) - - .org itlbm_vector - file_base -itlbm_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org dtlbm_vector - file_base -dtlbm_vectors: - mfspr r1, 0x1a - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - lis r3, 0x400 - mtspr 792, r3 - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mtspr 824, r18 - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org itlbe_vector - file_base -itlbe_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - .org dtlbe_vector - file_base -dtlbe_vectors: - mfspr r2, 784 /* MI_CTR */ - mfspr r3, 792 /* MD_CTR */ - mfspr r4, 787 /* MI_EPN */ - mfspr r5, 789 /* MI_TWC */ - mfspr r6, 797 /* MD_TWC */ - mfspr r7, 789 /* MI_TWC */ - mfspr r8, 790 /* MI_RPN */ - mfspr r9, 798 /* MD_RPN */ - mfspr r10, 796 /* M_TWB */ - mfspr r11, 793 /* M_CASID */ - mfspr r12, 786 /* MI_AP */ - mfspr r13, 794 /* MD_AP */ - mfspr r14, 799 /* M_TW */ - mfspr r15, 816 /* MI_CAM */ - mfspr r16, 817 /* MI_RAM0 */ - mfspr r17, 818 /* MI_RAM1 */ - mfspr r18, 824 /* MD_CAM */ - mfspr r19, 825 /* M_RAM0 */ - mfspr r20, 826 /* M_RAM1 */ - .long 0 - - - -/* Now we look at what signaled the interrupt to the SIU. */ -/* I needed to do this in order to decode the CPM interrupts before */ -/* calling _ISR_Handler */ - -/* *IRQ0 */ - .org siu_vector - file_base -siu_vectors: - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ0 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 0 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL0 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ1 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* This is probably not the "correct" way to do this. I need to have a - * way of calling _ISR_Handler for the CPM interrupts and this is the - * simplest way I can think of. Since I have the CPM interrupt mapped - * to the SIU interrupt level 1 on the eth-comm board, I put it here. - * It would probably be ok if I moved this directory to under libbsp - * instead of libcpu. For now, deal with it. -*/ -/* Level 1 - CPM */ -/* Now we need to get the CPM interrupt vector */ - /* Registers: */ - /* R0 - has stored value of LR */ - /* R9 - pointer to m860 struct */ - /* R10 has already been saved and restored */ - li r10, 1 - sth r10, 0x930(r9) /* CIVR */ - lbz r10, 0x930(r9) /* if we use this as an offset into a */ - rlwinm r10, r10, 1, 0, 31 /* table, each entry will have room */ - /* 4 instructions. */ - addis r10, r10, cpm_vectors@ha - addi r10, r10, cpm_vectors@l - - mtlr r10 - lwz r10, IP_10(r1) - blr - - nop - nop - nop - nop - nop - nop - nop - -#if 0 -/* Level 1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL1 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -#endif - -/* *IRQ2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ2 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL2 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ3 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL3 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ4 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL4 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ5 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL5 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ6 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL6 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* *IRQ7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_IRQ7 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - -/* Level 7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_LVL7 - b PROC (_ISR_Handler) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - -/* .org cpm_vector - file_base*/ -cpm_vectors: - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_0 - .long 0 - - /* PC4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC4 - b PROC (_ISR_Handler) - - /* PC5 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC5 - b PROC (_ISR_Handler) - - /* SMC2 / PIP */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SMC2 - b PROC (_ISR_Handler) - - /* SMC1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SMC1 - b PROC (_ISR_Handler) - - /* SPI */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SPI - b PROC (_ISR_Handler) - - /* PC6 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC6 - b PROC (_ISR_Handler) - - /* Timer 4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER4 - b PROC (_ISR_Handler) - - /* Reserved - we should never see this */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_8 - .long 0 - - /* PC7 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC7 - b PROC (_ISR_Handler) - - /* PC8 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC8 - b PROC (_ISR_Handler) - - /* PC9 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC9 - b PROC (_ISR_Handler) - - /* Timer 3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER3 - b PROC (_ISR_Handler) - - /* Reserved - we should never get here */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_D - .long 0 - - /* PC10 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC10 - b PROC (_ISR_Handler) - - /* PC11 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC11 - b PROC (_ISR_Handler) - - /* I2C */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_I2C - b PROC (_ISR_Handler) - - /* RISC Timer Table */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RISC_TIMER - b PROC (_ISR_Handler) - - /* Timer 2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER2 - b PROC (_ISR_Handler) - - /* Reserved - we should never get here */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_RESERVED_13 - .long 0 - - /* IDMA2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_IDMA2 - b PROC (_ISR_Handler) - - /* IDMA1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_IDMA1 - b PROC (_ISR_Handler) - - /* SDMA Channel Bus Error */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SDMA_ERROR - b PROC (_ISR_Handler) - - /* PC12 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC12 - b PROC (_ISR_Handler) - - /* PC13 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC13 - b PROC (_ISR_Handler) - - /* Timer 1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_TIMER1 - b PROC (_ISR_Handler) - - /* PC14 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC14 - b PROC (_ISR_Handler) - - /* SCC4 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC4 - b PROC (_ISR_Handler) - - /* SCC3 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC3 - b PROC (_ISR_Handler) - - /* SCC2 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC2 - b PROC (_ISR_Handler) - - /* SCC1 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_SCC1 - b PROC (_ISR_Handler) - - /* PC15 */ - mtlr r0 - lwz r9, IP_9(r1) - li r0, PPC_IRQ_CPM_PC15 - b PROC (_ISR_Handler) - - - |