diff options
| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 05:09:41 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2009-11-30 05:09:41 +0000 |
| commit | 359e5374164ccb2a66833354b412a859c144ea2f (patch) | |
| tree | 6f065d7d6247bc255f43ddb0152fc26c50bd4f87 /c/src/lib/libcpu | |
| parent | Whitespace removal. (diff) | |
| download | rtems-359e5374164ccb2a66833354b412a859c144ea2f.tar.bz2 | |
Whitespace removal.
Diffstat (limited to '')
172 files changed, 1581 insertions, 1581 deletions
diff --git a/c/src/lib/libcpu/arm/at91rm9200/clock/clock.c b/c/src/lib/libcpu/arm/at91rm9200/clock/clock.c index 04b3f4f96f..7a9cf6af07 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/clock/clock.c +++ b/c/src/lib/libcpu/arm/at91rm9200/clock/clock.c @@ -34,7 +34,7 @@ static unsigned long st_pimr_reload; static void clock_isr_on(const rtems_irq_connect_data *unused) { /* enable timer interrupt */ - ST_REG(ST_IER) = ST_SR_PITS; + ST_REG(ST_IER) = ST_SR_PITS; } /** @@ -58,13 +58,13 @@ static void clock_isr_off(const rtems_irq_connect_data *unused) static int clock_isr_is_on(const rtems_irq_connect_data *irq) { /* check timer interrupt */ - return ST_REG(ST_IMR) & ST_SR_PITS; + return ST_REG(ST_IMR) & ST_SR_PITS; } rtems_isr Clock_isr(rtems_vector_number vector); /* Replace the first value with the clock's interrupt name. */ -rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ, +rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ, (rtems_irq_hdl)Clock_isr, clock_isr_on, clock_isr_off, @@ -88,11 +88,11 @@ void Clock_driver_support_initialize_hardware(void) (((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000); st_pimr_reload = st_pimr_value; - /* read the status to clear the int */ + /* read the status to clear the int */ st_str = ST_REG(ST_SR); - + /* set priority */ - AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); + AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); /* set the timer value */ ST_REG(ST_PIMR) = st_pimr_reload; diff --git a/c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c b/c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c index 7faabab5a1..4dbd16e536 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c +++ b/c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c @@ -1,7 +1,7 @@ /* * Console driver for AT91RM9200 DBGU port * - * This driver uses the shared console driver in + * This driver uses the shared console driver in * ...../libbsp/shared/console.c * * Copyright (c) 2003 by Cogent Computer Systems @@ -38,8 +38,8 @@ static void dbgu_write_polled(int minor, char c); static int dbgu_set_attributes(int minor, const struct termios *t); /* Pointers to functions for handling the UART. */ -console_fns dbgu_fns = -{ +console_fns dbgu_fns = +{ libchip_serial_default_probe, dbgu_first_open, dbgu_last_close, @@ -54,23 +54,23 @@ console_fns dbgu_fns = /* Functions called via callbacks (i.e. the ones in uart_fns */ /*********************************************************************/ -/* +/* * This is called the first time each device is opened. Since - * the driver is polled, we don't have to do anything. If the driver - * were interrupt driven, we'd enable interrupts here. + * the driver is polled, we don't have to do anything. If the driver + * were interrupt driven, we'd enable interrupts here. */ -static int dbgu_first_open(int major, int minor, void *arg) +static int dbgu_first_open(int major, int minor, void *arg) { return 0; } -/* +/* * This is called the last time each device is closed. Since - * the driver is polled, we don't have to do anything. If the driver - * were interrupt driven, we'd disable interrupts here. + * the driver is polled, we don't have to do anything. If the driver + * were interrupt driven, we'd disable interrupts here. */ -static int dbgu_last_close(int major, int minor, void *arg) +static int dbgu_last_close(int major, int minor, void *arg) { return 0; } @@ -82,7 +82,7 @@ static int dbgu_last_close(int major, int minor, void *arg) * return -1 if there's no data, otherwise return * the character in lowest 8 bits of returned int. */ -static int dbgu_read(int minor) +static int dbgu_read(int minor) { char c; console_tbl *console_entry; @@ -99,15 +99,15 @@ static int dbgu_read(int minor) if (!(dbgu->sr & DBGU_INT_RXRDY)) { return -1; } - - c = dbgu->rhr & 0xff; - + + c = dbgu->rhr & 0xff; + return c; } -/* - * Write buffer to UART +/* + * Write buffer to UART * * return 1 on success, -1 on error */ @@ -133,17 +133,17 @@ static int dbgu_write(int minor, const char *buf, int len) break; } } - + c = (char) buf[i]; dbgu->thr = c; - + /* the TXRDY flag does not seem to update right away (is this true?) */ /* so we wait a bit before continuing */ for (x = 0; x < 100; x++) { dbg_dly++; /* using a global so this doesn't get optimized out */ } } - + return 1; } @@ -186,7 +186,7 @@ static void dbgu_write_polled(int minor, char c) } /* This is for setting baud rate, bits, etc. */ -static int dbgu_set_attributes(int minor, const struct termios *t) +static int dbgu_set_attributes(int minor, const struct termios *t) { return 0; } @@ -197,7 +197,7 @@ static int dbgu_set_attributes(int minor, const struct termios *t) * functions use them instead. */ /***********************************************************************/ -/* +/* * Read from UART. This is used in the exit code, and can't * rely on interrupts. */ @@ -208,7 +208,7 @@ int dbgu_poll_read(int minor) /* - * Write a character to the console. This is used by printk() and + * Write a character to the console. This is used by printk() and * maybe other low level functions. It should not use interrupts or any * RTEMS system calls. It needs to be very simple */ diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h index 99346dbaa0..88825452d5 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h @@ -32,7 +32,7 @@ typedef volatile unsigned long vulong; #define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) /* Control Register - 32 of them */ -#define AIC_CTL_BASE 0xFFFFF100 +#define AIC_CTL_BASE 0xFFFFF100 #define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) /* Register Offsets */ @@ -103,9 +103,9 @@ typedef volatile unsigned long vulong; /* AIC_SMR */ #define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) #define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ -#define AIC_SMR_SRC_EDGE_LOW (1 << 5) -#define AIC_SMR_SRC_LVL_HI (2 << 5) -#define AIC_SMR_SRC_EDGE_HI (3 << 5) +#define AIC_SMR_SRC_EDGE_LOW (1 << 5) +#define AIC_SMR_SRC_LVL_HI (2 << 5) +#define AIC_SMR_SRC_EDGE_HI (3 << 5) /**************************************************************************/ /* Debug Unit */ @@ -192,7 +192,7 @@ typedef volatile unsigned long vulong; * Note that each of the following peripherals has it's own * set of these registers starting at offset 0x100 from it's * base address: DBGU, SPI, USART and SSC - * To access the DMA for a peripheral, use the macro for that + * To access the DMA for a peripheral, use the macro for that * peripheral but with these register offsets **************************************************************************/ /* Register Offsets */ diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h index e4952ae4ad..961da4b8e1 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h @@ -3,7 +3,7 @@ * * Copyright (c) 2003 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h index ea1d701de4..d7161e676f 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h @@ -3,7 +3,7 @@ * * Copyright (c) 2003 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -104,7 +104,7 @@ #define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ #define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ #define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ - + /* Receive Status Register, EMAC_RSR, Offset 0x20 */ #define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ #define EMAC_RSR_REC BIT1 /* 1 = Frame received */ @@ -137,7 +137,7 @@ #define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ #define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ #define EMAC_MAN_HIGH BIT30 /* Must be set */ -#define EMAC_MAN_LOW BIT31 +#define EMAC_MAN_LOW BIT31 /* * Bit assignments for Receive Buffer Descriptor diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h index d0a89a8f87..1aa38c9838 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h @@ -3,7 +3,7 @@ * * Copyright (c) 2002 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -59,16 +59,16 @@ * * PORT A */ -#define GPIO_0 BIT0 -#define GPIO_1 BIT1 -#define GPIO_2 BIT2 -#define GPIO_3 BIT3 -#define GPIO_4 BIT4 -#define GPIO_5 BIT5 -#define GPIO_6 BIT6 -#define GPIO_7 BIT7 -#define GPIO_8 BIT8 -#define GPIO_9 BIT9 +#define GPIO_0 BIT0 +#define GPIO_1 BIT1 +#define GPIO_2 BIT2 +#define GPIO_3 BIT3 +#define GPIO_4 BIT4 +#define GPIO_5 BIT5 +#define GPIO_6 BIT6 +#define GPIO_7 BIT7 +#define GPIO_8 BIT8 +#define GPIO_9 BIT9 #define GPIO_10 BIT10 #define GPIO_11 BIT11 #define GPIO_12 BIT12 @@ -92,16 +92,16 @@ #define GPIO_30 BIT30 #define GPIO_31 BIT31 /* PORT B */ -#define GPIO_32 BIT0 -#define GPIO_33 BIT1 -#define GPIO_34 BIT2 -#define GPIO_35 BIT3 -#define GPIO_36 BIT4 -#define GPIO_37 BIT5 -#define GPIO_38 BIT6 -#define GPIO_39 BIT7 -#define GPIO_40 BIT8 -#define GPIO_41 BIT9 +#define GPIO_32 BIT0 +#define GPIO_33 BIT1 +#define GPIO_34 BIT2 +#define GPIO_35 BIT3 +#define GPIO_36 BIT4 +#define GPIO_37 BIT5 +#define GPIO_38 BIT6 +#define GPIO_39 BIT7 +#define GPIO_40 BIT8 +#define GPIO_41 BIT9 #define GPIO_42 BIT10 #define GPIO_43 BIT11 #define GPIO_44 BIT12 @@ -125,16 +125,16 @@ #define GPIO_62 BIT30 #define GPIO_63 BIT31 /* PORT C */ -#define GPIO_64 BIT0 -#define GPIO_65 BIT1 -#define GPIO_66 BIT2 -#define GPIO_67 BIT3 -#define GPIO_68 BIT4 -#define GPIO_69 BIT5 -#define GPIO_70 BIT6 -#define GPIO_71 BIT7 -#define GPIO_72 BIT8 -#define GPIO_73 BIT9 +#define GPIO_64 BIT0 +#define GPIO_65 BIT1 +#define GPIO_66 BIT2 +#define GPIO_67 BIT3 +#define GPIO_68 BIT4 +#define GPIO_69 BIT5 +#define GPIO_70 BIT6 +#define GPIO_71 BIT7 +#define GPIO_72 BIT8 +#define GPIO_73 BIT9 #define GPIO_74 BIT10 #define GPIO_75 BIT11 #define GPIO_76 BIT12 @@ -158,16 +158,16 @@ #define GPIO_94 BIT30 #define GPIO_95 BIT31 /* PORT D */ -#define GPIO_96 BIT0 -#define GPIO_97 BIT1 -#define GPIO_98 BIT2 -#define GPIO_99 BIT3 -#define GPIO_100 BIT4 -#define GPIO_101 BIT5 -#define GPIO_102 BIT6 -#define GPIO_103 BIT7 -#define GPIO_104 BIT8 -#define GPIO_105 BIT9 +#define GPIO_96 BIT0 +#define GPIO_97 BIT1 +#define GPIO_98 BIT2 +#define GPIO_99 BIT3 +#define GPIO_100 BIT4 +#define GPIO_101 BIT5 +#define GPIO_102 BIT6 +#define GPIO_103 BIT7 +#define GPIO_104 BIT8 +#define GPIO_105 BIT9 #define GPIO_106 BIT10 #define GPIO_107 BIT11 #define GPIO_108 BIT12 @@ -376,9 +376,9 @@ #define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ #define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ #define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ - + /* Port D, Alternate Function B */ - + #define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ #define PIOC_ASR_TCLK BIT8 /* ETM Clock */ #define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h index ac11ceb697..6bc4be9103 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h @@ -3,7 +3,7 @@ * * Copyright (c) 2002 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h index 40fd6c58f1..634ab676d8 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2002 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * diff --git a/c/src/lib/libcpu/arm/at91rm9200/include/bits.h b/c/src/lib/libcpu/arm/at91rm9200/include/bits.h index 8bbfa19906..9178fc0f9b 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/include/bits.h +++ b/c/src/lib/libcpu/arm/at91rm9200/include/bits.h @@ -3,7 +3,7 @@ * * Copyright (c) 2002 by Cogent Computer Systems * Written by Mike Kelly <mike@cogcomp.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * diff --git a/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S index 75952e9631..d8b6757e4c 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S +++ b/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S @@ -2,7 +2,7 @@ * Atmel AT91RM9200 Interrupt handler * * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -12,7 +12,7 @@ * $Id$ */ #define __asm__ - + .globl bsp_interrupt_dispatch bsp_interrupt_dispatch : /* @@ -21,7 +21,7 @@ bsp_interrupt_dispatch : * and load vector into r0 and handler address into r1. */ ldr r0, =0xFFFFF100 /* AIC_CTL_BASE + AIC_IVR */ - ldr r1, [r0] + ldr r1, [r0] str r1, [r0] /* write back in case we are using protect */ ldr r0, =0xFFFFF108 /* AIC_CTL_BASE + AIC_ISR */ @@ -35,7 +35,7 @@ bsp_interrupt_dispatch : IRQ_return: ldr r2, =0xFFFFF130 /* AIC_CTL_BASE + AIC_EIOCR */ str r1, [r2] - + ldmia sp!,{lr} mov pc, lr diff --git a/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c index ab3d96b625..99cf822570 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c +++ b/c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c @@ -2,7 +2,7 @@ * Atmel AT91RM9200 Interrupt handler * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -17,8 +17,8 @@ extern void default_int_handler(void); -/* - * Interrupt system initialization. Disable interrupts, clear +/* + * Interrupt system initialization. Disable interrupts, clear * any that are pending. */ void BSP_rtems_irq_mngt_init(void) diff --git a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.c b/c/src/lib/libcpu/arm/at91rm9200/irq/irq.c index d8255cd233..416c63125b 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.c +++ b/c/src/lib/libcpu/arm/at91rm9200/irq/irq.c @@ -2,7 +2,7 @@ * Atmel AT91RM9200 Interrupt handler * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -34,52 +34,52 @@ static int isValidInterrupt(int irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } - + /* - * Check if default handler is actually connected. If not, issue - * an error. Note: irq->name is a number corresponding to the - * sources PID (see the at91rm9200_pid for this mapping). We - * convert it to a long word offset to get source's vector register + * Check if default handler is actually connected. If not, issue + * an error. Note: irq->name is a number corresponding to the + * sources PID (see the at91rm9200_pid for this mapping). We + * convert it to a long word offset to get source's vector register */ if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) { return 0; } - + rtems_interrupt_disable(level); - + /* * store the new handler */ AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl; - + /* * unmask interrupt */ AIC_CTL_REG(AIC_IECR) = 1 << irq->name; - + /* * Enable interrupt on device */ if(irq->on) { irq->on(irq); } - + rtems_interrupt_enable(level); - + return 1; } -/* +/* * Remove and interrupt handler */ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * mask interrupt */ AIC_CTL_REG(AIC_IDCR) = 1 << irq->name; - + /* * Disable interrupt on device */ @@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * restore the default irq value */ AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler; - + rtems_interrupt_enable(level); return 1; diff --git a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h b/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h index 617a24bf7d..320c4415e5 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h +++ b/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h @@ -2,7 +2,7 @@ * Interrupt handler Header file * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -24,7 +24,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <at91rm9200.h> @@ -35,7 +35,7 @@ extern void default_int_handler(); /* possible interrupt sources on the AT91RM9200 */ #define AT91RM9200_INT_FIQ 0 #define AT91RM9200_INT_SYSIRQ 1 -#define AT91RM9200_INT_PIOA 2 +#define AT91RM9200_INT_PIOA 2 #define AT91RM9200_INT_PIOB 3 #define AT91RM9200_INT_PIOC 4 #define AT91RM9200_INT_PIOD 5 @@ -71,7 +71,7 @@ extern void default_int_handler(); /* we can treat the AT91RM9200 AIC_SVR_BASE as */ /* a vector table */ #define VECTOR_TABLE AIC_SVR_BASE - + typedef unsigned char rtems_irq_level; typedef unsigned char rtems_irq_trigger; @@ -117,7 +117,7 @@ void BSP_rtems_irq_mngt_init(); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* - * function to get the current RTEMS irq handler for ptr->name. + * function to get the current RTEMS irq handler for ptr->name. */ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); diff --git a/c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c b/c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c index 89616565ea..b5d65149fb 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c +++ b/c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c @@ -2,7 +2,7 @@ * Atmel AT91RM9200 PMC functions * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * diff --git a/c/src/lib/libcpu/arm/at91rm9200/timer/timer.c b/c/src/lib/libcpu/arm/at91rm9200/timer/timer.c index 7e407d82cf..5e7c267e58 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/timer/timer.c +++ b/c/src/lib/libcpu/arm/at91rm9200/timer/timer.c @@ -4,7 +4,7 @@ * This uses timer 0 for timing measurments. * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -16,7 +16,7 @@ * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * the number of microseconds since benchmark_timer_initialize() exitted. * - * It is important that the timer start/stop overhead be determined + * It is important that the timer start/stop overhead be determined * when porting or modifying this code. * * $Id$ @@ -31,7 +31,7 @@ uint16_t tstart; bool benchmark_timer_find_average_overhead; uint32_t tick_time; /* - * Set up TC0 - + * Set up TC0 - * timer_clock2 (MCK/8) * capture mode - this shouldn't matter */ diff --git a/c/src/lib/libcpu/arm/at91rm9200/usart/usart.c b/c/src/lib/libcpu/arm/at91rm9200/usart/usart.c index c26cccc1f9..7633f05291 100644 --- a/c/src/lib/libcpu/arm/at91rm9200/usart/usart.c +++ b/c/src/lib/libcpu/arm/at91rm9200/usart/usart.c @@ -1,10 +1,10 @@ /* * Driver for AT91RM9200 USART ports * - * COPYRIGHT (c) 2006-2009. + * COPYRIGHT (c) 2006-2009. * NCB - Sistemas Embarcados Ltda. (Brazil) * Fernando Nicodemos <fgnicodemos@terra.com.br> - * + * * and * * COPYRIGHT (c) 1989-2009. @@ -60,7 +60,7 @@ at91rm9200_usart_regs_t *usart_get_base(int minor) if (console_entry == NULL) return 0; - + port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1; //printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port ); @@ -241,11 +241,11 @@ static int usart_set_attributes(int minor, const struct termios *t) mode |= US_MR_PAR_NONE; baud_requested = t->c_cflag & CBAUD; - + /* If not, set the dbgu console baud as USART baud default */ if (!baud_requested) - baud_requested = BSP_get_baud(); - + baud_requested = BSP_get_baud(); + baud = rtems_termios_baud_to_number(baud_requested); brgr = (at91rm9200_get_mck() / 16) / baud; diff --git a/c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c b/c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c index b8859f7bfa..c277c8ee2f 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c +++ b/c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c @@ -35,7 +35,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0, 3, /* unused for ARM cpus */ 0 }; /* unused for ARM cpus */ -/* If you follow the code, this is never used, so any value +/* If you follow the code, this is never used, so any value * should work */ #define CLOCK_VECTOR 0 @@ -72,16 +72,16 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0, * - enable it * - clear any pending interrupts * - * Since you may want the clock always running, you can + * Since you may want the clock always running, you can * enable interrupts here. If you do so, the clock_isr_on(), - * clock_isr_off(), and clock_isr_is_on() functions can be + * clock_isr_off(), and clock_isr_is_on() functions can be * NOPs. */ - + /* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick() * MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s - */ - + */ + #define Clock_driver_support_initialize_hardware() \ do { \ T0TCR &= 0; /* disable and clear timer 0, set to */ \ @@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0, } while (0) /** - * Do whatever you need to shut the clock down and remove the + * Do whatever you need to shut the clock down and remove the * interrupt handler. Since this normally only gets called on * RTEMS shutdown, you may not need to do anything other than * remove the ISR. @@ -110,12 +110,12 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0, uint32_t bsp_clock_nanoseconds_since_last_tick(void) { uint32_t clicks; - + clicks = T0TC; /*T0TC is the 32bit time counter 0*/ - + return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000; } - + #define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick diff --git a/c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h b/c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h index d5a021a34a..da99635d00 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h +++ b/c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h @@ -2,7 +2,7 @@ * Philips LPC22XX/LPC21xx Register definitions * * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -318,7 +318,7 @@ #define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ -#ifdef CONFIG_ARCH_LPC22xx +#ifdef CONFIG_ARCH_LPC22xx #define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */ #define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */ #define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */ @@ -455,7 +455,7 @@ /* Register define for constant -*/ +*/ #define REG_U0RBR 0xE000C000 #define REG_U1RBR 0xE0010000 diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S index d8181055c3..cec8a00b79 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S +++ b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S @@ -12,8 +12,8 @@ * $Id$ */ #define __asm__ - -/* + +/* * BSP specific interrupt handler for INT or FIQ. In here * you do determine which interrupt happened and call its * handler. @@ -30,7 +30,7 @@ bsp_interrupt_dispatch : * From source, determine offset into expanded vector table * and load handler address into r0. */ - + ldr r0, =0xFFFFF030 /* Read the vector number */ ldr r0, [r0] #ifdef __thumb__ diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c index db16373eac..4c5b7850ad 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c +++ b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c @@ -1,6 +1,6 @@ /* * NXP/Philips LPC22XX/LPC21xx Interrupt handler - * Ray 2007 <rayx.cn@gmail.com> to support LPC ARM + * Ray 2007 <rayx.cn@gmail.com> to support LPC ARM * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -16,8 +16,8 @@ extern void default_int_handler(void); -/* - * Interrupt system initialization. Disable interrupts, clear +/* + * Interrupt system initialization. Disable interrupts, clear * any that are pending. */ void BSP_rtems_irq_mngt_init(void) @@ -33,7 +33,7 @@ void BSP_rtems_irq_mngt_init(void) for (i=0; i<BSP_MAX_INT; i++) { *(vectorTable + i) = (long)(default_int_handler); } - + /* * Set IRQHandler */ @@ -56,10 +56,10 @@ void BSP_rtems_irq_mngt_init(void) * In case we must find an ABORT error, * enable the next lines and set a breakpoint * in ABORTHandler. - */ + */ #if 1 DATA_ABORT_VECTOR_ADDR = 0xE59FF018; -#endif +#endif /* * Init the Vectored Interrupt Controller (VIC) diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.c b/c/src/lib/libcpu/arm/lpc22xx/irq/irq.c index cf2287d070..dfc97f9135 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.c +++ b/c/src/lib/libcpu/arm/lpc22xx/irq/irq.c @@ -1,7 +1,7 @@ /* * Philps LPC22XX Interrupt handler - * - * Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM + * + * Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -37,11 +37,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) rtems_interrupt_level level; rtems_irq_hdl *bsp_tbl; int *vic_cntl; - + bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase; vic_cntl=(int *)VICVectCntlBase; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -66,8 +66,8 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) */ vic_cntl[irq->name] = 0x20 | irq->name; - VICIntEnable |= 1 << irq->name; - + VICIntEnable |= 1 << irq->name; + if(irq->on) { irq->on(irq); @@ -75,11 +75,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) rtems_interrupt_enable(level); - + return 1; } -/* +/* * Remove and interrupt handler * * You should only have to add the code to mask the interrupt. @@ -91,7 +91,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) rtems_irq_hdl *bsp_tbl; bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -116,7 +116,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * restore the default irq value */ bsp_tbl[irq->name] = default_int_handler; - + rtems_interrupt_enable(level); return 1; diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h b/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h index 428530958a..11f8de1bba 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h +++ b/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h @@ -1,8 +1,8 @@ /* * Interrupt handler Header file * - * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM - * + * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -25,7 +25,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <lpc22xx.h> @@ -66,7 +66,7 @@ extern void default_int_handler(); #define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ #define BSP_MAX_INT 28 -#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) +#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) #define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) #define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) #define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) @@ -77,7 +77,7 @@ extern void default_int_handler(); #define IRQ_ISR_ADDR (*(u_long *)0x00000038L) #define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) - + typedef unsigned char rtems_irq_level; typedef unsigned char rtems_irq_trigger; @@ -91,7 +91,7 @@ typedef int (*rtems_irq_is_enabled)(const struct __rtems_irq_connect_data__*); //extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT]; #define VECTOR_TABLE VICVectAddrBase - + typedef struct __rtems_irq_connect_data__ { /* IRQ line */ rtems_irq_number name; @@ -127,7 +127,7 @@ void BSP_rtems_irq_mngt_init(); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* - * function to get the current RTEMS irq handler for ptr->name. + * function to get the current RTEMS irq handler for ptr->name. */ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); diff --git a/c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h b/c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h index 2e58da4e6b..364812ddb8 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h +++ b/c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h @@ -11,16 +11,16 @@ #define TCR_ENABLE_BIT 0 #define TCR_RESET_BIT 1 -// The channel name which is used in matching, in fact they represent -// corresponding Match Register +// The channel name which is used in matching, in fact they represent +// corresponding Match Register #define CH_MAXNUM 4 #define CH0 0 #define CH1 1 #define CH2 2 #define CH3 3 -// The channel name which is used in capturing, in fact they represent -// corresponding Capture Register +// The channel name which is used in capturing, in fact they represent +// corresponding Capture Register #define CPCH_MAXNUM 4 #define CPCH0 0 #define CPCH1 1 diff --git a/c/src/lib/libcpu/arm/lpc22xx/timer/timer.c b/c/src/lib/libcpu/arm/lpc22xx/timer/timer.c index 91f6df408b..0ac8ab32c1 100644 --- a/c/src/lib/libcpu/arm/lpc22xx/timer/timer.c +++ b/c/src/lib/libcpu/arm/lpc22xx/timer/timer.c @@ -2,7 +2,7 @@ * RTL22xx board Timer driver * * This uses Timer1 for timing measurments. - * + * * By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP * * The license and distribution terms for this file may be @@ -16,7 +16,7 @@ * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * the number of microseconds since benchmark_timer_initialize() exitted. * - * It is important that the timer start/stop overhead be determined + * It is important that the timer start/stop overhead be determined * when porting or modifying this code. * * $Id$ @@ -31,7 +31,7 @@ uint32_t g_freq; bool benchmark_timer_find_average_overhead; - + /* * Set up Timer 1 */ diff --git a/c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c b/c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c index d54cf74543..1f18e1ce76 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c +++ b/c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c @@ -37,12 +37,12 @@ rtems_irq_connect_data clock_isr_data = { .isOn = clock_isr_is_on, }; -/* If you follow the code, this is never used, so any value +/* If you follow the code, this is never used, so any value * should work */ #define CLOCK_VECTOR 0 - + /** * When we get the clock interrupt * - clear the interrupt bit? @@ -72,9 +72,9 @@ rtems_irq_connect_data clock_isr_data = { * - enable it * - clear any pending interrupts * - * Since you may want the clock always running, you can + * Since you may want the clock always running, you can * enable interrupts here. If you do so, the clock_isr_on(), - * clock_isr_off(), and clock_isr_is_on() functions can be + * clock_isr_off(), and clock_isr_is_on() functions can be * NOPs. */ #define Clock_driver_support_initialize_hardware() \ @@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = { } while (0) /** - * Do whatever you need to shut the clock down and remove the + * Do whatever you need to shut the clock down and remove the * interrupt handler. Since this normally only gets called on * RTEMS shutdown, you may not need to do anything other than * remove the ISR. diff --git a/c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h b/c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h index 6aebf0928c..4a3dc03544 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h +++ b/c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h @@ -3,7 +3,7 @@ * * Copyright (c) 2003 by Cogent Computer Systems * Written by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -75,12 +75,12 @@ #define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6) #define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6) #define MC9328MXL_TMR_TCTL_OM (bit(5)) -#define MC9328MXL_TMR_TCTL_IRQEN (bit(4)) +#define MC9328MXL_TMR_TCTL_IRQEN (bit(4)) #define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1) -#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1) +#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1) #define MC9328MXL_TMR_TCTL_TEN (bit(0)) #define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00))) @@ -221,7 +221,7 @@ typedef struct { #define MC9328MXL_UART_CR3_INVT (bit(1)) #define MC9328MXL_UART_CR3_BPEN (bit(0)) -#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10) +#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10) #define MC9328MXL_UART_CR4_INVR (bit(9)) #define MC9328MXL_UART_CR4_ENIRI (bit(8)) #define MC9328MXL_UART_CR4_WKEN (bit(7)) @@ -313,7 +313,7 @@ typedef struct { #define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10) #define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff) #define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0) - + #define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00))) #define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04))) diff --git a/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S index bcb3ba0e19..c2a33c4b22 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S +++ b/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S @@ -12,8 +12,8 @@ * $Id$ */ #define __asm__ - -/* + +/* * BSP specific interrupt handler for INT or FIQ. In here * you do determine which interrupt happened and call its * handler. @@ -29,7 +29,7 @@ bsp_interrupt_dispatch : ldr r1, [r0] mov r1, r1, LSR #16 /* get the NIVECTOR into 16 LSbits */ - /* find the ISR's address based on the vector */ + /* find the ISR's address based on the vector */ ldr r0, =bsp_vector_table mov r1, r1, LSL #3 /* Shift vector to get offset into table */ add r1, r0, r1 /* r1 has address of vector entry */ diff --git a/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c index fd96778851..90e854440e 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c +++ b/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c @@ -2,7 +2,7 @@ * Motorola MC9328MXL Interrupt handler * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -17,8 +17,8 @@ extern void default_int_handler(void); -/* - * Interrupt system initialization. Disable interrupts, clear +/* + * Interrupt system initialization. Disable interrupts, clear * any that are pending. */ void BSP_rtems_irq_mngt_init(void) diff --git a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c b/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c index 81a9c8ee72..36d23dc1d9 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c +++ b/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c @@ -2,7 +2,7 @@ * Motorola MC9328MXL Interrupt handler * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -38,7 +38,7 @@ static int isValidInterrupt(int irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -65,13 +65,13 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { irq->on(irq); } - + rtems_interrupt_enable(level); - + return 1; } -/* +/* * Remove and interrupt handler * * You should only have to add the code to mask the interrupt. diff --git a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h b/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h index 04a5f2a00b..6cc5c22f07 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h +++ b/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h @@ -2,7 +2,7 @@ * Interrupt handler Header file * * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -27,7 +27,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <mc9328mxl.h> @@ -37,72 +37,72 @@ extern void default_int_handler(); **********************************************************************/ /* possible interrupt sources on the MC9328MXL */ -#define BSP_INT_UART3_PFERR 0 -#define BSP_INT_UART3_RTS 1 -#define BSP_INT_UART3_DTR 2 -#define BSP_INT_UART3_UARTC 3 -#define BSP_INT_UART3_TX 4 -#define BSP_INT_PEN_UP 5 +#define BSP_INT_UART3_PFERR 0 +#define BSP_INT_UART3_RTS 1 +#define BSP_INT_UART3_DTR 2 +#define BSP_INT_UART3_UARTC 3 +#define BSP_INT_UART3_TX 4 +#define BSP_INT_PEN_UP 5 #define BSP_INT_CSI 6 -#define BSP_INT_MMA_MAC 7 +#define BSP_INT_MMA_MAC 7 #define BSP_INT_MMA 8 #define BSP_INT_COMP 9 -#define BSP_INT_MSIRQ 10 -#define BSP_INT_GPIO_PORTA 11 -#define BSP_INT_GPIO_PORTB 12 -#define BSP_INT_GPIO_PORTC 13 -#define BSP_INT_LCDC 14 -#define BSP_INT_SIM_IRQ 15 -#define BSP_INT_SIM_DATA 16 +#define BSP_INT_MSIRQ 10 +#define BSP_INT_GPIO_PORTA 11 +#define BSP_INT_GPIO_PORTB 12 +#define BSP_INT_GPIO_PORTC 13 +#define BSP_INT_LCDC 14 +#define BSP_INT_SIM_IRQ 15 +#define BSP_INT_SIM_DATA 16 #define BSP_INT_RTC 17 -#define BSP_INT_RTC_SAM 18 -#define BSP_INT_UART2_PFERR 19 -#define BSP_INT_UART2_RTS 20 -#define BSP_INT_UART2_DTR 21 -#define BSP_INT_UART2_UARTC 22 -#define BSP_INT_UART2_TX 23 -#define BSP_INT_UART2_RX 24 -#define BSP_INT_UART1_PFERR 25 -#define BSP_INT_UART1_RTS 26 -#define BSP_INT_UART1_DTR 27 -#define BSP_INT_UART1_UARTC 28 -#define BSP_INT_UART1_TX 29 -#define BSP_INT_UART1_RX 30 -#define BSP_INT_RES31 31 -#define BSP_INT_RES32 32 -#define BSP_INT_PEN_DATA 33 +#define BSP_INT_RTC_SAM 18 +#define BSP_INT_UART2_PFERR 19 +#define BSP_INT_UART2_RTS 20 +#define BSP_INT_UART2_DTR 21 +#define BSP_INT_UART2_UARTC 22 +#define BSP_INT_UART2_TX 23 +#define BSP_INT_UART2_RX 24 +#define BSP_INT_UART1_PFERR 25 +#define BSP_INT_UART1_RTS 26 +#define BSP_INT_UART1_DTR 27 +#define BSP_INT_UART1_UARTC 28 +#define BSP_INT_UART1_TX 29 +#define BSP_INT_UART1_RX 30 +#define BSP_INT_RES31 31 +#define BSP_INT_RES32 32 +#define BSP_INT_PEN_DATA 33 #define BSP_INT_PWM 34 -#define BSP_INT_MMC_IRQ 35 -#define BSP_INT_SSI2_TX 36 -#define BSP_INT_SSI2_RX 37 -#define BSP_INT_SSI2_ERR 38 +#define BSP_INT_MMC_IRQ 35 +#define BSP_INT_SSI2_TX 36 +#define BSP_INT_SSI2_RX 37 +#define BSP_INT_SSI2_ERR 38 #define BSP_INT_I2C 39 #define BSP_INT_SPI2 40 #define BSP_INT_SPI1 41 -#define BSP_INT_SSI_TX 42 -#define BSP_INT_SSI_TX_ERR 43 -#define BSP_INT_SSI_RX 44 -#define BSP_INT_SSI_RX_ERR 45 -#define BSP_INT_TOUCH 46 -#define BSP_INT_USBD0 47 -#define BSP_INT_USBD1 48 -#define BSP_INT_USBD2 49 -#define BSP_INT_USBD3 50 -#define BSP_INT_USBD4 51 -#define BSP_INT_USBD5 52 -#define BSP_INT_USBD6 53 -#define BSP_INT_UART3_RX 54 -#define BSP_INT_BTSYS 55 -#define BSP_INT_BTTIM 56 -#define BSP_INT_BTWUI 57 -#define BSP_INT_TIMER2 58 -#define BSP_INT_TIMER1 59 -#define BSP_INT_DMA_ERR 60 +#define BSP_INT_SSI_TX 42 +#define BSP_INT_SSI_TX_ERR 43 +#define BSP_INT_SSI_RX 44 +#define BSP_INT_SSI_RX_ERR 45 +#define BSP_INT_TOUCH 46 +#define BSP_INT_USBD0 47 +#define BSP_INT_USBD1 48 +#define BSP_INT_USBD2 49 +#define BSP_INT_USBD3 50 +#define BSP_INT_USBD4 51 +#define BSP_INT_USBD5 52 +#define BSP_INT_USBD6 53 +#define BSP_INT_UART3_RX 54 +#define BSP_INT_BTSYS 55 +#define BSP_INT_BTTIM 56 +#define BSP_INT_BTWUI 57 +#define BSP_INT_TIMER2 58 +#define BSP_INT_TIMER1 59 +#define BSP_INT_DMA_ERR 60 #define BSP_INT_DMA 61 -#define BSP_INT_GPIO_PORTD 62 +#define BSP_INT_GPIO_PORTD 62 #define BSP_INT_WDT 63 #define BSP_MAX_INT 64 - + typedef struct { rtems_irq_hdl vector; rtems_irq_hdl_param data; diff --git a/c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c b/c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c index f97ba13751..46565669e6 100644 --- a/c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c +++ b/c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c @@ -5,7 +5,7 @@ * * Copyright (c) 2004 Cogent Computer Systems * Written by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -17,7 +17,7 @@ * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * the number of microseconds since benchmark_timer_initialize() exitted. * - * It is important that the timer start/stop overhead be determined + * It is important that the timer start/stop overhead be determined * when porting or modifying this code. * * $Id$ @@ -32,13 +32,13 @@ uint32_t g_freq; bool benchmark_timer_find_average_overhead; - + /* * Set up Timer 1 */ void benchmark_timer_initialize( void ) { - MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | + MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | MC9328MXL_TMR_TCTL_FRR | MC9328MXL_TMR_TCTL_TEN); /* set prescaler to 1 (register value + 1) */ \ @@ -80,12 +80,12 @@ int benchmark_timer_read( void ) total = (t - g_start); /* convert to nanoseconds */ - total = (total * 1000)/ g_freq; + total = (total * 1000)/ g_freq; if ( benchmark_timer_find_average_overhead == 1 ) { - return (int) total; + return (int) total; } else if ( total < LEAST_VALID ) { - return 0; + return 0; } /* * Somehow convert total into microseconds diff --git a/c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c b/c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c index cbcd44ed2a..cf01feea7f 100755 --- a/c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c +++ b/c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c @@ -31,8 +31,8 @@ static void ffuart_write_polled(int minor, char c); static int ffuart_set_attributes(int minor, const struct termios *t); /* Pointers to functions for handling the UART. */ -console_fns ffuart_fns = -{ +console_fns ffuart_fns = +{ libchip_serial_default_probe, ffuart_first_open, ffuart_last_close, @@ -45,23 +45,23 @@ console_fns ffuart_fns = }; -/* +/* * This is called the first time each device is opened. Since - * the driver is polled, we don't have to do anything. If the driver - * were interrupt driven, we'd enable interrupts here. + * the driver is polled, we don't have to do anything. If the driver + * were interrupt driven, we'd enable interrupts here. */ -static int ffuart_first_open(int major, int minor, void *arg) +static int ffuart_first_open(int major, int minor, void *arg) { return 0; } -/* +/* * This is called the last time each device is closed. Since - * the driver is polled, we don't have to do anything. If the driver - * were interrupt driven, we'd disable interrupts here. + * the driver is polled, we don't have to do anything. If the driver + * were interrupt driven, we'd disable interrupts here. */ -static int ffuart_last_close(int major, int minor, void *arg) +static int ffuart_last_close(int major, int minor, void *arg) { return 0; } @@ -73,7 +73,7 @@ static int ffuart_last_close(int major, int minor, void *arg) * return -1 if there's no data, otherwise return * the character in lowest 8 bits of returned int. */ -static int ffuart_read(int minor) +static int ffuart_read(int minor) { char c; console_tbl *console_entry; @@ -90,15 +90,15 @@ static int ffuart_read(int minor) if (!(ffuart->lsr & FULL_RECEIVE)) { return -1; } - - c = ffuart->rbr & 0xff; - + + c = ffuart->rbr & 0xff; + return c; } -/* - * Write buffer to UART +/* + * Write buffer to UART * * return 1 on success, -1 on error */ @@ -124,7 +124,7 @@ static int ffuart_write(int minor, const char *buf, int len) break; } } - + c = (char) buf[i]; #if ON_SKYEYE != 1 if(c=='\n'){ @@ -140,14 +140,14 @@ static int ffuart_write(int minor, const char *buf, int len) } #endif ffuart->rbr = c; - + /* the TXRDY flag does not seem to update right away (is this true?) */ /* so we wait a bit before continuing */ for (x = 0; x < 100; x++) { dbg_dly++; /* using a global so this doesn't get optimized out */ } } - + return 1; } @@ -155,7 +155,7 @@ static int ffuart_write(int minor, const char *buf, int len) static void ffuart_init(int minor) { - + console_tbl *console_entry; ffuart_reg_t *ffuart; unsigned int divisor; @@ -163,11 +163,11 @@ static void ffuart_init(int minor) console_entry = BSP_get_uart_from_minor(minor); - + if (console_entry == NULL) { return; } - + ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1; ffuart->lcr |= DLAB; /*Set the Bound*/ @@ -191,7 +191,7 @@ static void ffuart_write_polled(int minor, char c) } /* This is for setting baud rate, bits, etc. */ -static int ffuart_set_attributes(int minor, const struct termios *t) +static int ffuart_set_attributes(int minor, const struct termios *t) { return 0; } @@ -202,7 +202,7 @@ static int ffuart_set_attributes(int minor, const struct termios *t) * functions use them instead. */ /***********************************************************************/ -/* +/* * Read from UART. This is used in the exit code, and can't * rely on interrupts. */ @@ -213,7 +213,7 @@ int ffuart_poll_read(int minor) /* - * Write a character to the console. This is used by printk() and + * Write a character to the console. This is used by printk() and * maybe other low level functions. It should not use interrupts or any * RTEMS system calls. It needs to be very simple */ diff --git a/c/src/lib/libcpu/arm/pxa255/include/ffuart.h b/c/src/lib/libcpu/arm/pxa255/include/ffuart.h index db01efc296..6ca5879987 100755 --- a/c/src/lib/libcpu/arm/pxa255/include/ffuart.h +++ b/c/src/lib/libcpu/arm/pxa255/include/ffuart.h @@ -47,4 +47,4 @@ typedef struct { #define FULL_RECEIVE 0x01 #endif - + diff --git a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S index ada3b67821..17d5e47f1d 100755 --- a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S +++ b/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S @@ -1,7 +1,7 @@ /* * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. @@ -10,7 +10,7 @@ */ #define __asm__ - + .globl bsp_interrupt_dispatch bsp_interrupt_dispatch : /* diff --git a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c index ebdaf5bd18..0470c88ce9 100755 --- a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c +++ b/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c @@ -1,7 +1,7 @@ /* * PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. @@ -20,8 +20,8 @@ void dummy_handler(uint32_t vector) void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector); -/* - * Interrupt system initialization. Disable interrupts, clear +/* + * Interrupt system initialization. Disable interrupts, clear * any that are pending. */ void BSP_rtems_irq_mngt_init(void) diff --git a/c/src/lib/libcpu/arm/pxa255/irq/irq.c b/c/src/lib/libcpu/arm/pxa255/irq/irq.c index 859b6834c0..2bfcadc98f 100755 --- a/c/src/lib/libcpu/arm/pxa255/irq/irq.c +++ b/c/src/lib/libcpu/arm/pxa255/irq/irq.c @@ -1,7 +1,7 @@ /* * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. @@ -32,54 +32,54 @@ static int isValidInterrupt(int irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } - + /* - * Check if default handler is actually connected. If not, issue - * an error. Note: irq->name is a number corresponding to the - * interrupt number . We - * convert it to a long word offset to get source's vector register + * Check if default handler is actually connected. If not, issue + * an error. Note: irq->name is a number corresponding to the + * interrupt number . We + * convert it to a long word offset to get source's vector register */ if (IRQ_table[irq->name] != dummy_handler) { return 0; } - + _CPU_ISR_Disable(level); - + /* * store the new handler */ IRQ_table[irq->name] = irq->hdl; - + /* * unmask interrupt */ XSCALE_INT_ICMR = XSCALE_INT_ICMR | 1 << irq->name; - + /* * Enable interrupt on device */ if(irq->on) { irq->on(irq); } - + _CPU_ISR_Enable(level); - + return 1; } -/* +/* * Remove and interrupt handler */ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * mask interrupt */ XSCALE_INT_ICMR = XSCALE_INT_ICMR & (~(1 << irq->name)); - + /* * Disable interrupt on device */ @@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * restore the default irq value */ IRQ_table[irq->name] = dummy_handler; - + _CPU_ISR_Enable(level); return 1; diff --git a/c/src/lib/libcpu/arm/pxa255/irq/irq.h b/c/src/lib/libcpu/arm/pxa255/irq/irq.h index d685269ee6..dcc86384c7 100755 --- a/c/src/lib/libcpu/arm/pxa255/irq/irq.h +++ b/c/src/lib/libcpu/arm/pxa255/irq/irq.h @@ -1,7 +1,7 @@ /* * Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. @@ -21,7 +21,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <pxa255.h> @@ -77,7 +77,7 @@ void BSP_rtems_irq_mngt_init(); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* - * function to get the current RTEMS irq handler for ptr->name. + * function to get the current RTEMS irq handler for ptr->name. */ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); diff --git a/c/src/lib/libcpu/arm/pxa255/timer/timer.c b/c/src/lib/libcpu/arm/pxa255/timer/timer.c index d4162818fa..d174d4756f 100755 --- a/c/src/lib/libcpu/arm/pxa255/timer/timer.c +++ b/c/src/lib/libcpu/arm/pxa255/timer/timer.c @@ -8,7 +8,7 @@ * Timer_initialize() and Read_timer(). Read_timer() usually returns * the number of microseconds since Timer_initialize() exitted. * - * It is important that the timer start/stop overhead be determined + * It is important that the timer start/stop overhead be determined * when porting or modifying this code. * * The license and distribution terms for this file may be @@ -29,7 +29,7 @@ bool benchmark_timer_find_average_overhead; bool benchmark_timer_is_initialized = false; /* - * Use the timer count register to measure. + * Use the timer count register to measure. * The frequency of it is 3.4864MHZ * The longest period we are able to capture is 4G/3.4864MHZ */ @@ -62,7 +62,7 @@ int benchmark_timer_read(void) total -= tick_time; else total += 0xffffffff - tick_time; /*Round up but not overflow*/ - + if ( benchmark_timer_find_average_overhead == true ) return total; /*Counter cycles*/ diff --git a/c/src/lib/libcpu/arm/s3c2400/clock/support.c b/c/src/lib/libcpu/arm/s3c2400/clock/support.c index 7d85c1a9f4..99bd21168a 100644 --- a/c/src/lib/libcpu/arm/s3c2400/clock/support.c +++ b/c/src/lib/libcpu/arm/s3c2400/clock/support.c @@ -41,10 +41,10 @@ uint32_t get_UCLK(void) /* return HCLK frequency */ uint32_t get_HCLK(void) { - if (rCLKDIVN & 0x2) + if (rCLKDIVN & 0x2) return get_FCLK()/2; else - return get_FCLK(); + return get_FCLK(); } /* return PCLK frequency */ diff --git a/c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h b/c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h index 98138ab08b..b8243a7790 100644 --- a/c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h +++ b/c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h @@ -472,7 +472,7 @@ typedef union unsigned long all; } LCDCON1; -typedef union { +typedef union { struct { unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ /* VSYNC pulse's high level width by counting the */ diff --git a/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S index 5fab93dc2f..d3df84dd11 100644 --- a/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S +++ b/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S @@ -14,24 +14,24 @@ */ #define __asm__ - -/* - * Function to obtain, execute an IT handler and acknowledge the IT + +/* + * Function to obtain, execute an IT handler and acknowledge the IT */ .globl bsp_interrupt_dispatch - -bsp_interrupt_dispatch : + +bsp_interrupt_dispatch : ldr r0, =0x14400014 /* Read rINTOFFSET */ ldr r1, [r0] ldr r0, =bsp_vector_table ldr r0, [r0, r1, LSL #2] /* Read the address */ - + stmdb sp!,{lr} ldr lr, =IRQ_return /* prepare the return from handler */ - + mov pc, r0 IRQ_return: diff --git a/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c index c3122a0b8d..2e1e0c4ae1 100644 --- a/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c +++ b/c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c @@ -18,7 +18,7 @@ extern void default_int_handler(); -void BSP_rtems_irq_mngt_init() +void BSP_rtems_irq_mngt_init() { long *vectorTable; int i; diff --git a/c/src/lib/libcpu/arm/s3c2400/irq/irq.c b/c/src/lib/libcpu/arm/s3c2400/irq/irq.c index 6cef0e9268..20bcbb409f 100644 --- a/c/src/lib/libcpu/arm/s3c2400/irq/irq.c +++ b/c/src/lib/libcpu/arm/s3c2400/irq/irq.c @@ -41,7 +41,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_irq_hdl *HdlTable; rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -53,7 +53,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) if (*(HdlTable + irq->name) != default_int_handler) { return 0; } - + rtems_interrupt_disable(level); /* @@ -78,7 +78,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_irq_hdl *HdlTable; rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -103,7 +103,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * restore the default irq value */ *(HdlTable + irq->name) = default_int_handler; - + rtems_interrupt_enable(level); return 1; diff --git a/c/src/lib/libcpu/arm/s3c2400/irq/irq.h b/c/src/lib/libcpu/arm/s3c2400/irq/irq.h index f58dbb9d98..1700285df5 100644 --- a/c/src/lib/libcpu/arm/s3c2400/irq/irq.h +++ b/c/src/lib/libcpu/arm/s3c2400/irq/irq.h @@ -23,7 +23,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <s3c2400.h> @@ -41,35 +41,35 @@ extern void default_int_handler(); #define BSP_EINT5 5 #define BSP_EINT6 6 #define BSP_EINT7 7 -#define BSP_INT_TICK 8 -#define BSP_INT_WDT 9 -#define BSP_INT_TIMER0 10 -#define BSP_INT_TIMER1 11 -#define BSP_INT_TIMER2 12 -#define BSP_INT_TIMER3 13 -#define BSP_INT_TIMER4 14 -#define BSP_INT_UERR01 15 -#define _res0 16 -#define BSP_INT_DMA0 17 -#define BSP_INT_DMA1 18 -#define BSP_INT_DMA2 19 -#define BSP_INT_DMA3 20 -#define BSP_INT_MMC 21 -#define BSP_INT_SPI 22 -#define BSP_INT_URXD0 23 -#define BSP_INT_URXD1 24 -#define BSP_INT_USBD 25 -#define BSP_INT_USBH 26 -#define BSP_INT_IIC 27 -#define BSP_INT_UTXD0 28 -#define BSP_INT_UTXD1 29 -#define BSP_INT_RTC 30 -#define BSP_INT_ADC 31 -#define BSP_MAX_INT 32 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UERR01 15 +#define _res0 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_MMC 21 +#define BSP_INT_SPI 22 +#define BSP_INT_URXD0 23 +#define BSP_INT_URXD1 24 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UTXD0 28 +#define BSP_INT_UTXD1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 extern void *bsp_vector_table; #define VECTOR_TABLE &bsp_vector_table - + /* * Type definition for RTEMS managed interrupts */ @@ -101,9 +101,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). @@ -178,7 +178,7 @@ void BSP_rtems_irq_mngt_init(); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); diff --git a/c/src/lib/libcpu/arm/s3c2400/timer/timer.c b/c/src/lib/libcpu/arm/s3c2400/timer/timer.c index aa9dd22077..171ce4e5a6 100644 --- a/c/src/lib/libcpu/arm/s3c2400/timer/timer.c +++ b/c/src/lib/libcpu/arm/s3c2400/timer/timer.c @@ -14,7 +14,7 @@ * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * the number of microseconds since benchmark_timer_initialize() exitted. * - * It is important that the timer start/stop overhead be determined + * It is important that the timer start/stop overhead be determined * when porting or modifying this code. * * $Id$ @@ -29,7 +29,7 @@ uint32_t g_freq; bool benchmark_timer_find_average_overhead; - + /* * Set up Timer 1 */ @@ -37,7 +37,7 @@ void benchmark_timer_initialize( void ) { uint32_t cr; - /* stop TIMER1*/ + /* stop TIMER1*/ cr=rTCON & 0xFFFFF0FF; rTCON=(cr | (0x0 << 8)); @@ -45,15 +45,15 @@ void benchmark_timer_initialize( void ) cr=rTCFG1 & 0xFFFFFF0F; rTCFG1=(cr | (0<<4)); - /* input freq=PLCK/2 Mhz*/ - g_freq = get_PCLK() / 2000; + /* input freq=PLCK/2 Mhz*/ + g_freq = get_PCLK() / 2000; rTCNTB1 = 0xFFFF; - /* start TIMER1 with manual reload */ + /* start TIMER1 with manual reload */ cr=rTCON & 0xFFFFF0FF; rTCON=(cr | (0x1 << 9)); rTCON=(cr | (0x1 << 8)); - + g_start = rTCNTO1; } @@ -83,16 +83,16 @@ int benchmark_timer_read( void ) * interrupts since the timer was initialized and clicks since the last * interrupts. */ - + total = (g_start - t); /* convert to microseconds */ - total = (total*1000) / g_freq; + total = (total*1000) / g_freq; if ( benchmark_timer_find_average_overhead == 1 ) { - return (int) total; + return (int) total; } else if ( total < LEAST_VALID ) { - return 0; + return 0; } /* diff --git a/c/src/lib/libcpu/arm/s3c2410/irq/irq.h b/c/src/lib/libcpu/arm/s3c2410/irq/irq.h index 78dd84de88..de3accbf71 100644 --- a/c/src/lib/libcpu/arm/s3c2410/irq/irq.h +++ b/c/src/lib/libcpu/arm/s3c2410/irq/irq.h @@ -23,7 +23,7 @@ extern "C" { /* * Include some preprocessor value also used by assember code */ - + #include <rtems.h> #include <s3c2410.h> @@ -40,34 +40,34 @@ extern void default_int_handler(); #define BSP_EINT4_7 4 #define BSP_EINT8_23 5 #define BSP_nBATT_FLT 7 -#define BSP_INT_TICK 8 -#define BSP_INT_WDT 9 -#define BSP_INT_TIMER0 10 -#define BSP_INT_TIMER1 11 -#define BSP_INT_TIMER2 12 -#define BSP_INT_TIMER3 13 -#define BSP_INT_TIMER4 14 -#define BSP_INT_UART2 15 -#define BSP_INT_LCD 16 -#define BSP_INT_DMA0 17 -#define BSP_INT_DMA1 18 -#define BSP_INT_DMA2 19 -#define BSP_INT_DMA3 20 -#define BSP_INT_SDI 21 -#define BSP_INT_SPI0 22 -#define BSP_INT_UART1 23 -#define BSP_INT_USBD 25 -#define BSP_INT_USBH 26 -#define BSP_INT_IIC 27 -#define BSP_INT_UART0 28 -#define BSP_INT_SPI1 29 -#define BSP_INT_RTC 30 -#define BSP_INT_ADC 31 -#define BSP_MAX_INT 32 +#define BSP_INT_TICK 8 +#define BSP_INT_WDT 9 +#define BSP_INT_TIMER0 10 +#define BSP_INT_TIMER1 11 +#define BSP_INT_TIMER2 12 +#define BSP_INT_TIMER3 13 +#define BSP_INT_TIMER4 14 +#define BSP_INT_UART2 15 +#define BSP_INT_LCD 16 +#define BSP_INT_DMA0 17 +#define BSP_INT_DMA1 18 +#define BSP_INT_DMA2 19 +#define BSP_INT_DMA3 20 +#define BSP_INT_SDI 21 +#define BSP_INT_SPI0 22 +#define BSP_INT_UART1 23 +#define BSP_INT_USBD 25 +#define BSP_INT_USBH 26 +#define BSP_INT_IIC 27 +#define BSP_INT_UART0 28 +#define BSP_INT_SPI1 29 +#define BSP_INT_RTC 30 +#define BSP_INT_ADC 31 +#define BSP_MAX_INT 32 extern void *bsp_vector_table; #define VECTOR_TABLE &bsp_vector_table - + /* * Type definition for RTEMS managed interrupts */ @@ -99,9 +99,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). @@ -176,7 +176,7 @@ void BSP_rtems_irq_mngt_init(); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); diff --git a/c/src/lib/libcpu/arm/shared/arm920/mmu.c b/c/src/lib/libcpu/arm/shared/arm920/mmu.c index 0158475e35..752314723d 100644 --- a/c/src/lib/libcpu/arm/shared/arm920/mmu.c +++ b/c/src/lib/libcpu/arm/shared/arm920/mmu.c @@ -108,9 +108,9 @@ void mmu_init(mmu_sect_map_t *map) while (sects > 0) { lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20, - MMU_SECT_AP_ALL, - 0, - c, + MMU_SECT_AP_ALL, + 0, + c, b); pbase++; vbase++; @@ -249,4 +249,4 @@ void mmu_set_cpu_async_mode(void) reg |= 0xc0000000; mmu_set_ctrl(reg); } - + diff --git a/c/src/lib/libcpu/bfin/cache/cache.c b/c/src/lib/libcpu/bfin/cache/cache.c index 992e12ffc9..c263890568 100644 --- a/c/src/lib/libcpu/bfin/cache/cache.c +++ b/c/src/lib/libcpu/bfin/cache/cache.c @@ -1,5 +1,5 @@ /* Blackfin Cache Support - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -9,7 +9,7 @@ * * $Id$ */ - + #include <rtems.h> #include <bsp.h> diff --git a/c/src/lib/libcpu/bfin/clock/clock.c b/c/src/lib/libcpu/bfin/clock/clock.c index 6ccab33e81..17df3246b1 100644 --- a/c/src/lib/libcpu/bfin/clock/clock.c +++ b/c/src/lib/libcpu/bfin/clock/clock.c @@ -1,5 +1,5 @@ /* RTEMS Clock Tick Driver for Blackfin. Uses Blackfin Core Timer. - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -9,7 +9,7 @@ * * $Id$ */ - + #include <rtems.h> #include <stdlib.h> diff --git a/c/src/lib/libcpu/bfin/clock/rtc.c b/c/src/lib/libcpu/bfin/clock/rtc.c index 5120a5efae..07ec729532 100644 --- a/c/src/lib/libcpu/bfin/clock/rtc.c +++ b/c/src/lib/libcpu/bfin/clock/rtc.c @@ -10,7 +10,7 @@ * * $Id$ */ - + #include <rtems.h> #include "tod.h" @@ -21,7 +21,7 @@ /* The following are inside RTEMS -- we are violating visibility!!! * Perhaps an API could be defined to get days since 1 Jan. - */ + */ extern const uint16_t _TOD_Days_to_date[2][13]; /* @@ -42,8 +42,8 @@ void setRealTimeFromRTEMS (void) { rtems_time_of_day time_buffer; rtems_status_code status; - - status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer ); + + status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer ); if (status == RTEMS_SUCCESSFUL){ setRealTime(&time_buffer); } @@ -56,9 +56,9 @@ void setRealTimeFromRTEMS (void) void setRealTimeToRTEMS (void) { rtems_time_of_day time_buffer; - - getRealTime(&time_buffer); - rtems_clock_set( &time_buffer ); + + getRealTime(&time_buffer); + rtems_clock_set( &time_buffer ); } /* @@ -70,16 +70,16 @@ int setRealTime( { uint32_t days; rtems_time_of_day tod_temp; - + tod_temp = *tod; - + days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \ _TOD_Days_to_date[0][tod_temp.month] + tod_temp.day - 1; if (tod_temp.month < 3) days += Leap_years_until_now (tod_temp.year - 1); else days += Leap_years_until_now (tod_temp.year); - + *((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)| (tod_temp.hour << RTC_STAT_HOURS_SHIFT)| (tod_temp.minute << RTC_STAT_MINUTES_SHIFT)| @@ -99,21 +99,21 @@ void getRealTime( uint32_t days, rtc_reg; rtems_time_of_day tod_temp = { 0, 0, 0 }; int n, Leap_year; - - rtc_reg = *((uint32_t volatile *)RTC_STAT); - + + rtc_reg = *((uint32_t volatile *)RTC_STAT); + days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1; - + /* finding year */ tod_temp.year = days/365 + TOD_BASE_YEAR; if (days%365 > Leap_years_until_now (tod_temp.year - 1)) { days = (days%365) - Leap_years_until_now (tod_temp.year - 1); - } else { + } else { tod_temp.year--; days = (days%365) + 365 - Leap_years_until_now (tod_temp.year - 1); } - /* finding month and day */ + /* finding month and day */ Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) || (!(tod_temp.year%400)))?1:0; for (n=1; n<=12; n++) { diff --git a/c/src/lib/libcpu/bfin/clock/tod.h b/c/src/lib/libcpu/bfin/clock/tod.h index 84e0d15383..6c4f8b39ce 100644 --- a/c/src/lib/libcpu/bfin/clock/tod.h +++ b/c/src/lib/libcpu/bfin/clock/tod.h @@ -1,5 +1,5 @@ /* tod.h - * + * * Real Time Clock definitions for eZKit533. * * Copyright (c) 2006 by Atos Automacao Industrial Ltda. @@ -11,7 +11,7 @@ * http://www.rtems.com/license/LICENSE. * * $Id$ - */ + */ #ifndef TOD_H diff --git a/c/src/lib/libcpu/bfin/include/sicRegs.h b/c/src/lib/libcpu/bfin/include/sicRegs.h index 56c19acd96..185bd5f09a 100644 --- a/c/src/lib/libcpu/bfin/include/sicRegs.h +++ b/c/src/lib/libcpu/bfin/include/sicRegs.h @@ -17,7 +17,7 @@ #define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) #define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) -#define SIC_IAR_PITCH 0x04 +#define SIC_IAR_PITCH 0x04 #define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) #if SIC_IAR_COUNT > 1 #define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) diff --git a/c/src/lib/libcpu/bfin/interrupt/interrupt.c b/c/src/lib/libcpu/bfin/interrupt/interrupt.c index 43cf33aea4..b8e353b048 100644 --- a/c/src/lib/libcpu/bfin/interrupt/interrupt.c +++ b/c/src/lib/libcpu/bfin/interrupt/interrupt.c @@ -1,5 +1,5 @@ /* Support for Blackfin interrupt controller - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -9,7 +9,7 @@ * * $Id$ */ - + #include <rtems.h> #include <rtems/libio.h> diff --git a/c/src/lib/libcpu/bfin/interrupt/interrupt.h b/c/src/lib/libcpu/bfin/interrupt/interrupt.h index 85de1f7dba..bf12258268 100644 --- a/c/src/lib/libcpu/bfin/interrupt/interrupt.h +++ b/c/src/lib/libcpu/bfin/interrupt/interrupt.h @@ -73,7 +73,7 @@ void bfin_interrupt_enable_all(int source, bool enable); /* disable a source independently of the individual ISR enables (starts out all enabled) */ void bfin_interrupt_enable_global(int source, bool enable); - + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.c b/c/src/lib/libcpu/bfin/mmu/mmu.c index b1a3c038f2..7cfd13958d 100644 --- a/c/src/lib/libcpu/bfin/mmu/mmu.c +++ b/c/src/lib/libcpu/bfin/mmu/mmu.c @@ -1,5 +1,5 @@ /* Blackfin MMU Support - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -9,7 +9,7 @@ * * $Id$ */ - + #include <rtems.h> diff --git a/c/src/lib/libcpu/bfin/serial/spi.c b/c/src/lib/libcpu/bfin/serial/spi.c index 42c2a5250f..471a607f2f 100644 --- a/c/src/lib/libcpu/bfin/serial/spi.c +++ b/c/src/lib/libcpu/bfin/serial/spi.c @@ -1,7 +1,7 @@ /* placeholder (just a shell) */ /* SPI driver for Blackfin - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -11,7 +11,7 @@ * * $Id$ */ - + #include <stdlib.h> #include <rtems.h> diff --git a/c/src/lib/libcpu/bfin/serial/spi.h b/c/src/lib/libcpu/bfin/serial/spi.h index 080d9b3571..a656f44c29 100644 --- a/c/src/lib/libcpu/bfin/serial/spi.h +++ b/c/src/lib/libcpu/bfin/serial/spi.h @@ -40,7 +40,7 @@ typedef struct { extern rtems_libi2c_bus_ops_t bfin_spi_libi2c_bus_ops; - + void bfin_spi_isr(int source); diff --git a/c/src/lib/libcpu/bfin/serial/twi.c b/c/src/lib/libcpu/bfin/serial/twi.c index 80abc52bf1..63b4a0999e 100644 --- a/c/src/lib/libcpu/bfin/serial/twi.c +++ b/c/src/lib/libcpu/bfin/serial/twi.c @@ -1,7 +1,7 @@ /* this is not much more than a shell; it does not do anything useful yet */ /* TWI (I2C) driver for Blackfin - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -11,7 +11,7 @@ * * $Id$ */ - + #include <stdlib.h> #include <rtems.h> @@ -49,9 +49,9 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) { if (channel < 0 || channel >= N_BFIN_TWI) return RTEMS_INVALID_NUMBER; - + base = config->base; - twi[channel].base = base; + twi[channel].base = base; result = rtems_semaphore_create(rtems_build_name('t','w','i','s'), 0, @@ -77,7 +77,7 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) { TWI_CONTROL_TWI_ENA; BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ? ((8 << TWI_CLKDIV_CLKHI_SHIFT) | - (17 << TWI_CLKDIV_CLKLOW_SHIFT)) : + (17 << TWI_CLKDIV_CLKLOW_SHIFT)) : ((33 << TWI_CLKDIV_CLKHI_SHIFT) | (67 << TWI_CLKDIV_CLKLOW_SHIFT)); BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; diff --git a/c/src/lib/libcpu/bfin/serial/uart.c b/c/src/lib/libcpu/bfin/serial/uart.c index 8637830e61..cb2c229322 100644 --- a/c/src/lib/libcpu/bfin/serial/uart.c +++ b/c/src/lib/libcpu/bfin/serial/uart.c @@ -1,5 +1,5 @@ /* UART driver for Blackfin - * + * * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * written by Allan Hessenflow <allanh@kallisti.com> * @@ -9,7 +9,7 @@ * * $Id$ */ - + #include <rtems.h> #include <rtems/libio.h> @@ -34,7 +34,7 @@ static void initializeHardware(int minor) { uint16_t r; base = uartsConfig->channels[minor].base_address; - + *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0; if (uartsConfig->channels[minor].force_baud) @@ -60,12 +60,12 @@ static void initializeHardware(int minor) { static int pollRead(int minor) { int c; char *base; - + base = uartsConfig->channels[minor].base_address; - + /* check to see if driver is using interrupts so this call will be harmless (though non-functional) in case some debug code tries to - use it */ + use it */ if (!uartsConfig->channels[minor].use_interrupts && *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR) c = *((uint16_t volatile *) (base + UART_RBR_OFFSET)); @@ -87,7 +87,7 @@ char bfin_uart_poll_read(int minor) { void bfin_uart_poll_write(int minor, char c) { char *base; - + base = uartsConfig->channels[minor].base_address; while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE)) @@ -158,7 +158,7 @@ static int pollWrite(int minor, const char *buf, int len) { static void enableInterrupts(int minor) { char *base; - + base = uartsConfig->channels[minor].base_address; *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI | diff --git a/c/src/lib/libcpu/bfin/serial/uart.h b/c/src/lib/libcpu/bfin/serial/uart.h index bac7cdcfa1..87e493bf6d 100644 --- a/c/src/lib/libcpu/bfin/serial/uart.h +++ b/c/src/lib/libcpu/bfin/serial/uart.h @@ -50,7 +50,7 @@ rtems_device_driver bfin_uart_open(rtems_device_major_number major, void bfin_uart_isr(int source); - + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libcpu/bfin/timer/timer.c b/c/src/lib/libcpu/bfin/timer/timer.c index f60ff57981..bb2c88514e 100644 --- a/c/src/lib/libcpu/bfin/timer/timer.c +++ b/c/src/lib/libcpu/bfin/timer/timer.c @@ -4,7 +4,7 @@ * Suite. Each measured time period is demarcated by calls to * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * the number of microseconds since benchmark_timer_initialize() exitted. - * + * * Copyright (c) 2006 by Atos Automacao Industrial Ltda. * written by Alain Schaefer <alain.schaefer@easc.ch> * and Antonio Giovanini <antonio@atos.com.br> @@ -15,7 +15,7 @@ * * $Id$ */ - + #include <rtems.h> #include <bsp.h> @@ -26,7 +26,7 @@ bool benchmark_timer_find_average_overhead; /* * benchmark_timer_initialize - * + * * Blackfin processor has a counter for clock cycles. */ void benchmark_timer_initialize( void ) @@ -40,7 +40,7 @@ void benchmark_timer_initialize( void ) asm ("R2 = SYSCFG;"); asm ("BITSET(R2,1);"); asm ("SYSCFG = R2"); - + } /* @@ -64,7 +64,7 @@ int benchmark_timer_read( void ) uint32_t total; register uint32_t cycles asm ("R2"); - /* stop counter */ + /* stop counter */ asm("R2 = SYSCFG;"); asm("BITCLR(R2,1);"); asm("SYSCFG = R2;"); @@ -74,7 +74,7 @@ int benchmark_timer_read( void ) clicks = cycles; /* Clock cycles */ /* converting to microseconds */ - total = clicks / (CCLK/1000000); + total = clicks / (CCLK/1000000); if ( benchmark_timer_find_average_overhead == 1 ) return total; /* in XXX microsecond units */ diff --git a/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c b/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c index 95b8842c7b..3ceb6639dd 100644 --- a/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c +++ b/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c @@ -28,7 +28,7 @@ * * Output parameters: NONE */ - + void *_CPU_Thread_Idle_body( uintptr_t ignored ) { #if defined(mcf5272) diff --git a/c/src/lib/libcpu/m68k/shared/misc/memProbe.c b/c/src/lib/libcpu/m68k/shared/misc/memProbe.c index 29160496d0..5c52911dff 100644 --- a/c/src/lib/libcpu/m68k/shared/misc/memProbe.c +++ b/c/src/lib/libcpu/m68k/shared/misc/memProbe.c @@ -1,4 +1,4 @@ -/* +/* * Address Probing for M68k/ColdFire */ diff --git a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h index 7f027119cf..5a489fa959 100644 --- a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h +++ b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005 by Cogent Computer Systems * Written by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -189,15 +189,15 @@ #define MEM_STADDR3 0x11003f00 /* - * SDCS0 - - * SDCS1 - - * SDCS2 - + * SDCS0 - + * SDCS1 - + * SDCS2 - */ #define MEM_SDMODE0 0x00552229 #define MEM_SDMODE1 0x00552229 #define MEM_SDMODE2 0x00552229 -#define MEM_SDADDR0 0x001003F8 +#define MEM_SDADDR0 0x001003F8 #define MEM_SDADDR1 0x001023F8 #define MEM_SDADDR2 0x001043F8 @@ -245,7 +245,7 @@ -#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) +#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) #define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) #define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) #define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) @@ -315,7 +315,7 @@ typedef struct { uint32_t _rsv0; uint32_t _rsv1; } au1x00_macdma_rx_t; - + typedef struct { volatile uint32_t stat; @@ -323,7 +323,7 @@ typedef struct { volatile uint32_t len; uint32_t _rsv0; } au1x00_macdma_tx_t; - + #define AU1X00_MAC_CTRL_RA (bit(31)) #define AU1X00_MAC_CTRL_EM (bit(30)) #define AU1X00_MAC_CTRL_DO (bit(23)) @@ -392,7 +392,7 @@ typedef struct { #define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) -#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) +#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) #define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) #define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) #define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) @@ -425,8 +425,8 @@ typedef struct { volatile uint32_t enable; } au1x00_uart_t; -extern au1x00_uart_t *uart0; -extern au1x00_uart_t *uart3; +extern au1x00_uart_t *uart0; +extern au1x00_uart_t *uart3; /* * Interrupt Vector Numbers diff --git a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c index f006a21999..6830656577 100644 --- a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c index f301567181..4d6da36da3 100644 --- a/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c @@ -1,9 +1,9 @@ /* - * Au1x00 Interrupt Vectoring + * Au1x00 Interrupt Vectoring * * Copyright (c) 2005 by Cogent Computer Systems * Written by Jay Monkman <jtm@lopingdog.com> - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -44,7 +44,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cause & 0x80 ) { unsigned long zero = 0; /* - * I don't see a good way to disable the compare + * I don't see a good way to disable the compare * interrupt, so let's just ignore it. */ asm volatile ("mtc0 %0, $11\n" :: "r" (zero)); @@ -56,23 +56,23 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cause & 0x40 ) { CALL_ISR( AU1X00_IRQ_PERF, frame ); } - + /* Interrupt controller 0 */ if ( cause & 0x0c ) { call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR); } - + /* Interrupt controller 1 */ if ( cause & 0x30 ) { call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR); } - + /* SW[0] */ if ( cause & 0x01 ) CALL_ISR( AU1X00_IRQ_SW0, frame ); - + /* SW[1] */ - if ( cause & 0x02 ) + if ( cause & 0x02 ) CALL_ISR( AU1X00_IRQ_SW1, frame ); } @@ -90,8 +90,8 @@ void mips_default_isr( int vector ) } static void call_vectored_isr( - CPU_Interrupt_frame *frame, - uint32_t cause, + CPU_Interrupt_frame *frame, + uint32_t cause, void *ctrlr ) { diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c index c2d170ba2e..54ab69d1e0 100644 --- a/c/src/lib/libcpu/mips/clock/ckinit.c +++ b/c/src/lib/libcpu/mips/clock/ckinit.c @@ -84,7 +84,7 @@ uint32_t Clock_isrs; /* ISRs until next tick */ /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -160,7 +160,7 @@ void Install_clock( * Hardware specific initialize goes here */ - mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * + mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_microsecond; mips_set_timer( mips_timer_rate ); mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK); @@ -195,13 +195,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/mips/clock/clock.S b/c/src/lib/libcpu/mips/clock/clock.S index cd535bdf63..de62337faa 100644 --- a/c/src/lib/libcpu/mips/clock/clock.S +++ b/c/src/lib/libcpu/mips/clock/clock.S @@ -1,4 +1,4 @@ -/* clock.s +/* clock.s * * This file contains the assembly code for the IDT 4650 clock driver. * diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c index 5b284bc463..af832cfdbd 100644 --- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c +++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c @@ -172,8 +172,8 @@ MG5UART_STATIC int mg5uart_set_attributes( cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); @@ -305,8 +305,8 @@ MG5UART_STATIC int mg5uart_open( MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); rtems_interrupt_enable(Irql); @@ -352,8 +352,8 @@ MG5UART_STATIC int mg5uart_close( rtems_interrupt_disable(Irql); cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); rtems_interrupt_enable(Irql); @@ -393,7 +393,7 @@ MG5UART_STATIC void mg5uart_write_polled( */ timeout = 2000; - while( --timeout ) + while( --timeout ) { status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; @@ -411,7 +411,7 @@ MG5UART_STATIC void mg5uart_write_polled( */ #if 0 - if(_System_state_Is_up(_System_state_Get())) + if(_System_state_Is_up(_System_state_Get())) { rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); } @@ -473,8 +473,8 @@ __ISR(rx_ready, MG5UART_IRQ_RX_READY) MG5UART_STATIC void mg5uart_process_isr_rx_error( - int minor, - uint32_t mask + int minor, + uint32_t mask ) { uint32_t pMG5UART; @@ -524,7 +524,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( { uint32_t pMG5UART; int shift; - + pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); @@ -533,7 +533,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( shift = MONGOOSEV_UART0_IRQ_SHIFT; else shift = MONGOOSEV_UART1_IRQ_SHIFT; - + MG5UART_SETREG( pMG5UART, MG5UART_STATUS_REGISTER, @@ -549,7 +549,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( * There are no more characters to transmit. The tx interrupts are be cleared * by writing data to the uart, so just disable the tx interrupt sources. */ - + Console_Port_Data[minor].bActive = FALSE; /* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */ @@ -659,7 +659,7 @@ MG5UART_STATIC int mg5uart_write_support_int( MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf); - if( Console_Port_Data[minor].bActive == FALSE ) + if( Console_Port_Data[minor].bActive == FALSE ) { Console_Port_Data[minor].bActive = TRUE; mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); @@ -690,7 +690,7 @@ MG5UART_STATIC int mg5uart_write_support_polled( /* * poll each byte in the string out of the port. */ - while (nwrite < len) + while (nwrite < len) { mg5uart_write_polled(minor, *buf++); nwrite++; @@ -734,11 +734,11 @@ MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled( status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; } - if ( status & MONGOOSEV_UART_RX_READY ) + if ( status & MONGOOSEV_UART_RX_READY ) { return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); - } - else + } + else { return -1; } diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c index b81d851fb2..316896665a 100644 --- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c +++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c @@ -20,13 +20,13 @@ #ifndef _MG5UART_MULTIPLIER #define _MG5UART_MULTIPLIER 1 #define _MG5UART_NAME(_X) _X -#define _MG5UART_TYPE uint32_t +#define _MG5UART_TYPE uint32_t #endif #define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \ (_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER )) -/* +/* * MG5UART Get Register Routine */ diff --git a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h index 57fa593a91..b4e6403b6f 100644 --- a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h +++ b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @@ -122,10 +122,10 @@ #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F -/* - * The Peripheral Interrupt Status, Cause, and Mask registers have the - * same bit assignments although some revisions of the document have - * the Cause and Status registers incorrect. +/* + * The Peripheral Interrupt Status, Cause, and Mask registers have the + * same bit assignments although some revisions of the document have + * the Cause and Status registers incorrect. */ #define MONGOOSEV_UART0_IRQ_SHIFT 11 @@ -193,7 +193,7 @@ ** Peripheral Command bits (non-uart, those are defined above) */ #define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT -#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT +#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c index 6f40a79df9..6933eb7553 100644 --- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). @@ -17,9 +17,9 @@ */ /* - * The Synova Mongoose-V attached one of the eight interrupt bits + * The Synova Mongoose-V attached one of the eight interrupt bits * to a Peripheral Function Interrupt Cause Register on-CPU. - * This results in: 2 software interrupts, 5 interrupts + * This results in: 2 software interrupts, 5 interrupts * through the IP bits, and 32 more from the PFICR. Some of * these are reserved but for simplicity in processing, we * reserve slots for those bits anyway. diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c index ba1499433d..421f95da58 100644 --- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c @@ -91,7 +91,7 @@ int assertSoftwareInterrupt( uint32_t n ) static volatile uint32_t _ivcause, _ivsr; -static uint32_t READ_CAUSE(void) +static uint32_t READ_CAUSE(void) { mips_get_cause( _ivcause ); _ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */ @@ -140,7 +140,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cshifted & 0x01 ) /* SW[0] */ { CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); - } + } if ( cshifted & 0x02 ) /* SW[1] */ { CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); @@ -156,7 +156,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x4 ); if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect; } - + if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ { SET_ISR_FLAG( 0x8 ); @@ -164,7 +164,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x8 ); if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect; } - + if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ { SET_ISR_FLAG( 0x10 ); @@ -172,7 +172,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x10 ); if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect; } - + if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ { SET_ISR_FLAG( 0x20 ); @@ -180,7 +180,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x20 ); if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect; } - + if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ { SET_ISR_FLAG( 0x40 ); @@ -198,7 +198,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); /* - for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) + for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) { if ( pf_icr & pf_mask ) { @@ -208,7 +208,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) pf_reset |= pf_mask; if( (cshifted = READ_CAUSE()) & 0xff ) break; } - } + } */ /* @@ -217,7 +217,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) * way thru a full 32 bits. pf_mask shifts left 8 bits at a time * to serve as a interrupt cause test mask. */ - for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) + for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) { if ( pf_icr & pf_mask ) { diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c index 86cd89f8d3..c7ef845e60 100644 --- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c index d72273c582..79c509ca21 100644 --- a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c index 070884228b..511b8fe4c4 100644 --- a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * RM5231 Interrupt Vectoring + * RM5231 Interrupt Vectoring * * vectorisrs.c,v 1.6 2004/06/23 18:16:36 */ diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S index 89fc538e49..6c1f4a1637 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S +++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S @@ -32,7 +32,7 @@ FRAME(exc_dbg_code,sp,0,ra) j k0 nop ENDFRAME(exc_dbg_code) - + /* XXX this is dependent on IDT/SIM and needs to be addressed */ FRAME(exc_utlb_code,sp,0,ra) la k0, (R_VEC+((48)*8)) @@ -40,7 +40,7 @@ FRAME(exc_utlb_code,sp,0,ra) nop ENDFRAME(exc_utlb_code) -/* +/* * MIPS ISA Level 32 * XXX Again, reliance on SIM. Not good.?????????? */ @@ -69,8 +69,8 @@ FRAME(exc_norm_code,sp,0,ra) j k0 nop ENDFRAME(exc_norm_code) - -/* + +/* * MIPS ISA Level 3 * XXX Again, reliance on SIM. Not good. */ diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c index c3e41251eb..5a4fb9ca73 100644 --- a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c index dae7aa2b32..a5b4e182eb 100644 --- a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * TX3904 Interrupt Vectoring + * TX3904 Interrupt Vectoring * * $Id$ */ @@ -38,7 +38,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) unsigned int v = (cause >> 2) & 0x0f; CALL_ISR( MIPS_INTERRUPT_BASE + v, frame ); } - + if ( cause & 0x02 ) /* SW[0] */ CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame ); diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4925.h b/c/src/lib/libcpu/mips/tx49/include/tx4925.h index 38985e5fe4..a55107b8c1 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4925.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4925.h @@ -26,7 +26,7 @@ #define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */ /* Pin Configuration register bits */ -#define SELCHI 0x00100000 +#define SELCHI 0x00100000 #define SELTMR0 0x00000200 @@ -64,7 +64,7 @@ #define TWIS 0x8 -/* +/* * Interrupt Controller Registers */ #define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4938.h b/c/src/lib/libcpu/mips/tx49/include/tx4938.h index 2f2b340937..3264784ddd 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4938.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4938.h @@ -41,7 +41,7 @@ #define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */ /* Pin Configuration register bits */ -#define SELCHI 0x00100000 +#define SELCHI 0x00100000 #define SELTMR0 0x00000200 @@ -79,7 +79,7 @@ #define TWIS 0x8 -/* +/* * Interrupt Controller Registers */ #define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c index 43fa34f8d1..e56989a297 100644 --- a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c index b43e08dbf0..1f6b811224 100644 --- a/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * TX4925 Interrupt Vectoring + * TX4925 Interrupt Vectoring * * vectorisrs.c,v 1.6 2004/06/23 18:16:36 */ @@ -35,7 +35,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f; CALL_ISR( MIPS_INTERRUPT_BASE + v, frame ); } - + if ( pending & 0x01 ) /* IP[0] */ CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame ); @@ -53,9 +53,9 @@ void mips_default_isr( int vector ) printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr ); - + while(1); /* Lock it up */ - + rtems_fatal_error_occurred(1); } diff --git a/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h b/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h index 3907a26674..286cd65bd4 100644 --- a/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h +++ b/c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h @@ -7,19 +7,19 @@ * is not very useful so we mostly focus on TLB1 (variable page size) */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -28,18 +28,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -48,9 +48,9 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ + */ #include <rtems.h> #include <inttypes.h> @@ -98,7 +98,7 @@ extern E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16]; void rtems_e500_dmptlbc(FILE *f); -/* +/* * Read a TLB entry from the hardware; if it is a TLB1 entry * then the current settings are stored in the * rtems_e500_tlb_va_cache[] structure. diff --git a/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c b/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c index ff0e42821a..6782629a87 100644 --- a/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c @@ -15,23 +15,23 @@ * (the 7 LSBs, that is) can be mapped with TLB0 since there * are only two entries per 'way'. * - * Since this is a real-time OS we want to stay away from + * Since this is a real-time OS we want to stay away from * software TLB replacement. */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -40,18 +40,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -60,9 +60,9 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ + */ /* 8450 MSR definitions; note that there are *substantial* differences * compared to classic powerpc; in particular, IS/DS are *different* @@ -230,8 +230,8 @@ int i; return; } for ( i=0; i<16; i++ ) { - if ( !rtems_e500_tlb_va_cache[i].att.v ) - continue; + if ( !rtems_e500_tlb_va_cache[i].att.v ) + continue; myprintf(f,"#%2i: TID 0x%03x, TS %i, ea 0x%08x .. 0x%08x\n", i, rtems_e500_tlb_va_cache[i].va.va_tid, @@ -259,7 +259,7 @@ int idx = key & ~E500_SELTLB_1; } } -/* +/* * Read a TLB entry from the hardware; if it is a TLB1 entry * then the current settings are stored in the * rtems_e500_tlb_va_cache[] structure. @@ -500,7 +500,7 @@ rtems_interrupt_level lvl; /* OK to proceed */ mas1 |= MAS1_IPROT | MAS1_TID(tid); - if ( sz >= 0 ) + if ( sz >= 0 ) mas1 |= MAS1_V | MAS1_TSIZE(sz); mas2 = MAS2_EPN( ea>>12 ) | E500_TLB_ATTR_WIMGE(attr); @@ -668,11 +668,11 @@ rtems_interrupt_level lvl; if ( (key & E500_SELTLB_1) ) { if ( (key & ~E500_SELTLB_1) > 15 ) { myprintf(stderr,"Invalid TLB index; TLB1 index must be < 16\n"); - return -1; + return -1; } } else if ( key > 255 ) { myprintf(stderr,"Invalid TLB index; TLB0 index must be < 256\n"); - return -1; + return -1; } /* Must not invalidate page 0 which holds vectors, text etc... */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c b/c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c index 8181c65cca..78127de5ad 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c @@ -190,7 +190,7 @@ static int mpc55xx_esci_termios_first_open( int major, int minor, void *arg) } /* Connect TTY */ - e->tty = tty; + e->tty = tty; /* Enable interrupts */ if (MPC55XX_ESCI_USE_INTERRUPTS( e)) { @@ -380,7 +380,7 @@ static int mpc55xx_esci_termios_set_attributes( int minor, const struct termios br = 0; } cr1.B.SBR = br; - + /* Number of data bits */ if ((t->c_cflag & CSIZE) != CS8) { return RTEMS_IO_ERROR; @@ -390,7 +390,7 @@ static int mpc55xx_esci_termios_set_attributes( int minor, const struct termios /* Parity */ cr1.B.PE = (t->c_cflag & PARENB) ? 1 : 0; cr1.B.PT = (t->c_cflag & PARODD) ? 1 : 0; - + /* Stop bits */ if ( t->c_cflag & CSTOPB ) { /* Two stop bits */ @@ -484,11 +484,11 @@ static const rtems_termios_callbacks mpc55xx_esci_termios_callbacks_polled = { rtems_device_driver console_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *arg) { rtems_status_code sc = RTEMS_SUCCESSFUL; - int console_done = 0; - int termios_do_init = 1; + int console_done = 0; + int termios_do_init = 1; rtems_device_minor_number i = 0; mpc55xx_esci_driver_entry *e = NULL; - + for (i = 0; i < MPC55XX_ESCI_NUMBER; ++i) { e = &mpc55xx_esci_driver_table [i]; sc = rtems_io_register_name ( e->device_name, major, i); diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h index fd4b7fe414..7134dbe793 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h @@ -18,9 +18,9 @@ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. */ -/** +/** * @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI) - * + * * @ingroup mpc55xx */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h index b6df13d332..3066f23a3a 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h @@ -18,9 +18,9 @@ * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. */ -/** +/** * @defgroup mpc55xx_esci Enhanced Serial Communication Interface (eSCI). - * + * * @ingroup mpc55xx */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h index 5aa0d9080b..c81e0231e7 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h @@ -22,11 +22,11 @@ * @defgroup mpc55xx BSP for MPC55xx boards */ -/** +/** * @defgroup mpc55xx_config Configuration files - * + * * @ingroup mpc55xx - * + * * Makefiles, configure scripts etc. */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h index acee4face9..843c3c1c3a 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h +++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h @@ -2809,7 +2809,7 @@ extern "C" { .DADDR = 0, .CDF = { .R = 0 }, .DLAST_SGA = 0, - .BMF = { .R = 0 } + .BMF = { .R = 0 } }; #define EDMA_TCD_BITER_MASK 0x7fff diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c b/c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c index 1de4f7e6b3..be766ef5ed 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c +++ b/c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c @@ -41,7 +41,7 @@ rtems_status_code mpc55xx_intc_get_priority( rtems_vector_number vector, unsigne } else { *priority = MPC55XX_INTC_INVALID_PRIORITY; return RTEMS_INVALID_NUMBER; - } + } } /** @@ -58,7 +58,7 @@ rtems_status_code mpc55xx_intc_set_priority( rtems_vector_number vector, unsigne } } else { return RTEMS_INVALID_NUMBER; - } + } } /** @@ -71,7 +71,7 @@ rtems_status_code mpc55xx_intc_raise_software_irq( rtems_vector_number vector) return RTEMS_SUCCESSFUL; } else { return RTEMS_INVALID_NUMBER; - } + } } /** @@ -84,7 +84,7 @@ rtems_status_code mpc55xx_intc_clear_software_irq( rtems_vector_number vector) return RTEMS_SUCCESSFUL; } else { return RTEMS_INVALID_NUMBER; - } + } } /** diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S b/c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S index ef529d6e4b..279620346b 100644 --- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S +++ b/c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S @@ -95,7 +95,7 @@ zero_big_data: evstddx r0, r3, r8 addi r8, r8, 32 bdnz zero_big_data - + /* Return */ blr @@ -145,6 +145,6 @@ zero_big_line: dcbz r3, r8 addi r8, r8, 128 bdnz zero_big_line - + /* Return */ blr diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c index bdb915fb29..6fedc70bd8 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c @@ -58,10 +58,10 @@ void Clock_exit( void ); /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + /* * ISR Handler */ @@ -70,7 +70,7 @@ rtems_isr Clock_isr(rtems_vector_number vector) usiu.piscrk = USIU_UNLOCK_KEY; usiu.piscr |= USIU_PISCR_PS; /* acknowledge interrupt */ usiu.piscrk = 0; - + Clock_driver_ticks++; rtems_clock_tick(); } @@ -81,10 +81,10 @@ void clockOn(void* unused) uint32_t pit_value; extern uint32_t bsp_clicks_per_usec; - /* calculate and set modulus */ + /* calculate and set modulus */ pit_value = (rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec) - 1 ; - + if (pit_value > 0xffff) { /* pit is only 16 bits long */ rtems_fatal_error_occurred(-1); } @@ -114,13 +114,13 @@ clockOff(void* unused) { /* disable PIT and PIT interrupts */ usiu.piscrk = USIU_UNLOCK_KEY; - usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); + usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); usiu.piscrk = 0; } int clockIsOn(void* unused) { - if (usiu.piscr & USIU_PISCR_PIE) + if (usiu.piscr & USIU_PISCR_PIE) return 1; return 0; } @@ -157,13 +157,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c index 43c371248f..19072a3781 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c @@ -14,7 +14,7 @@ * MPC5xx port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * - * Derived from + * Derived from * c/src/lib/libcpu/powerpc/mpc8xx/console_generic/console_generic.c: * Author: Jay Monkman (jmonkman@frasca.com) * Copyright (C) 1998 by Frasca International, Inc. @@ -84,15 +84,15 @@ static struct termios default_termios = { { 0 } /* control characters */ }; - + /* * Termios callback functions */ int m5xx_uart_firstOpen( - int major, - int minor, + int major, + int minor, void *arg ) { @@ -109,7 +109,7 @@ m5xx_uart_firstOpen( int m5xx_uart_lastClose( - int major, + int major, int minor, void* arg ) @@ -129,7 +129,7 @@ m5xx_uart_pollRead( { volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs; int c = -1; - + if ( regs ) { while ( (regs->scsr & QSMCM_SCI_RDRF) == 0 ) ; @@ -139,7 +139,7 @@ m5xx_uart_pollRead( return c; } -int +int m5xx_uart_write( int minor, const char *buf, @@ -170,7 +170,7 @@ m5xx_uart_pollWrite( return 0; } -int +int m5xx_uart_setAttributes( int minor, const struct termios *t @@ -179,11 +179,11 @@ m5xx_uart_setAttributes( uint16_t sccr0 = sci_descs[minor].regs->sccr0; uint16_t sccr1 = sci_descs[minor].regs->sccr1; int baud; - + /* * Check that port number is valid */ - if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) + if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) return RTEMS_INVALID_NUMBER; /* Baud rate */ @@ -212,10 +212,10 @@ m5xx_uart_setAttributes( if (baud > 0) { extern uint32_t bsp_clock_speed; sccr0 &= ~QSMCM_SCI_BAUD(-1); - sccr0 |= + sccr0 |= QSMCM_SCI_BAUD((bsp_clock_speed + (16 * baud)) / (32 * baud)); } - + /* Number of data bits -- not available with MPC5xx SCI */ switch ( t->c_cflag & CSIZE ) { case CS5: break; @@ -236,7 +236,7 @@ m5xx_uart_setAttributes( sccr1 |= QSMCM_SCI_PE; else sccr1 &= ~QSMCM_SCI_PE; - + if ( t->c_cflag & PARODD ) sccr1 |= QSMCM_SCI_PT; else @@ -248,29 +248,29 @@ m5xx_uart_setAttributes( sccr1 |= QSMCM_SCI_RE; else sccr1 &= ~QSMCM_SCI_RE; - + /* Write hardware registers */ sci_descs[minor].regs->sccr0 = sccr0; sci_descs[minor].regs->sccr1 = sccr1; - + return RTEMS_SUCCESSFUL; } -/* +/* * Interrupt handling. */ static void m5xx_sci_interrupt_handler (rtems_irq_hdl_param unused) { int minor; - + for ( minor = 0; minor < NUM_PORTS; minor++ ) { sci_desc *desc = &sci_descs[minor]; int sccr1 = desc->regs->sccr1; int scsr = desc->regs->scsr; - - /* + + /* * Character received? */ if ((sccr1 & QSMCM_SCI_RIE) && (scsr & QSMCM_SCI_RDRF)) { @@ -306,14 +306,14 @@ m5xx_uart_initialize (int minor) /* * Check that minor number is valid. */ - if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) + if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) return; /* * Configure and enable receiver and transmitter. */ m5xx_uart_setAttributes(minor, &default_termios); - + /* * Connect interrupt if not yet done. */ @@ -325,7 +325,7 @@ m5xx_uart_initialize (int minor) irq_data.on = m5xx_sci_nop; /* can't enable both channels here */ irq_data.off = m5xx_sci_nop; /* can't disable both channels here */ irq_data.isOn = m5xx_sci_isOn; - + if (!CPU_install_rtems_irq_handler (&irq_data)) { printk("Unable to connect SCI Irq handler\n"); rtems_fatal_error_occurred(1); diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c index 7c131cc7b7..d88e9787ac 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c @@ -61,7 +61,7 @@ int mpc5xx_vector_is_valid(rtems_vector vector) case ASM_MEBREAK_VECTOR: case ASM_NMEBREAK_VECTOR: return 1; - default: + default: return 0; } default: @@ -85,19 +85,19 @@ int mpc5xx_set_exception (const rtems_raw_except_connect_data* except) * RATIONALE : to always have the same transition by forcing the user * to get the previous handler before accepting to disconnect. */ - if (exception_handler_table[except->exceptIndex] != + if (exception_handler_table[except->exceptIndex] != default_raw_except_entry.hdl.raw_hdl) { return 0; } rtems_interrupt_disable(level); - + raw_except_table[except->exceptIndex] = *except; exception_handler_table[except->exceptIndex] = except->hdl.raw_hdl; if (except->on) except->on(except); - + rtems_interrupt_enable(level); return 1; } @@ -107,16 +107,16 @@ int mpc5xx_get_current_exception (rtems_raw_except_connect_data* except) if (!mpc5xx_vector_is_valid(except->exceptIndex)){ return 0; } - + *except = raw_except_table[except->exceptIndex]; - + return 1; } int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except) { rtems_interrupt_level level; - + if (!mpc5xx_vector_is_valid(except->exceptIndex)){ return 0; } @@ -135,14 +135,14 @@ int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except) if (except->off) except->off(except); - exception_handler_table[except->exceptIndex] = + exception_handler_table[except->exceptIndex] = default_raw_except_entry.hdl.raw_hdl; - + raw_except_table[except->exceptIndex] = default_raw_except_entry; raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex; rtems_interrupt_enable(level); - + return 1; } @@ -156,7 +156,7 @@ int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config) { unsigned i; rtems_interrupt_level level; - + /* * store various accelerators */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h index 6d8f7e2714..8388a4d4bc 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h @@ -62,7 +62,7 @@ #ifndef ASM /* - * Type definition for raw exceptions. + * Type definition for raw exceptions. */ typedef unsigned char rtems_vector; @@ -73,7 +73,7 @@ typedef struct { rtems_vector vector; rtems_exception_handler_t* raw_hdl; }rtems_raw_except_hdl; - + typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); @@ -93,16 +93,16 @@ typedef struct __rtems_raw_except_connect_data__{ * libcpu library, this library should have no knowledge of * board specific hardware to manage exceptions and thus the * "on" routine must enable the except at processor level only. - * + * */ - rtems_raw_except_enable on; + rtems_raw_except_enable on; /* * function for disabling raw exceptions. In order to be consistent * with the fact that the raw connexion can defined in the * libcpu library, this library should have no knowledge of * board specific hardware to manage exceptions and thus the * "on" routine must disable the except both at device and PIC level. - * + * */ rtems_raw_except_disable off; /* diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h index 9c933ffb6b..027754b709 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h @@ -8,7 +8,7 @@ * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h index a2c34a3141..8edeaa186e 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h @@ -44,7 +44,7 @@ * * * Corrections/additions: * * Copyright (c) 1999, National Research Council of Canada * - * + * * MPC5xx port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * @@ -340,14 +340,14 @@ do { \ #define UIMB_UMCR_STOP (1<<31) #define UIMB_UMCR_IRQMUX(x) ((x)<<29) #define UIMB_UMCR_HSPEED (1<<28) - + /* ************************************************************************* * QSMCM Serial Communications Interface (SCI) * ************************************************************************* */ - - + + #define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ #define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ @@ -417,7 +417,7 @@ typedef struct usiu_ { uint8_t _pad71[0x03C-0x034]; uint32_t pdmcr; uint8_t _pad2[0x100-0x40]; - + /* * MEMC Block */ @@ -428,7 +428,7 @@ typedef struct usiu_ { uint8_t _pad8[0x178-0x148]; uint16_t mstat; uint8_t _pad9[0x200-0x17A]; - + /* * System integration timers */ @@ -450,7 +450,7 @@ typedef struct usiu_ { uint16_t pitr; uint16_t _pad_14_2; uint8_t _pad15[0x280-0x24c]; - + /* * Clocks and Reset */ @@ -462,7 +462,7 @@ typedef struct usiu_ { uint16_t _pad73; uint16_t vsrmcr; uint8_t _pad16[0x300-0x292]; - + /* * System integration timers keys */ @@ -479,7 +479,7 @@ typedef struct usiu_ { uint32_t piscrk; uint32_t pitck; uint8_t _pad19[0x380-0x348]; - + /* * Clocks and Reset Keys */ @@ -541,7 +541,7 @@ typedef struct m5xxSPIRegisters_ { /* * Queued Serial Multi-Channel Module (QSMCM) - */ + */ typedef struct m5xxQSMCMRegisters_ { uint16_t qsmcmmcr; uint16_t qtest; diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c index c109bc35b2..443340a914 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c @@ -16,7 +16,7 @@ * * $Id$ */ - + #include <rtems.h> #include <rtems/score/apiext.h> #include <mpc5xx.h> @@ -28,12 +28,12 @@ * Convert an rtems_irq_number constant to an interrupt level * suitable for programming into an I/O device's interrupt level field. */ - + int CPU_irq_level_from_symbolic_name(const rtems_irq_number name) { if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7) return (name - CPU_USIU_EXT_IRQ_0) / 2; - + if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31) return 8 + (name - CPU_UIMB_IRQ_8); @@ -84,9 +84,9 @@ static inline int is_proc_irq(const rtems_irq_number irqLine) /* - * Masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * Masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int USIU_IvectMask[CPU_USIU_IRQ_COUNT] = @@ -134,7 +134,7 @@ static void compute_USIU_IvectMask_from_prio () */ static int isValidInterrupt(int irq) { - if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) + if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) || (irq == CPU_UIMB_INTERRUPT) ) return 0; return 1; @@ -164,7 +164,7 @@ int CPU_irq_enabled_at_uimb(const rtems_irq_number irqLine) int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine) { int usiu_irq_index; - + if (!is_usiu_irq(irqLine)) return 1; @@ -181,7 +181,7 @@ int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine) if (!is_usiu_irq(irqLine)) return 1; - + usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index)); usiu.simask = ppc_cached_irq_mask; @@ -207,7 +207,7 @@ int CPU_irq_enabled_at_usiu(const rtems_irq_number irqLine) int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -228,14 +228,14 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_uimb_irq(irq->name)) { /* * Enable interrupt at UIMB level */ CPU_irq_enable_at_uimb (irq->name); } - + if (is_usiu_irq(irq->name)) { /* * Enable interrupt at USIU level @@ -254,7 +254,7 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) */ if (irq->on) irq->on(irq); - + rtems_interrupt_enable(level); return 1; @@ -273,7 +273,7 @@ int CPU_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -311,7 +311,7 @@ int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * restore the default irq value @@ -424,7 +424,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[CPU_DECREMENTER].hdl(rtems_hdl_tbl[CPU_DECREMENTER].handle); _CPU_MSR_SET(msr); @@ -448,20 +448,20 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * interrupts. */ usiu.sipend = (1 << (31 - irq)); - + if (uimbIntr) { /* * Look at the bits set in the UIMB interrupt-pending register. The - * highest-order set bit indicates the handler we will run. + * highest-order set bit indicates the handler we will run. * * Unfortunately, we can't easily mask individual UIMB interrupts * unless they use USIU levels 0 to 6, so we must mask all low-level * (level > 7) UIMB interrupts while we service any interrupt. */ int uipend = imb.uimb.uipend << 8; - + if (uipend == 0) { /* spurious interrupt? use last vector */ - irq = CPU_UIMB_IRQ_MAX_OFFSET; + irq = CPU_UIMB_IRQ_MAX_OFFSET; } else { irq = CPU_UIMB_IRQ_MIN_OFFSET; @@ -473,7 +473,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); _CPU_MSR_SET(msr); @@ -482,7 +482,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) usiu.simask = ppc_cached_irq_mask; } } - + void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) { /* diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h index 6086db8e65..87c6593e10 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h @@ -1,4 +1,4 @@ -/* +/* * irq.h * * This include file describe the data structure and the functions implemented @@ -40,8 +40,8 @@ extern volatile unsigned int ppc_cached_irq_mask; * Symblolic IRQ names and related definitions. */ - /* - * Base vector for our USIU IRQ handlers. + /* + * Base vector for our USIU IRQ handlers. */ #define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) /* @@ -71,7 +71,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) /* * USIU IRQ symbolic name definitions. - */ + */ #define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) #define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) @@ -80,19 +80,19 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) #define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) - + #define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) #define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) - + #define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) #define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) #define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) #define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) - + #define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) #define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) - + #define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) #define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) @@ -101,7 +101,7 @@ extern volatile unsigned int ppc_cached_irq_mask; */ #define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) #define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) - + /* * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to * the USIU interrupts of the same number, because they are detected in @@ -140,7 +140,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) #define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) #define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) - + /* * Symbolic names for UIMB interrupt sources. */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S index 9271a83f1d..cf79c13ed9 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S @@ -1,7 +1,7 @@ /* * irq_asm.S * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -23,7 +23,7 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <libcpu/vectors.h> @@ -33,7 +33,7 @@ #define SYNC \ sync; \ isync - + /* * Common handler for interrupt exceptions. * @@ -46,22 +46,22 @@ * LR have been saved. R4 holds the exception number. */ PUBLIC_VAR(C_dispatch_irq_handler) - + PUBLIC_VAR(dispatch_irq_handler) SYM (dispatch_irq_handler): /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to re-enable exception processing. - * + * * Note that R2 should never change (it's the EABI pointer to - * .sdata2), but we save it just in case. + * .sdata2), but we save it just in case. */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r3, SRR1_FRAME_OFFSET(r1) @@ -93,11 +93,11 @@ SYM (dispatch_irq_handler): mfcr r5 mfctr r6 mfxer r7 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) - + /* * Add some non volatile registers to store information that will be * used when returning from C handler. @@ -128,9 +128,9 @@ SYM (dispatch_irq_handler): bne nested mfspr r1, SPRG1 /* switch to interrupt stack */ -nested: +nested: - /* + /* * Start Incrementing nesting level in R3 */ addi r3, r3, 1 @@ -153,11 +153,11 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* - * Call C exception handler for decrementer or external interrupt. + * Call C exception handler for decrementer or external interrupt. * Pass frame along just in case.. * * C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) @@ -166,7 +166,7 @@ nested: bl C_dispatch_irq_handler /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -187,7 +187,7 @@ nested: cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -196,14 +196,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lbz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lbz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -241,12 +241,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -260,22 +260,22 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -283,7 +283,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c index 9f2488a012..009443cca2 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c @@ -1,4 +1,4 @@ -/* +/* * irq_init.c * * This file contains the implementation of rtems initialization @@ -90,7 +90,7 @@ void CPU_USIU_irq_init() usiu.siel = usiu.siel; } -/* +/* * Initialize UIMB interrupt management */ void @@ -102,7 +102,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + CPU_USIU_irq_init(); CPU_UIMB_irq_init(); /* @@ -130,7 +130,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c index 98460cafea..7aa0c6be92 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c @@ -75,7 +75,7 @@ void benchmark_timer_initialize(void) | USIU_TBSCR_TBF /* freeze timebase during debug */ | USIU_TBSCR_TBE; /* enable timebase */ usiu.tbscrk = 0; - + Timer_starting = get_itimer(); } diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S index 2177186969..7dc3434c57 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S @@ -14,7 +14,7 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <libcpu/vectors.h> @@ -22,7 +22,7 @@ #define SYNC \ sync; \ isync - + /* * Hardware exception vector table. @@ -92,7 +92,7 @@ common_prologue: lwz r3, 0(r3) /* get entry */ mtlr r3 /* run it */ blr - + /* * Default exception handler. @@ -106,7 +106,7 @@ common_prologue: * LR have been saved. R4 holds the exception number. */ .text - + PUBLIC_VAR(default_exception_handler) SYM (default_exception_handler): /* @@ -129,7 +129,7 @@ SYM (default_exception_handler): * the frame. * * Note that R2 should never change (it's the EABI pointer to - * .sdata2), but we save it just in case. + * .sdata2), but we save it just in case. * * Recall that R3 and R4 were saved by the specific- and * common-exception handlers before entry to this routine. @@ -153,7 +153,7 @@ SYM (default_exception_handler): /* * Call C-language portion of the default exception handler, passing - * in the address of the frame. + * in the address of the frame. * * To simplify things a bit, we assume that the target routine is * within +/- 32 Mbyte from here, which is a reasonable assumption @@ -192,7 +192,7 @@ SYM (default_exception_handler): mtsrr1 r0 lwz r0, SRR0_FRAME_OFFSET(r1) mtsrr0 r0 - + /* * Restore the final GPR, close the stack frame, and return to the * interrupted code. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h index 53ae416969..438562a8a3 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -28,10 +28,10 @@ #define NUM_EXCEPTIONS 0x20 /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -140,7 +140,7 @@ typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr); /* * Exception handler table. * - * This table contains pointers to assembly-language exception handlers. + * This table contains pointers to assembly-language exception handlers. * The common exception prologue in vectors.S looks up an entry in this * table and jumps to it. No return address is saved, so the handlers in * this table must return directly to the interrupted code. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c index e5314ee50a..66bc729852 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -32,7 +32,7 @@ rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS]; void C_default_exception_handler(CPU_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -76,7 +76,7 @@ void C_default_exception_handler(CPU_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c index ebf306a3e9..0f7fe86ef0 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c @@ -54,7 +54,7 @@ uint32_t Clock_Decrementer_value; /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -214,12 +214,12 @@ void Clock_exit( void ) { (void) BSP_disconnect_clock_handler (); } - + uint32_t Clock_driver_nanoseconds_since_last_tick(void) { uint32_t clicks, tmp; - PPC_Get_decrementer( clicks ); + PPC_Get_decrementer( clicks ); /* * Multiply by 1000 here separately from below so we do not overflow @@ -257,7 +257,7 @@ rtems_interrupt_level l,tcr; Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)* (rtems_configuration_get_microseconds_per_tick()/1000); - /* set the decrementer now, prior to installing the handler + /* set the decrementer now, prior to installing the handler * so no interrupts will happen in a while. */ PPC_Set_decrementer( (unsigned)-1 ); @@ -298,7 +298,7 @@ rtems_interrupt_level l,tcr; rtems_fatal_error_occurred(1); } /* make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S index 30bda4face..34fc13092e 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S +++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S @@ -25,11 +25,11 @@ codemove: beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f - + la r8,-4(r4) la r7,-4(r3) 1: lwzu r0,4(r8) - stwu r0,4(r7) + stwu r0,4(r7) bdnz 1b b 4f @@ -39,23 +39,23 @@ codemove: 3: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b - + /* Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. + * address. Otherwise we might miss one cache line. */ 4: cmpwi r6,0 add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ + beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mr r4,r3 -5: cmplw r4,r5 +5: cmplw r4,r5 dcbst 0,r4 add r4,r4,r6 blt 5b sync /* Wait for all dcbst to complete on bus */ mr r4,r3 -6: cmplw r4,r5 +6: cmplw r4,r5 icbi 0,r4 add r4,r4,r6 blt 6b diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c index 0c85143c5d..f5119800fb 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c @@ -6,7 +6,7 @@ * More detailed information can be found on motorola * site and more precisely in the following book : * - * MPC750 + * MPC750 * Risc Microporcessor User's Manual * Mtorola REF : MPC750UM/AD 8/97 * @@ -380,7 +380,7 @@ setbat (int typ, int bat_index, unsigned long virt, unsigned long phys, init_done = 1; } } - + err = check_overlap (typ, virt, size); if ((size >= (1 << 17)) && (err >= 0) && (err != bat_index)) { rtems_interrupt_enable (level); diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h index 1f86dab66e..b5141686dd 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h @@ -6,7 +6,7 @@ * More detailed information can be found on motorola * site and more precisely in the following book : * - * MPC750 + * MPC750 * Risc Microporcessor User's Manual * Motorola REF : MPC750UM/AD 8/97 * @@ -57,7 +57,7 @@ extern int setibat(int bat_index, unsigned long virt, unsigned long phys, /* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed. * If pu and pl are NULL, the bat contents are dumped to the console (printk). - * + * * RETURNS: upper BAT contents or (-1) if index is invalid */ extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl); diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S index 2df1c85c9a..1035ed6922 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S @@ -11,7 +11,7 @@ * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * T. Straumann - 11/2001: added support for 7400 (no AltiVec yet) * S.K. Feng - 10/2003: added support for 7455 (no AltiVec yet) * @@ -40,7 +40,7 @@ #define PPC_860 0x50 #define PPC_821 PPC_860 #define PPC_8260 0x81 -#define PPC_8240 PPC_8260 +#define PPC_8240 PPC_8260 /* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */ #define DSSALL .long 0x7e00066c /* DSSALL altivec instruction opcode */ @@ -54,13 +54,13 @@ #define DL1HWF (1<<(31-8)) #define L2HWF (1<<(31-20)) - + #FIXME Should really move this to C code .globl L1_caches_enables .type L1_caches_enables, @function - -L1_caches_enables: + +L1_caches_enables: /* * Enable caches and 604-specific features if necessary. */ @@ -87,15 +87,15 @@ L1_caches_enables: cror 6,6,10 cror 6,6,14 cmpi 2,r9,PPC_750 /* or 750 */ - cror 6,6,10 + cror 6,6,10 cmpi 2,r9,PPC_7400 /* or 7400 */ - cror 6,6,10 + cror 6,6,10 cmpli 0,r9,PPC_7455 /* or 7455 */ beq 1f cmpli 0,r9,PPC_7457 /* or 7457 */ bne 2f 1: - /* 7455:link register stack,branch folding & + /* 7455:link register stack,branch folding & * TBEN : enable the time base and decrementer. * EMCP bit is defined in HID1. However, it's not used * in mvme5500 board because of GT64260 (e.g. it's connected @@ -103,7 +103,7 @@ L1_caches_enables: */ oris r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@h ori r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@l -2: cror 2,2,10 +2: cror 2,2,10 bne 3f ori r11,r11,HID0_BTIC /* enable branch tgt cache on 7400 , 7455 , 7457 */ 3: cror 2,2,6 @@ -119,14 +119,14 @@ L1_caches_enables: blr .globl get_L1CR -.type get_L1CR, @function +.type get_L1CR, @function get_L1CR: mfspr r3,HID0 blr - + .globl get_L2CR - .type get_L2CR, @function -get_L2CR: + .type get_L2CR, @function +get_L2CR: /* Make sure this is a > 750 chip */ mfspr r3,PVR rlwinm r3,r3,16,16,31 @@ -135,12 +135,12 @@ get_L2CR: cmplwi r3,PPC_7400 /* it's a 7400 */ beq 1f cmplwi r3,PPC_7455 /* it's a 7455 */ - beq 1f + beq 1f cmplwi r3,PPC_7457 /* it's a 7457 */ - beq 1f + beq 1f li r3,-1 blr - + 1: /* Return the L2CR contents */ mfspr r3,L2CR @@ -148,18 +148,18 @@ get_L2CR: .globl set_L2CR .type set_L2CR, @function -set_L2CR: +set_L2CR: /* Usage: - * When setting the L2CR register, you must do a few special things. - * If you are enabling the cache, you must perform a global invalidate. + * When setting the L2CR register, you must do a few special things. + * If you are enabling the cache, you must perform a global invalidate. * If you are disabling the cache, you must flush the cache contents first. * This routine takes care of doing these things. When first - * enabling the cache, make sure you pass in the L2CR you want, as well as - * passing in the global invalidate bit set. A global invalidate will - * only be performed if the L2I bit is set in applyThis. When enabling + * enabling the cache, make sure you pass in the L2CR you want, as well as + * passing in the global invalidate bit set. A global invalidate will + * only be performed if the L2I bit is set in applyThis. When enabling * the cache, you should also set the L2E bit in applyThis. If you - * want to modify the L2CR contents after the cache has been enabled, - * the recommended procedure is to first call __setL2CR(0) to disable + * want to modify the L2CR contents after the cache has been enabled, + * the recommended procedure is to first call __setL2CR(0) to disable * the cache and then call it again with the new values for L2CR. Examples: * * _setL2CR(0) - disables the cache @@ -171,13 +171,13 @@ set_L2CR: * - L2I set to perform a global invalidation * - L2OH set to 1 nS * - * A similar call should work for your card. You need to know the correct - * setting for your card and then place them in the fields I have outlined - * above. Other fields support optional features, such as L2DO which caches - * only data, or L2TS which causes cache pushes from the L1 cache to go to + * A similar call should work for your card. You need to know the correct + * setting for your card and then place them in the fields I have outlined + * above. Other fields support optional features, such as L2DO which caches + * only data, or L2TS which causes cache pushes from the L1 cache to go to *the L2 cache instead of to main memory. */ - + /* Make sure this is a > 750 chip */ mfspr r0,PVR rlwinm r0,r0,16,16,31 @@ -186,17 +186,17 @@ set_L2CR: cmplwi r0,PPC_7400 beq thisIs750 cmplwi r0,PPC_7455 - beq thisIs750 + beq thisIs750 cmplwi r0,PPC_7457 - beq thisIs750 + beq thisIs750 li r3,-1 blr - + thisIs750: /* Get the current enable bit of the L2CR into r4 */ mfspr r4,L2CR rlwinm r4,r4,0,0,0 - + /* See if we want to perform a global inval this time. */ rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ @@ -209,7 +209,7 @@ thisIs750: mtmsr r4 bne dontDisableCache /* Only disable the cache if L2CRApply has the enable bit off */ - cmplwi r0,PPC_7400 /* 7400 ? */ + cmplwi r0,PPC_7400 /* 7400 ? */ bne disableCache /* use traditional method */ /* On the 7400, they recommend using the hardware flush feature */ @@ -241,18 +241,18 @@ disableCache: mtmsr r4 sync isync - mfspr r4, MSSCR0 + mfspr r4, MSSCR0 rlwinm r4,r4,0,29,0 /* Turn off the L2PFE bits */ mtspr MSSCR0, r4 - sync + sync /* flush L1 first */ lis r4,0x0001 mtctr r4 li r4,0 - li r0,0 + li r0,0 loadFlush: lwzx r0,r0,r4 - dcbf r0,r4 + dcbf r0,r4 addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ bdnz loadFlush sync @@ -269,8 +269,8 @@ loadFlush: sync /* L2 flushed,L2IO & L2DO got cleared in the dontDisableCache: */ b reenableDR - -not745x: + +not745x: sync mtmsr r4 isync @@ -286,7 +286,7 @@ loadLoop: lwzx r0,r0,r4 addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ bdnz loadLoop - + /* Now, flush the first 2MB of memory */ lis r4,0x0001 mtctr r4 @@ -296,17 +296,17 @@ flushLoop: dcbf r0,r4 addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ bdnz flushLoop -reenableDR: +reenableDR: rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ sync mtmsr r4 isync flushDone: - + /* Turn off the L2CR enable bit. */ rlwinm r3,r3,0,1,31 - + dontDisableCache: /* Set up the L2CR configuration bits */ sync @@ -314,7 +314,7 @@ dontDisableCache: sync cmplwi r6,0 beq noInval - + /* Perform a global invalidation */ oris r3,r3,0x0020 sync @@ -324,11 +324,11 @@ invalCompleteLoop: /* Wait for the invalidation to complete */ mfspr r3,L2CR rlwinm. r4,r3,0,31,31 bne invalCompleteLoop - + rlwinm r3,r3,0,11,9; /* Turn off the L2I bit */ sync mtspr L2CR,r3 - + noInval: sync /* re-enable interrupts, i.e. restore original MSR */ @@ -336,7 +336,7 @@ noInval: /* See if we need to enable the cache */ cmplwi r5,0 beqlr - + enableCache: /* Enable the cache */ oris r3,r3,0x8000 @@ -344,20 +344,20 @@ enableCache: sync blr - + .globl get_L3CR - .type get_L3CR, @function -get_L3CR: + .type get_L3CR, @function +get_L3CR: /* Make sure this is a 7455 chip */ mfspr r3,PVR rlwinm r3,r3,16,16,31 cmplwi r3,PPC_7455 /* it's a 7455 */ - beq 1f + beq 1f cmplwi r3,PPC_7457 /* it's a 7457 */ - beq 1f + beq 1f li r3,-1 blr - + 1: /* Return the L3CR contents */ mfspr r3,L3CR @@ -365,34 +365,34 @@ get_L3CR: .globl set_L3CR .type set_L3CR, @function -set_L3CR: +set_L3CR: /* Usage: - * When setting the L3CR register, you must do a few special things. + * When setting the L3CR register, you must do a few special things. * If you are enabling the cache, you must perform a global invalidate. * Then call cpu_enable_l3cr(l3cr). * If you are disabling the cache, you must flush the cache contents first. * This routine takes care of doing these things. If you - * want to modify the L3CR contents after the cache has been enabled, - * the recommended procedure is to first call __setL3CR(0) to disable - * the cache and then call cpu_enable_l3cr with the new values for + * want to modify the L3CR contents after the cache has been enabled, + * the recommended procedure is to first call __setL3CR(0) to disable + * the cache and then call cpu_enable_l3cr with the new values for * L3CR. */ - + /* Make sure this is a 7455 chip */ mfspr r0,PVR rlwinm r0,r0,16,16,31 cmplwi r0,PPC_7455 - beq thisIs7455 + beq thisIs7455 cmplwi r0,PPC_7457 - beq thisIs7455 + beq thisIs7455 li r3,-1 blr - + thisIs7455: /* Get the current enable bit of the L3CR into r4 */ mfspr r4,L3CR rlwinm r4,r4,0,0,0 - + /* See if we want to perform a global inval this time. */ rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ @@ -411,7 +411,7 @@ thisIs7455: sync mtmsr r4 isync /* make sure memory accesses have completed */ - /* 7455: L3 : hardware flush + /* 7455: L3 : hardware flush * Set the L3CR[L3IO & L3DO] bits to completely lock the L3 cache */ mfspr r0, L3CR lis r4, L3CR_LOCK_745x@h @@ -428,19 +428,19 @@ thisIs7455: sync mtmsr r4 isync - + /* Turn off the L3CR enable bit. */ rlwinm r3,r3,0,1,31 - -dontDisableL3Cache: + +dontDisableL3Cache: /* Set up the L3CR configuration bits */ sync mtspr L3CR,r3 sync -ifL3Inval: +ifL3Inval: cmplwi r6,0 beq noL3Inval - + /* Perform a global invalidation */ oris r3,r3,0x0020 sync @@ -450,19 +450,19 @@ invalCompleteL3: /* Wait for the invalidation to complete */ mfspr r3,L3CR rlwinm. r4,r3,0,31,31 bne invalCompleteL3 - + rlwinm r3,r3,0,11,9; /* Turn off the L3I bit */ sync mtspr L3CR,r3 sync - + noL3Inval: /* re-enable interrupts, i.e. restore original MSR */ mtmsr r7 /* (no sync needed) */ /* See if we need to enable the cache */ cmplwi r5,0 beqlr - + enableL3Cache: /* Enable the cache */ oris r3,r3,0x8000 diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c index a81ed2d119..d4a891c7dd 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c @@ -4,19 +4,19 @@ * Purpose: allow write protection of text/ro-data */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -25,18 +25,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -45,9 +45,9 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ + */ /* Chose debugging options */ #undef DEBUG_MAIN /* create a standalone (host) program for basic testing */ @@ -419,7 +419,7 @@ triv121PgTblInit (unsigned long base, unsigned ldSize) * for a new CPU variant and that it has hardware PTE lookup/ * TLB replacement before adding it to this list. * - * NOTE: The 603 features no hardware PTE lookup - and + * NOTE: The 603 features no hardware PTE lookup - and * hence the page tables should NOT be used. * Although lookup could be implemented in * software this is probably not desirable @@ -1024,7 +1024,7 @@ dumpPteg (unsigned long vsid, unsigned long pi, unsigned long hash) * * RETURNS: address of the first page for which no * PTE was found (i.e. page index * page size) - * + * * ON SUCCESS, the special value 0x0C0C ("OKOK") * [which is not page aligned and hence is not * a valid page address]. diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h index 6b9497106d..fef2f0b269 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.h @@ -2,19 +2,19 @@ #define _LIBCPU_PTE121_H /* $Id$ */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -23,18 +23,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -43,9 +43,9 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ + */ /* Rudimentary page/hash table support for Powerpc * @@ -56,7 +56,7 @@ * * PURPOSE: * 1) allow write-protection of text/read-only data areas - * 2) provide more effective-address space in case + * 2) provide more effective-address space in case * the BATs are not enough * 3) allow 'alias' mappings. Such aliases can only use * the upper bits of the VSID since VSID & 0xf and the @@ -67,7 +67,7 @@ * be big enough!. * - only one page table supported. * - no locking implemented. If multiple threads modify - * the page table, it is the user's responsibility to + * the page table, it is the user's responsibility to * implement exclusive access. */ @@ -92,7 +92,7 @@ typedef struct PTERec_ { * RETURNS: a handle to the internal data structure * used to manage the page table. NULL on * error. - * + * * NOTES: - 'base' must be aligned to the size * - minimal ldSize is 16 (== 64k) * - this routine maps the page table itself @@ -100,7 +100,7 @@ typedef struct PTERec_ { * the CPU from overwriting the page table, * it can still be corrupted by PCI bus masters * (like DMA engines, [VME] bridges etc.) and - * even by this CPU if either the MMU is off + * even by this CPU if either the MMU is off * or if there is a DBAT mapping granting write * access... */ @@ -118,7 +118,7 @@ triv121PgTblInit(unsigned long base, unsigned ldSize); * ldSize = triv121PgTblLdMinSize(memsize); * memsize -= (1<<ldSize); / * reduce memory available to RTEMS * / * pgTbl = triv121PgTblInit(memsize,ldSize); - * + * */ unsigned long triv121PgTblLdMinSize(unsigned long size); @@ -167,7 +167,7 @@ triv121PgTblMap( unsigned protection /* 'pp' access protection: Super User * * 0 r/w none - * 1 r/w ro + * 1 r/w ro * 2 r/w r/w * 3 ro ro */ @@ -231,7 +231,7 @@ APte triv121DumpEa(unsigned long ea); */ APte triv121FindPte(unsigned long vsid, unsigned long pi); -/* +/* * Unmap an effective address * * RETURNS: pte that mapped the ea or NULL if no @@ -239,7 +239,7 @@ APte triv121FindPte(unsigned long vsid, unsigned long pi); */ APte triv121UnmapEa(unsigned long ea); -/* +/* * Change the WIMG and PP attributes of the page containing 'ea' * * NOTES: The 'wimg' and 'pp' may be <0 to indicate that no diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c index bc9ed1e7b2..f32f6b572e 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c @@ -42,7 +42,7 @@ int Timer_get_clicks_overhead(void) } /* - * benchmark_timer_initialize + * benchmark_timer_initialize */ void benchmark_timer_initialize(void) { diff --git a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c index 167d860dcd..68d857dd2e 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c @@ -12,7 +12,7 @@ * resource minor note * SMC1 0 * SMC2 1 - * SCC1 2 + * SCC1 2 * SCC2 3 * SCC3 4 * SCC4 5 @@ -117,7 +117,7 @@ static int m8xx_smc_set_attributes (int minor, const struct termios *t) { int baud, brg=0, csize=0, ssize, psize; - uint16_t clen=0, cstopb, parenb, parodd, cread; + uint16_t clen=0, cstopb, parenb, parodd, cread; /* Baud rate */ switch (t->c_cflag & CBAUD) { @@ -152,13 +152,13 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) break; case SMC2_MINOR: /* SMC2 can only choose between BRG2 and 8 */ - brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; + brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; m8260.cmxsmr &= ~0x30; m8260.cmxsmr |= (brg==2? 0x00: 0x01 ); break; } } - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 5; break; @@ -184,15 +184,15 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) parenb = 0x0000; /* No parity on Tx and Rx */ psize = 0; } - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else parodd = 0x0100; - /* + /* * Character Length = start + data + parity + stop - 1 - */ + */ switch ( 1 + csize + psize + ssize - 1 ) { case 6: clen = 0x3000; break; case 7: clen = 0x3800; break; @@ -206,7 +206,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) cread = 0x0023; /* UART normal operation, enable Rx and Tx */ else cread = 0x0021; /* UART normal operation, enable Tx */ - + /* Write the SIMODE/SMCMR registers */ switch (minor) { case SMC1_MINOR: @@ -257,7 +257,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) case B460800: baud = 460800; break; } if (baud > 0) { - brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); + brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); m8260.cmxscr |= ((brg<<(3+8*(3-(minor-SCC1_MINOR)))) & (brg<<(8*(3-(minor-SCC1_MINOR))))); @@ -275,13 +275,13 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) cstopb = 0x4000; /* Two stop bits */ else cstopb = 0x0000; /* One stop bit */ - + /* Parity */ if ( t->c_cflag & PARENB ) parenb = 0x0010; /* Parity enabled on Tx and Rx */ else parenb = 0x0000; /* No parity on Tx and Rx */ - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else @@ -319,7 +319,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) } -int +int m8xx_uart_setAttributes( int minor, const struct termios *t @@ -328,7 +328,7 @@ m8xx_uart_setAttributes( /* * Check that port number is valid */ - if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) return 0; switch (minor) { @@ -408,8 +408,8 @@ m8xx_scc2_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC2_MINOR], @@ -453,8 +453,8 @@ m8xx_scc3_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC3_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC3_MINOR], @@ -499,8 +499,8 @@ m8xx_scc4_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC4_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC4_MINOR], @@ -543,8 +543,8 @@ m8xx_smc1_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC1_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC1_MINOR], @@ -588,8 +588,8 @@ m8xx_smc2_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC2_MINOR], @@ -693,7 +693,7 @@ m8xx_uart_scc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) return; /* Get the sicr clock source bit values for 9600 bps */ @@ -740,7 +740,7 @@ m8xx_uart_scc_initialize (int minor) sccparms = (m8260SCCparms_t*)&m8260.scc4p; sccregs = (m8260SCCRegisters_t*)&m8260.scc4; } - + sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260; sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260; @@ -823,7 +823,7 @@ m8xx_uart_scc_initialize (int minor) switch (minor) { case SCC1_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC1; - consoleIrqData.hdl = m8xx_scc1_interrupt_handler; + consoleIrqData.hdl = m8xx_scc1_interrupt_handler; break; case SCC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC2; @@ -837,7 +837,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SCC4; consoleIrqData.hdl = m8xx_scc4_interrupt_handler; break; - + } if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { printk("Unable to connect SCC Irq handler\n"); @@ -896,7 +896,7 @@ m8xx_uart_smc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) + if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) return; /* Get the simode clock source bit values for 9600 bps */ @@ -943,13 +943,13 @@ m8xx_uart_smc_initialize (int minor) m8260.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ m8260.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ m8260.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ - + m8260.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ m8260.simode |= brg << 28; /* SMC2CS = brg */ #endif break; } - + /* * Set up SMC parameter RAM common to all protocols */ @@ -1000,7 +1000,7 @@ m8xx_uart_smc_initialize (int minor) m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC2); break; } - + /* * Enable receiver and transmitter */ @@ -1029,7 +1029,7 @@ m8xx_uart_smc_initialize (int minor) m8260.sipnr_l |= M8260_SIMASK_SMC1; /* Clear pending register */ m8260.simr_l |= M8260_SIMASK_SMC1; /* Enable SMC1 interrupts */ break; - + case SMC2_MINOR: rtems_interrupt_catch (m8xx_smc2_interrupt_handler, PPC_IRQ_CPM_SMC2, @@ -1055,7 +1055,7 @@ m8xx_uart_initialize(void) } -void +void m8xx_uart_interrupts_initialize(void) { #ifdef mpc8260 @@ -1085,7 +1085,7 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8260_BD_EMPTY) { return -1; } - rtems_cache_invalidate_multiple_data_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[minor]->buffer, RxBd[minor]->length ); @@ -1098,7 +1098,7 @@ m8xx_uart_pollRead( /* * TODO: Get a free buffer and set it up. */ -int +int m8xx_uart_write( int minor, const char *buf, @@ -1113,7 +1113,7 @@ m8xx_uart_write( TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT; return 0; } - + int m8xx_uart_pollWrite( diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c index 7f56abff7e..b8adf9feaf 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c @@ -2,7 +2,7 @@ * cp.c * * MPC8xx CPM RISC Communication Processor routines. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -23,7 +23,7 @@ void m8xx_cp_execute_cmd( uint32_t command ) { uint16_t lvl; - + rtems_interrupt_disable(lvl); while (m8260.cpcr & M8260_CR_FLG) { continue; diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c index b38a63ee16..4e6202ed79 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c @@ -49,16 +49,16 @@ m8xx_dpram_allocate( unsigned int byte_count ) unsigned int i; ISR_Level level; void *blockp = NULL; - + byte_count = (byte_count + 3) & ~0x3; - + /* * Running with interrupts disabled is usually considered bad * form, but this routine is probably being run as part of an * initialization sequence so the effect shouldn't be too severe. */ _ISR_Disable (level); - + for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) { /* * Verify that the region is available for use. @@ -84,9 +84,9 @@ m8xx_dpram_allocate( unsigned int byte_count ) break; } } - + _ISR_Enable(level); - + if (blockp == NULL) rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count); return blockp; diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h index c73afa138a..34800a6ba5 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h @@ -1,7 +1,7 @@ -/* +/* * cpm.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the Communications Processor Module (CPM) on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -104,7 +104,7 @@ void *m8xx_dpram_allocate( unsigned int byte_count ); #define m8xx_RISC_timer_table_allocate(count) \ m8xx_dpram_allocate( (count) * 4 ) - + int m8xx_get_brg_cd (int baud); int m8xx_get_brg(unsigned brgmask, int baud); @@ -114,7 +114,7 @@ void m8xx_free_brg(int brg_num); int m8xx_get_clk( unsigned clkmask ); void m8xx_free_clk( int clk_num ); - + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h index 352c7e25ca..66bd426c79 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h @@ -1,7 +1,7 @@ -/* +/* * mmu.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -29,7 +29,7 @@ typedef struct { } MMU_TLB_table_t; /* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be * supplied by the BSP. */ extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h index a710765650..ea088ebae8 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h @@ -738,8 +738,8 @@ typedef struct m8260BufferDescriptor_ { */ typedef struct m8260IDMABufferDescriptor_ { uint16_t status; - uint8_t dfcr; - uint8_t sfcr; + uint8_t dfcr; + uint8_t sfcr; uint32_t length; void *source; void *destination; @@ -1178,7 +1178,7 @@ typedef struct m8260_ { uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ - + /* * General SIU Block */ @@ -1237,7 +1237,7 @@ typedef struct m8260_ { uint32_t immr; uint8_t mem_pad4[84]; - + /* * System integration timers */ @@ -1255,7 +1255,7 @@ typedef struct m8260_ { uint8_t sit_pad3[94]; uint8_t sit_pad4[2390]; - + /* * Interrupt Controller */ @@ -1283,7 +1283,7 @@ typedef struct m8260_ { uint32_t rsr; uint32_t rmr; uint8_t clr_pad0[104]; - + /* * Input/ Output Port @@ -1369,7 +1369,7 @@ typedef struct m8260_ { uint8_t idmr4; uint8_t dma_pad9[707]; - + /* * FCC Block */ @@ -1404,8 +1404,8 @@ typedef struct m8260_ { uint8_t i2m_pad4[3]; uint8_t i2cmr; uint8_t i2m_pad5[331]; - - + + /* * CPM Block */ @@ -1419,7 +1419,7 @@ typedef struct m8260_ { uint8_t cpm_pad4[2]; uint32_t rtsr; uint8_t cpm_pad5[12]; - + /* * BRG 1-4 Block @@ -1428,7 +1428,7 @@ typedef struct m8260_ { uint32_t brgc2; uint32_t brgc3; uint32_t brgc4; - + /* * SCC Block @@ -1438,14 +1438,14 @@ typedef struct m8260_ { m8260SCCRegisters_t scc3; m8260SCCRegisters_t scc4; - + /* * SMC Block */ m8260SMCRegisters_t smc1; m8260SMCRegisters_t smc2; - + /* * SPI Block */ @@ -1458,7 +1458,7 @@ typedef struct m8260_ { uint8_t spcom; uint8_t spi_pad3[82]; - + /* * CPM Mux Block */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c index 5c1fac655f..278f5165ad 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c @@ -1,7 +1,7 @@ -/* +/* * mmu.c - * - * This file contains routines for initializing + * + * This file contains routines for initializing * and manipulating the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -21,18 +21,18 @@ /* * mmu_init * - * This routine sets up the virtual memory maps on an MPC8xx. - * The MPC8xx does not support block address translation (BATs) - * and does not have segment registers. Thus, we must set up page + * This routine sets up the virtual memory maps on an MPC8xx. + * The MPC8xx does not support block address translation (BATs) + * and does not have segment registers. Thus, we must set up page * translation. However, its MMU supports variable size pages * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. * - * The MPC8xx has separate data and instruction 32-entry translation - * lookaside buffers (TLB). By mapping all of DRAM as one huge page, - * we can preload the TLBs and not have to be concerned with taking + * The MPC8xx has separate data and instruction 32-entry translation + * lookaside buffers (TLB). By mapping all of DRAM as one huge page, + * we can preload the TLBs and not have to be concerned with taking * TLB miss exceptions. * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ void mmu_init( void ) @@ -50,11 +50,11 @@ void mmu_init( void ) * We can assume the MSR has already been set this way. */ - /* + /* * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) * GPM [0] 0b0 = PowerPC mode * PPM [1] 0b0 = Page resolution of protection - * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = + * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = * NO for IMMU, YES for DMMU! * reserved/WTDEF [3] 0b0 = Default write-through attribute = not * RSV4x [4] 0b0 = 4 entries not reserved @@ -63,7 +63,7 @@ void mmu_init( void ) * reserved [7-18] 0x00 * xTLB_INDX [19-23] 31 = 0x1F * reserved [24-31] 0x00 - * + * * Note: It is important that cache-inhibit be set as the default for the * data cache when the DMMU is disabled in order to prevent internal memory * mapped registers from being cached accidentally when address translation @@ -74,15 +74,15 @@ void mmu_init( void ) reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); _mtspr( M8xx_MD_CTR, reg1 ); _isync; - - /* + + /* * Invalidate all TLB entries in both TLBs. * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so * all 32 entries are invalidated. */ __asm__ volatile ("tlbia\n"::); _isync; - + /* * Set Current Address Space ID Register (M_CASID). * Supervisor: CASID = 0 @@ -90,7 +90,7 @@ void mmu_init( void ) reg1 = 0; _mtspr( M8xx_M_CASID, reg1 ); - /* + /* * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) * We ignore the Access Protection Group (APG) mechanism globally * by setting all of the Mx_AP fields to 0b01 : client access @@ -100,10 +100,10 @@ void mmu_init( void ) _mtspr( M8xx_MI_AP, reg1 ); _mtspr( M8xx_MD_AP, reg1 ); - /* + /* * Load both 32-entry TLBs with values from the MMU_TLB_table * which is defined in the BSP. - * Note the _TLB_Table must have at most 32 entries. This code + * Note the _TLB_Table must have at most 32 entries. This code * makes no effort to enforce this restriction. */ for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { @@ -118,9 +118,9 @@ void mmu_init( void ) _mtspr( M8xx_MD_RPN, reg1 ); } - /* + /* * Turn on address translation by setting MSR[IR] and MSR[DR]. - */ + */ _CPU_MSR_GET( reg1 ); reg1 |= PPC_MSR_IR | PPC_MSR_DR; _CPU_MSR_SET( reg1 ); diff --git a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c index 2b8d0b812d..be77f4fd14 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c @@ -73,7 +73,7 @@ void benchmark_timer_initialize(void) /* m860.tbscr |= M860_TBSCR_TBIRQ(4) | M860_TBSCR_TBE; */ - + Timer_starting = get_itimer(); } diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c index 2510bbfef9..113654f487 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c @@ -54,7 +54,7 @@ static rtems_status_code mpc83xx_i2c_find_clock_divider int divider; int fdr_val; } dividers[] ={ - { 256,0x20 }, { 288,0x21 }, { 320,0x22 }, { 352,0x23 }, + { 256,0x20 }, { 288,0x21 }, { 320,0x22 }, { 352,0x23 }, { 384,0x00 }, { 416,0x01 }, { 448,0x25 }, { 480,0x02 }, { 512,0x26 }, { 576,0x03 }, { 640,0x04 }, { 704,0x05 }, { 768,0x29 }, { 832,0x06 }, { 896,0x2a }, { 1024,0x07 }, @@ -118,7 +118,7 @@ static int mpc83xx_i2c_wait if (softc_ptr->initialized) { /* - * enable interrupt mask + * enable interrupt mask */ softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_MIEN; rc = rtems_semaphore_obtain(softc_ptr->irq_sema_id,RTEMS_WAIT,100); @@ -171,19 +171,19 @@ static void mpc83xx_i2c_irq_handler \*=========================================================================*/ { mpc83xx_i2c_softc_t *softc_ptr = (mpc83xx_i2c_softc_t *)handle; - + /* * clear IRQ flag */ softc_ptr->reg_ptr->i2csr &= ~MPC83XX_I2CSR_MIF; /* - * disable interrupt mask + * disable interrupt mask */ softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MIEN; if (softc_ptr->initialized) { rtems_semaphore_release(softc_ptr->irq_sema_id); - } + } } /*=========================================================================*\ @@ -269,7 +269,7 @@ static void mpc83xx_i2c_install_irq_handler */ rc = rtems_semaphore_create(rtems_build_name('i','2','c','s'), 0, - RTEMS_FIFO + RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE, 0, &softc_ptr->irq_sema_id); @@ -339,13 +339,13 @@ static rtems_status_code mpc83xx_i2c_init /* * set own slave address to broadcast (0x00) */ - softc_ptr->reg_ptr->i2cadr = 0x00 ; + softc_ptr->reg_ptr->i2cadr = 0x00 ; /* * set control register to module enable */ softc_ptr->reg_ptr->i2ccr = MPC83XX_I2CCR_MEN; - + /* * init interrupt stuff */ @@ -386,7 +386,7 @@ static rtems_status_code mpc83xx_i2c_send_start #endif if (0 != (softc_ptr->reg_ptr->i2ccr & MPC83XX_I2CCR_MSTA)) { /* - * already started, so send a "repeated start" + * already started, so send a "repeated start" */ softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_RSTA; } @@ -470,11 +470,11 @@ static rtems_status_code mpc83xx_i2c_send_addr */ if (addr > 0x7f) { long_addr = true; - addr_byte = (0xf0 + addr_byte = (0xf0 | ((addr >> 7) & 0x06) | ((rw) ? 1 : 0)); /* - * send first byte + * send first byte */ softc_ptr->reg_ptr->i2cdr = addr_byte; /* @@ -491,9 +491,9 @@ static rtems_status_code mpc83xx_i2c_send_addr } } /* - * send (final) byte + * send (final) byte */ - addr_byte = ((addr << 1) + addr_byte = ((addr << 1) | ((rw) ? 1 : 0)); softc_ptr->reg_ptr->i2cdr = addr_byte; @@ -541,7 +541,7 @@ static int mpc83xx_i2c_read_bytes softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX; softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK; /* - * FIXME: do we need to deactivate TXAK from the start, + * FIXME: do we need to deactivate TXAK from the start, * when only one byte is to be received? */ /* @@ -569,7 +569,7 @@ static int mpc83xx_i2c_read_bytes return -rc; } *p++ = softc_ptr->reg_ptr->i2cdr; - + } /* @@ -611,7 +611,7 @@ static int mpc83xx_i2c_write_bytes #if defined(DEBUG) printk("mpc83xx_i2c_write_bytes called... "); #endif - softc_ptr->reg_ptr->i2ccr = + softc_ptr->reg_ptr->i2ccr = (softc_ptr->reg_ptr->i2ccr & ~MPC83XX_I2CCR_TXAK) | MPC83XX_I2CCR_MTX; while (len-- > 0) { softc_ptr->reg_ptr->i2cdr = *p++; diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h index 33f40003ad..4aca85bbab 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h @@ -36,7 +36,7 @@ typedef struct mpc83xx_i2c_softc { } mpc83xx_i2c_softc_t ; typedef struct { - rtems_libi2c_bus_t bus_desc; + rtems_libi2c_bus_t bus_desc; struct mpc83xx_i2c_softc softc; } mpc83xx_i2c_desc_t; diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h index 9e7fb62053..5431319adf 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h @@ -679,8 +679,8 @@ typedef struct m83xxUSB_DRRegisters_ { } m83xxUSB_DRRegisters_t; /* - * this enumeration defines the index - * of a given rmon mib counter + * this enumeration defines the index + * of a given rmon mib counter * in the tsec_rmon_mib array */ typedef enum { @@ -1114,7 +1114,7 @@ typedef struct m83xxRegisters_ { uint8_t reserved0_4000[0x4500-0x4000]; m83xxDUARTRegisters_t duart[2]; uint8_t reserved0_4700[0x5000-0x4700]; - m83xxLBCRegisters_t lbc; + m83xxLBCRegisters_t lbc; uint8_t reserved0_5100[0x7000-0x5100]; m83xxSPIRegisters_t spi; uint8_t reserved0_7100[0x8000-0x7100]; @@ -1228,9 +1228,9 @@ extern m83xxRegisters_t mpc83xx; #define RCWLR_DDRCM_1_1 (0 << (31- 1)) /* 1:1 */ #define RCWLR_DDRCM_2_1 (1 << (31- 1)) /* 2:1 */ /* System PLL mult. factor */ -#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7)) +#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7)) /* Core PLL mult. factor */ -#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) +#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) /* PCI host mode */ #define RCWHR_PCI_AGENT (0 << (31- 0)) /* agent mode */ @@ -1298,38 +1298,38 @@ typedef struct PQ_BufferDescriptor_ { /* * Bits in receive buffer descriptor status word */ -#define M83xx_BD_EMPTY (1<<15) -#define M83xx_BD_RO1 (1<<14) -#define M83xx_BD_WRAP (1<<13) -#define M83xx_BD_INTERRUPT (1<<12) -#define M83xx_BD_LAST (1<<11) -#define M83xx_BD_CONTROL_CHAR (1<<11) -#define M83xx_BD_FIRST_IN_FRAME (1<<10) -#define M83xx_BD_MISS (1<<8) -#define M83xx_BD_BROADCAST (1<<7) -#define M83xx_BD_MULTICAST (1<<6) -#define M83xx_BD_LONG (1<<5) -#define M83xx_BD_NONALIGNED (1<<4) -#define M83xx_BD_SHORT (1<<3) -#define M83xx_BD_CRC_ERROR (1<<2) -#define M83xx_BD_OVERRUN (1<<1) -#define M83xx_BD_COLLISION (1<<0) +#define M83xx_BD_EMPTY (1<<15) +#define M83xx_BD_RO1 (1<<14) +#define M83xx_BD_WRAP (1<<13) +#define M83xx_BD_INTERRUPT (1<<12) +#define M83xx_BD_LAST (1<<11) +#define M83xx_BD_CONTROL_CHAR (1<<11) +#define M83xx_BD_FIRST_IN_FRAME (1<<10) +#define M83xx_BD_MISS (1<<8) +#define M83xx_BD_BROADCAST (1<<7) +#define M83xx_BD_MULTICAST (1<<6) +#define M83xx_BD_LONG (1<<5) +#define M83xx_BD_NONALIGNED (1<<4) +#define M83xx_BD_SHORT (1<<3) +#define M83xx_BD_CRC_ERROR (1<<2) +#define M83xx_BD_OVERRUN (1<<1) +#define M83xx_BD_COLLISION (1<<0) /* * Bits in transmit buffer descriptor status word * Many bits have the same meaning as those in receiver buffer descriptors. */ -#define M83xx_BD_READY (1<<15) -#define M83xx_BD_PAD_CRC (1<<14) +#define M83xx_BD_READY (1<<15) +#define M83xx_BD_PAD_CRC (1<<14) /* WRAP/Interrupt as in Rx BDs */ -#define M83xx_BD_TX_CRC (1<<10) -#define M83xx_BD_DEFER (1<<9) -#define M83xx_BD_TO1 (1<<8) -#define M83xx_BD_HFE_ (1<<7) -#define M83xx_BD_LATE_COLLISION (1<<7) -#define M83xx_BD_RETRY_LIMIT (1<<6) -#define M83xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) -#define M83xx_BD_UNDERRUN (1<<1) -#define M83xx_BD_TXTRUNC (1<<0) +#define M83xx_BD_TX_CRC (1<<10) +#define M83xx_BD_DEFER (1<<9) +#define M83xx_BD_TO1 (1<<8) +#define M83xx_BD_HFE_ (1<<7) +#define M83xx_BD_LATE_COLLISION (1<<7) +#define M83xx_BD_RETRY_LIMIT (1<<6) +#define M83xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) +#define M83xx_BD_UNDERRUN (1<<1) +#define M83xx_BD_TXTRUNC (1<<0) #endif /* _MPC83XX_MPC83XX_H */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c index dd80a29696..dd3c28ea27 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c @@ -70,8 +70,8 @@ struct mpc83xx_tsec_struct { int irq_num_tx; /* tx irq number */ int irq_num_rx; /* rx irq number */ int irq_num_err; /* error irq number */ - - /* + + /* * BD management */ int rxBdCount; @@ -87,10 +87,10 @@ struct mpc83xx_tsec_struct { PQBufferDescriptor_t *Tx_NxtUsed_BD; /* First BD, which is in Use */ PQBufferDescriptor_t *Tx_NxtFill_BD; /* BD to be filled next */ struct mbuf **Tx_mBuf_Ptr; /* Storage for mbufs */ - /* - * Daemon IDs + /* + * Daemon IDs */ - rtems_id rxDaemonTid; + rtems_id rxDaemonTid; rtems_id txDaemonTid; /* @@ -214,7 +214,7 @@ static void mpc83xx_tsec_hwinit * NOTE: do not clear bits set in BSP init function */ reg_ptr->ecntrl = ((reg_ptr->ecntrl & ~M83xx_TSEC_ECNTRL_AUTOZ) - | M83xx_TSEC_ECNTRL_CLRCNT + | M83xx_TSEC_ECNTRL_CLRCNT | M83xx_TSEC_ECNTRL_STEN | M83xx_TSEC_ECNTRL_R100M); @@ -237,7 +237,7 @@ static void mpc83xx_tsec_hwinit | M83xx_TSEC_ATTR_RBDSEN); - reg_ptr->mrblr = MCLBYTES-64; /* take care of buffer size lost + reg_ptr->mrblr = MCLBYTES-64; /* take care of buffer size lost * due to alignment */ /* @@ -282,7 +282,7 @@ static void mpc83xx_tsec_hwinit */ reg_ptr->maccfg1 = (M83xx_TSEC_MACCFG1_RX_FLOW | M83xx_TSEC_MACCFG1_TX_FLOW); - + /* * init MACCFG2 register */ @@ -395,9 +395,9 @@ int mpc83xx_tsec_mdio_read return EINVAL; } /* - * set PHY/reg address + * set PHY/reg address */ - reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy) + reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy) | M83xx_TSEC_MIIMADD_REGADDR(reg)); /* * start read cycle @@ -463,9 +463,9 @@ int mpc83xx_tsec_mdio_write return EINVAL; } /* - * set PHY/reg address + * set PHY/reg address */ - reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy) + reg_ptr->miimadd = (M83xx_TSEC_MIIMADD_PHY(phy) | M83xx_TSEC_MIIMADD_REGADDR(reg)); /* * start write cycle @@ -511,13 +511,13 @@ static rtems_event_set mpc83xx_tsec_rx_wait_for_events * enable Rx interrupts, make sure this is not interrupted :-) */ M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_RXALL,~0); - + /* * wait for events to come in */ - rtems_bsdnet_event_receive(event_mask, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive(event_mask, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); return events; } @@ -558,7 +558,7 @@ static void mpc83xx_rxbd_alloc_clear sc->Rx_Frst_BD = (PQBufferDescriptor_t *)alloc_ptr; sc->Rx_NxtUsed_BD = sc->Rx_Frst_BD; sc->Rx_NxtFill_BD = sc->Rx_Frst_BD; - + /* * clear all BDs */ @@ -602,7 +602,7 @@ static void mpc83xx_tsec_receive_packets while ((0 == ((status = BD_ptr->status) & M83xx_BD_EMPTY)) && !finished && - (BD_ptr->buffer != NULL)) { + (BD_ptr->buffer != NULL)) { /* * get mbuf associated with BD */ @@ -624,8 +624,8 @@ static void mpc83xx_tsec_receive_packets /* * send mbuf of this buffer to ether_input() */ - m->m_len = m->m_pkthdr.len = (BD_ptr->length - - sizeof(uint32_t) + m->m_len = m->m_pkthdr.len = (BD_ptr->length + - sizeof(uint32_t) - sizeof(struct ether_header)); eh = mtod(m, struct ether_header *); m->m_data += sizeof(struct ether_header); @@ -644,8 +644,8 @@ static void mpc83xx_tsec_receive_packets /* * Advance BD_ptr to next BD */ - BD_ptr = ((BD_ptr == sc->Rx_Last_BD) - ? sc->Rx_Frst_BD + BD_ptr = ((BD_ptr == sc->Rx_Last_BD) + ? sc->Rx_Frst_BD : BD_ptr+1); } sc->Rx_NxtUsed_BD = BD_ptr; @@ -675,7 +675,7 @@ static void mpc83xx_tsec_refill_rxbds int bd_idx; BD_ptr = sc->Rx_NxtFill_BD; - while ((BD_ptr->buffer == NULL) && + while ((BD_ptr->buffer == NULL) && !finished) { /* * get new mbuf and attach a cluster @@ -699,16 +699,16 @@ static void mpc83xx_tsec_refill_rxbds m->m_data = M83xx_TSEC_ALIGN_BUFFER(m->m_ext.ext_buf,64); BD_ptr->buffer = m->m_data; BD_ptr->length = 0; - BD_ptr->status = (M83xx_BD_EMPTY + BD_ptr->status = (M83xx_BD_EMPTY | M83xx_BD_INTERRUPT - | ((BD_ptr == sc->Rx_Last_BD) - ? M83xx_BD_WRAP + | ((BD_ptr == sc->Rx_Last_BD) + ? M83xx_BD_WRAP : 0)); /* * Advance BD_ptr to next BD */ - BD_ptr = ((BD_ptr == sc->Rx_Last_BD) - ? sc->Rx_Frst_BD + BD_ptr = ((BD_ptr == sc->Rx_Last_BD) + ? sc->Rx_Frst_BD : BD_ptr+1); } } @@ -733,7 +733,7 @@ static void mpc83xx_tsec_rxDaemon | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)arg; bool finished = false; rtems_event_set events; @@ -817,7 +817,7 @@ static void mpc83xx_txbd_alloc_clear sc->Tx_Frst_BD = (PQBufferDescriptor_t *)alloc_ptr; sc->Tx_NxtUsed_BD = sc->Tx_Frst_BD; sc->Tx_NxtFill_BD = sc->Tx_Frst_BD; - + /* * clear all BDs */ @@ -881,13 +881,13 @@ static rtems_event_set mpc83xx_tsec_tx_wait_for_events * enable Tx interrupts, make sure this is not interrupted :-) */ M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask,M83xx_IEVENT_TXALL,~0); - + /* * wait for events to come in */ - rtems_bsdnet_event_receive(event_mask, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive(event_mask, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); return events; } @@ -929,8 +929,8 @@ static void mpc83xx_tsec_tx_retire /* * Advance CurrBD to next BD */ - RetBD = ((RetBD == sc->Tx_Last_BD) - ? sc->Tx_Frst_BD + RetBD = ((RetBD == sc->Tx_Last_BD) + ? sc->Tx_Frst_BD : RetBD+1); } sc->Tx_NxtUsed_BD = RetBD; @@ -971,7 +971,7 @@ static void mpc83xx_tsec_sendpacket */ struct mbuf *n; MFREE(m, n); - m = n; + m = n; if(l != NULL) { l->m_next = m; } @@ -981,7 +981,7 @@ static void mpc83xx_tsec_sendpacket * this mbuf is non-empty, so send it */ /* - * Is CurrBD still in Use/not yet retired? + * Is CurrBD still in Use/not yet retired? */ while (CurrBD->buffer != NULL) { /* @@ -997,11 +997,11 @@ static void mpc83xx_tsec_sendpacket } } status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC) - | ((m->m_next == NULL) + | ((m->m_next == NULL) ? M83xx_BD_LAST | M83xx_BD_INTERRUPT : 0) | ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0)); - + /* * link buffer to BD */ @@ -1015,7 +1015,7 @@ static void mpc83xx_tsec_sendpacket m = m->m_next; /* advance to next mbuf of this packet */ /* * is this the first BD of the packet? - * then don't set it to "READY" state, + * then don't set it to "READY" state, * and remember this BD position */ if (FrstBD == NULL) { @@ -1028,14 +1028,14 @@ static void mpc83xx_tsec_sendpacket /* * Advance CurrBD to next BD */ - CurrBD = ((CurrBD == sc->Tx_Last_BD) - ? sc->Tx_Frst_BD + CurrBD = ((CurrBD == sc->Tx_Last_BD) + ? sc->Tx_Frst_BD : CurrBD+1); } } /* - * mbuf chain of this packet - * has been translated + * mbuf chain of this packet + * has been translated * to BD chain, so set first BD ready now */ if (FrstBD != NULL) { @@ -1066,7 +1066,7 @@ static void mpc83xx_tsec_txDaemon | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)arg; struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; @@ -1086,7 +1086,7 @@ static void mpc83xx_tsec_txDaemon * wait for events to come in */ events = mpc83xx_tsec_tx_wait_for_events(sc, - START_TRANSMIT_EVENT + START_TRANSMIT_EVENT | INTERRUPT_EVENT); #if !defined(CLREVENT_IN_IRQ) /* @@ -1107,13 +1107,13 @@ static void mpc83xx_tsec_txDaemon * Get the next mbuf chain to transmit. */ IF_DEQUEUE(&ifp->if_snd, m); - + if (m) { mpc83xx_tsec_sendpacket(sc,m); } } while (m != NULL); - ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags &= ~IFF_OACTIVE; } /* * disable Tx in MACCFG1 register @@ -1148,7 +1148,7 @@ static void mpc83xx_tsec_tx_irq_handler | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)handle; #if defined(CLREVENT_IN_IRQ) uint32_t irq_events; @@ -1191,7 +1191,7 @@ static void mpc83xx_tsec_rx_irq_handler | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)handle; #if defined(CLREVENT_IN_IRQ) uint32_t irq_events; @@ -1234,7 +1234,7 @@ static void mpc83xx_tsec_err_irq_handler | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)handle; /* * clear error events in IEVENT @@ -1267,9 +1267,9 @@ static uint32_t mpc83xx_tsec_irq_mask | determine irq mask for given interrupt number | +---------------------------------------------------------------------------+ | Input Parameters: | -\*-------------------------------------------------------------------------*/ +\*-------------------------------------------------------------------------*/ int irqnum, - struct mpc83xx_tsec_struct *sc + struct mpc83xx_tsec_struct *sc ) /*-------------------------------------------------------------------------*\ | Return Value: | @@ -1303,7 +1303,7 @@ static void mpc83xx_tsec_irq_on | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)(irq_conn_data->handle); M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask, @@ -1330,7 +1330,7 @@ static void mpc83xx_tsec_irq_off | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)irq_conn_data->handle; M83xx_TSEC_IMASK_SET(sc->reg_ptr->imask, @@ -1357,10 +1357,10 @@ static int mpc83xx_tsec_irq_isOn | <none> | \*=========================================================================*/ { - struct mpc83xx_tsec_struct *sc = + struct mpc83xx_tsec_struct *sc = (struct mpc83xx_tsec_struct *)irq_conn_data->handle; - return (0 != (sc->reg_ptr->imask + return (0 != (sc->reg_ptr->imask & mpc83xx_tsec_irq_mask(irq_conn_data->name,sc))); } @@ -1466,11 +1466,11 @@ static void mpc83xx_tsec_init * allocate storage for mbuf ptrs */ sc->Rx_mBuf_Ptr = calloc(sc->rxBdCount,sizeof(struct mbuf *)); - sc->Tx_mBuf_Ptr = calloc(sc->txBdCount,sizeof(struct mbuf *)); + sc->Tx_mBuf_Ptr = calloc(sc->txBdCount,sizeof(struct mbuf *)); if ((sc->Rx_mBuf_Ptr == NULL) || (sc->Tx_mBuf_Ptr == NULL)) { rtems_panic("TSEC: cannot allocate buffers for mbuf management"); - + } /* @@ -1486,12 +1486,12 @@ static void mpc83xx_tsec_init /* * Start driver tasks */ - sc->txDaemonTid = rtems_bsdnet_newproc("TStx", - 4096, - mpc83xx_tsec_txDaemon, + sc->txDaemonTid = rtems_bsdnet_newproc("TStx", + 4096, + mpc83xx_tsec_txDaemon, sc); - sc->rxDaemonTid = rtems_bsdnet_newproc("TSrx", 4096, - mpc83xx_tsec_rxDaemon, + sc->rxDaemonTid = rtems_bsdnet_newproc("TSrx", 4096, + mpc83xx_tsec_rxDaemon, sc); /* * install interrupt handlers @@ -1512,7 +1512,7 @@ static void mpc83xx_tsec_init /* * for HSC CM01: we need to configure the PHY to use maximum skew adjust */ - + mpc83xx_tsec_mdio_write(-1,sc,23,0x0100); #endif @@ -1592,17 +1592,17 @@ static void mpc83xx_tsec_stats (((reg % 4) == 3) ? '\n' : ' ')); } } -#endif +#endif /* * print some statistics */ printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); printf (" Rx Errors:%-8lu", sc->rxErrors); - printf (" Rx packets:%-8lu\n", + printf (" Rx packets:%-8lu\n", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rpkt]); - printf (" Rx broadcasts:%-8lu", + printf (" Rx broadcasts:%-8lu", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rbca]); - printf (" Rx multicasts:%-8lu", + printf (" Rx multicasts:%-8lu", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rmca]); printf (" Giant:%-8lu\n", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rovr]); @@ -1612,10 +1612,10 @@ static void mpc83xx_tsec_stats sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rfcs]); printf (" Overrun:%-8lu\n", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_rdrp]); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" Tx Errors:%-8lu", sc->txErrors); - printf (" Tx packets:%-8lu\n", + printf (" Tx packets:%-8lu\n", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tpkt]); printf (" Deferred:%-8lu", sc->reg_ptr->rmon_mib[m83xx_tsec_rmon_tdfr]); @@ -1770,12 +1770,12 @@ int rtems_mpc83xx_tsec_mode_adapt * if we are 1000MBit, then switch IF to byte mode */ if (IFM_1000_T == IFM_SUBTYPE(media)) { - sc->reg_ptr->maccfg2 = + sc->reg_ptr->maccfg2 = ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK) | M83xx_TSEC_MACCFG2_IFMODE_BYT); } else { - sc->reg_ptr->maccfg2 = + sc->reg_ptr->maccfg2 = ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK) | M83xx_TSEC_MACCFG2_IFMODE_NIB); } @@ -1796,7 +1796,7 @@ int rtems_mpc83xx_tsec_mode_adapt } else { sc->reg_ptr->maccfg2 |= M83xx_TSEC_MACCFG2_FULLDUPLEX; - } + } /* * store current media state for future compares */ @@ -1825,7 +1825,7 @@ static void mpc83xx_tsec_watchdog \*=========================================================================*/ { rtems_mpc83xx_tsec_mode_adapt(ifp); - ifp->if_timer = TSEC_WATCHDOG_TIMEOUT; + ifp->if_timer = TSEC_WATCHDOG_TIMEOUT; } /*=========================================================================*\ @@ -1944,7 +1944,7 @@ static int mpc83xx_tsec_driver_attach return 0; } #else /* MPC8313ERDB */ - sc->phy_default = unitNumber-1; + sc->phy_default = unitNumber-1; #endif /* MPC8313ERDB */ /* diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c index 1977b8bdad..28a2abef05 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c @@ -101,7 +101,7 @@ static rtems_status_code mpc83xx_spi_char_mode else { if (lsb_first) { /* - * non-reversed data (LSB first): 4..16 bits valid + * non-reversed data (LSB first): 4..16 bits valid * always aligned to bit 16 of data register */ if ((bits_per_char >= 4) && @@ -226,14 +226,14 @@ static void mpc83xx_spi_irq_handler \*=========================================================================*/ { mpc83xx_spi_softc_t *softc_ptr = (mpc83xx_spi_softc_t *)handle; - + /* - * disable interrupt mask + * disable interrupt mask */ softc_ptr->reg_ptr->spim = 0; if (softc_ptr->initialized) { rtems_semaphore_release(softc_ptr->irq_sema_id); - } + } } /*=========================================================================*\ @@ -319,7 +319,7 @@ static void mpc83xx_spi_install_irq_handler */ rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'), 0, - RTEMS_FIFO + RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE, 0, &softc_ptr->irq_sema_id); @@ -374,7 +374,7 @@ rtems_status_code mpc83xx_spi_init /* * FIXME: set default mode in SPIM */ - + /* * init interrupt stuff */ @@ -415,7 +415,7 @@ int mpc83xx_spi_read_write_bytes rtems_status_code rc; int bc = 0; int bytes_per_char = softc_ptr->bytes_per_char; - int bit_shift = softc_ptr->bit_shift; + int bit_shift = softc_ptr->bit_shift; uint32_t spird_val; #if defined(DEBUG) @@ -457,11 +457,11 @@ int mpc83xx_spi_read_write_bytes */ #if defined(USE_LAST_BIT) rc = mpc83xx_spi_wait(softc_ptr, - ((len == 0) - ? MPC83XX_SPIE_LT + ((len == 0) + ? MPC83XX_SPIE_LT : MPC83XX_SPIE_NE), - ((len == 0) - ? MPC83XX_SPIE_LT + ((len == 0) + ? MPC83XX_SPIE_LT : MPC83XX_SPIE_NF) | MPC83XX_SPIE_NE, MPC83XX_SPIE_LT @@ -614,7 +614,7 @@ rtems_status_code mpc83xx_spi_set_tfr_mode spimode |= MPC83XX_SPIMODE_CP; } } - + if (rc == RTEMS_SUCCESSFUL) { /* * disable SPI @@ -653,12 +653,12 @@ int mpc83xx_spi_ioctl switch(cmd) { case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: - ret_val = + ret_val = -mpc83xx_spi_set_tfr_mode(bh, (const rtems_libi2c_tfr_mode_t *)arg); break; case RTEMS_LIBI2C_IOCTL_READ_WRITE: - ret_val = + ret_val = mpc83xx_spi_read_write_bytes(bh, ((rtems_libi2c_read_write_t *)arg)->rd_buf, ((rtems_libi2c_read_write_t *)arg)->wr_buf, diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h index ba98d3413c..7a4f2f694e 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h @@ -41,7 +41,7 @@ typedef struct mpc83xx_spi_softc { } mpc83xx_spi_softc_t ; typedef struct { - rtems_libi2c_bus_t bus_desc; + rtems_libi2c_bus_t bus_desc; mpc83xx_spi_softc_t softc; } mpc83xx_spi_desc_t; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c index 346e188a76..78cc703010 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c @@ -56,10 +56,10 @@ void Clock_exit( void ); /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + /* * ISR Handler */ @@ -104,7 +104,7 @@ void clockOn(void* unused) s_value = (plprcr_val & (0x00300000)) >> (31-11); mfi_value = (plprcr_val & (0x000f0000)) >> (31-15); pdf_value = (plprcr_val & (0x00000006)) >> (31-30); - extclk = (((uint64_t)bsp_clock_speed) + extclk = (((uint64_t)bsp_clock_speed) * ((pdf_value + 1) * (mfd_value + 1)) / (mfi_value * (mfd_value + 1) + mfn_value) * (1 << s_value)); @@ -128,7 +128,7 @@ void clockOn(void* unused) else { pit_value = (rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec); - + m8xx.sccr &= ~(1<<23); } if ((pit_value > 0xffff) || force_prescaler){ @@ -162,7 +162,7 @@ void clockOff(void* unused) { /* disable PIT and PIT interrupts */ - m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); + m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); } int clockIsOn(void* unused) @@ -203,13 +203,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c index 574120bd4f..b8dff4683b 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c @@ -122,7 +122,7 @@ m8xx_get_brg_cd (int baud) } -/* +/* * This function will fail if more that 4 baud rates have been selected * at any time since the OS started. It needs to be fixed. FIXME */ @@ -181,7 +181,7 @@ static int m8xx_smc_set_attributes (int minor, const struct termios *t) { int baud, brg=0, csize=0, ssize, psize; - uint16_t clen=0, cstopb, parenb, parodd, cread; + uint16_t clen=0, cstopb, parenb, parodd, cread; /* Baud rate */ switch (t->c_cflag & CBAUD) { @@ -209,7 +209,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) if (baud > 0) brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ /* at least 2 ports will be the same */ - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 5; break; @@ -235,15 +235,15 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) parenb = 0x0000; /* No parity on Tx and Rx */ psize = 0; } - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else parodd = 0x0100; - /* + /* * Character Length = start + data + parity + stop - 1 - */ + */ switch ( 1 + csize + psize + ssize - 1 ) { case 6: clen = 0x3000; break; case 7: clen = 0x3800; break; @@ -257,7 +257,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) cread = 0x0023; /* UART normal operation, enable Rx and Tx */ else cread = 0x0021; /* UART normal operation, enable Tx */ - + /* Write the SIMODE/SMCMR registers */ switch (minor) { case SMC1_MINOR: @@ -306,7 +306,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ /* at least 2 ports will be the same */ /* Write the SICR register below */ - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 0x0000; break; @@ -320,13 +320,13 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) cstopb = 0x4000; /* Two stop bits */ else cstopb = 0x0000; /* One stop bit */ - + /* Parity */ if ( t->c_cflag & PARENB ) parenb = 0x0010; /* Parity enabled on Tx and Rx */ else parenb = 0x0000; /* No parity on Tx and Rx */ - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else @@ -349,12 +349,12 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) break; #endif } - + return 0; } -int +int m8xx_uart_setAttributes( int minor, const struct termios *t @@ -363,7 +363,7 @@ m8xx_uart_setAttributes( /* * Check that port number is valid */ - if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) return 0; switch (minor) { @@ -396,8 +396,8 @@ static void m8xx_scc2_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC2_MINOR], @@ -438,8 +438,8 @@ m8xx_scc3_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC3_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC3_MINOR], @@ -479,8 +479,8 @@ m8xx_scc4_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC4_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC4_MINOR], @@ -520,8 +520,8 @@ m8xx_smc1_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC1_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC1_MINOR], @@ -561,8 +561,8 @@ m8xx_smc2_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC2_MINOR], @@ -641,7 +641,7 @@ int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) } static rtems_irq_connect_data consoleIrqData; - + void m8xx_uart_scc_initialize (int minor) { @@ -652,7 +652,7 @@ m8xx_uart_scc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) return; /* Get the sicr clock source bit values for 9600 bps */ @@ -694,7 +694,7 @@ m8xx_uart_scc_initialize (int minor) case SCC2_MINOR: sccparms = &m8xx.scc2p; sccregs = &m8xx.scc2; - + m8xx.papar |= 0x000C; /* PA12 & PA13 are dedicated peripheral pins */ m8xx.padir &= ~0x000C; /* PA13 & PA12 must not drive the UART lines */ m8xx.paodr &= ~0x000C; /* PA12 & PA13 are not open drain */ @@ -702,7 +702,7 @@ m8xx_uart_scc_initialize (int minor) m8xx.pcpar &= ~0x00C0; /* PC8 & PC9 are SCC2 DCD and CTS */ m8xx.pcdir &= ~0x00C2; /* PC8, PC9 & PC14 must not drive the UART lines */ m8xx.pcso |= 0x00C0; /* Enable DCD and CTS inputs */ - + m8xx.sicr &= 0xFFFF00FF; /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */ m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */ break; @@ -711,12 +711,12 @@ m8xx_uart_scc_initialize (int minor) case SCC3_MINOR: sccparms = &m8xx.scc3p; sccregs = &m8xx.scc3; - + m8xx.pcpar &= ~0x0300; /* PC6 & PC7 are SCC3 DCD and CTS */ m8xx.pcdir &= ~0x0300; /* PC6 & PC7 must not drive the UART lines */ m8xx.pcso |= 0x0300; /* Enable DCD and CTS inputs */ m8xx.pdpar |= 0x0130; /* PD7, PD10 & PD11 are dedicated peripheral pins */ - + m8xx.sicr &= 0xFF00FFFF; /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */ m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */ break; @@ -724,12 +724,12 @@ m8xx_uart_scc_initialize (int minor) case SCC4_MINOR: sccparms = &m8xx.scc4p; sccregs = &m8xx.scc4; - + m8xx.pcpar &= ~0x0C00; /* PC4 & PC5 are SCC4 DCD and CTS */ m8xx.pcdir &= ~0x0C00; /* PC4 & PC5 must not drive the UART lines */ m8xx.pcso |= 0x0C00; /* Enable DCD and CTS inputs */ m8xx.pdpar |= 0x02C0; /* PD6, PD8 & PD9 are dedicated peripheral pins */ - + m8xx.sicr &= 0x00FFFFFF; /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */ m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */ break; @@ -822,7 +822,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.on = m8xx_scc_enable; consoleIrqData.off = m8xx_scc_disable; consoleIrqData.isOn = m8xx_scc_isOn; - + switch (minor) { case SCC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC2; @@ -834,7 +834,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SCC3; consoleIrqData.hdl = m8xx_scc3_interrupt_handler; break; - + case SCC4_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC4; consoleIrqData.hdl = m8xx_scc4_interrupt_handler; @@ -895,7 +895,7 @@ m8xx_uart_smc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) + if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) return; m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */ @@ -922,7 +922,7 @@ m8xx_uart_smc_initialize (int minor) case SMC1_MINOR: smcparms = &m8xx.smc1p; smcregs = &m8xx.smc1; - + m8xx.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ m8xx.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ m8xx.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ @@ -934,16 +934,16 @@ m8xx_uart_smc_initialize (int minor) case SMC2_MINOR: smcparms = &m8xx.smc2p; smcregs = &m8xx.smc2; - + m8xx.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ m8xx.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ m8xx.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ - + m8xx.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ m8xx.simode |= brg << 28; /* SMC2CS = brg */ break; } - + /* * Set up SMC1 parameter RAM common to all protocols */ @@ -994,7 +994,7 @@ m8xx_uart_smc_initialize (int minor) m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2); break; } - + /* * Enable receiver and transmitter */ @@ -1008,7 +1008,7 @@ m8xx_uart_smc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SMC1; consoleIrqData.hdl = m8xx_smc1_interrupt_handler; break; - + case SMC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP; consoleIrqData.hdl = m8xx_smc2_interrupt_handler; @@ -1025,7 +1025,7 @@ void m8xx_uart_initialize(void) { int i; - + for (i=0; i < 4; i++) { brg_spd[i] = 0; brg_used[i] = 0; @@ -1044,7 +1044,7 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8xx_BD_EMPTY) { return -1; } - rtems_cache_invalidate_multiple_data_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[minor]->buffer, RxBd[minor]->length ); @@ -1057,7 +1057,7 @@ m8xx_uart_pollRead( /* * TODO: Get a free buffer and set it up. */ -int +int m8xx_uart_write( int minor, const char *buf, @@ -1070,7 +1070,7 @@ m8xx_uart_write( TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; return 0; } - + int m8xx_uart_pollWrite( diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c index 560299f69d..de38f0a5df 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c @@ -2,7 +2,7 @@ * cp.c * * MPC8xx CPM RISC Communication Processor routines. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -23,7 +23,7 @@ void m8xx_cp_execute_cmd( uint16_t command ) { rtems_interrupt_level lvl; - + rtems_interrupt_disable(lvl); while (m8xx.cpcr & M8xx_CR_FLG) { continue; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c index 22319c3c1b..94fcaa61c8 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c @@ -2,7 +2,7 @@ * dpram.c * * MPC8xx dual-port RAM allocation routines - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -47,16 +47,16 @@ m8xx_dpram_allocate( unsigned int byte_count ) unsigned int i; ISR_Level level; void *blockp = NULL; - + byte_count = (byte_count + 3) & ~0x3; - + /* * Running with interrupts disabled is usually considered bad * form, but this routine is probably being run as part of an * initialization sequence so the effect shouldn't be too severe. */ _ISR_Disable (level); - + for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) { /* * Verify that the region is available for use. @@ -82,9 +82,9 @@ m8xx_dpram_allocate( unsigned int byte_count ) break; } } - + _ISR_Enable(level); - + if (blockp == NULL) rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count); return blockp; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h index ddc6d19f23..f3341ed915 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h @@ -1,7 +1,7 @@ -/* +/* * cpm.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the Communications Processor Module (CPM) on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h index 5e4cd2536b..73e75a8904 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h @@ -1,7 +1,7 @@ -/* +/* * mmu.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -29,7 +29,7 @@ typedef struct { } MMU_TLB_table_t; /* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be * supplied by the BSP. */ extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h index 6aa75d1269..3222e7fd03 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h @@ -722,8 +722,8 @@ typedef struct m8xxBufferDescriptor_ { */ typedef struct m8xxIDMABufferDescriptor_ { uint16_t status; - uint8_t dfcr; - uint8_t sfcr; + uint8_t dfcr; + uint8_t sfcr; uint32_t length; void *source; void *destination; @@ -1116,14 +1116,14 @@ typedef struct m8xxIDMABufferDescriptor_ { * Value to write to a key register to unlock the corresponding SIU register */ #define M8xx_UNLOCK_KEY 0x55CCAA33 - + /* ************************************************************************* * MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * ************************************************************************* */ typedef struct m8xx_ { - + /* * SIU Block */ @@ -1144,7 +1144,7 @@ typedef struct m8xx_ { uint32_t _pad1[3]; uint32_t sdcr; uint8_t _pad2[0x80-0x34]; - + /* * PCMCIA Block */ @@ -1173,7 +1173,7 @@ typedef struct m8xx_ { uint32_t _pad5; uint32_t per; uint32_t _pad6; - + /* * MEMC Block */ @@ -1188,7 +1188,7 @@ typedef struct m8xx_ { uint16_t mptpr; uint32_t mdr; uint8_t _pad9[0x200-0x180]; - + /* * System integration timers */ @@ -1210,8 +1210,8 @@ typedef struct m8xx_ { uint16_t pitr; uint16_t _pad_14_2; uint8_t _pad15[0x280-0x24c]; - - + + /* * Clocks and Reset */ @@ -1219,8 +1219,8 @@ typedef struct m8xx_ { uint32_t plprcr; uint32_t rsr; uint8_t _pad16[0x300-0x28c]; - - + + /* * System integration timers keys */ @@ -1237,7 +1237,7 @@ typedef struct m8xx_ { uint32_t piscrk; uint32_t pitck; uint8_t _pad19[0x380-0x348]; - + /* * Clocks and Reset Keys */ @@ -1247,8 +1247,8 @@ typedef struct m8xx_ { uint8_t _pad20[0x400-0x38c]; uint8_t _pad21[0x800-0x400]; uint8_t _pad22[0x860-0x800]; - - + + /* * I2C */ @@ -1264,7 +1264,7 @@ typedef struct m8xx_ { uint8_t _pad27[3]; uint8_t i2cmr; uint8_t _pad28[0x900-0x875]; - + /* * DMA Block */ @@ -1282,7 +1282,7 @@ typedef struct m8xx_ { uint8_t _pad34[3]; uint8_t idmr2; uint8_t _pad35[0x930-0x91d]; - + /* * CPM Interrupt Control Block */ @@ -1292,7 +1292,7 @@ typedef struct m8xx_ { uint32_t cipr; uint32_t cimr; uint32_t cisr; - + /* * I/O Port Block */ @@ -1312,7 +1312,7 @@ typedef struct m8xx_ { uint16_t _pad40; uint16_t pddat; uint8_t _pad41[8]; - + /* * CPM Timers Block */ @@ -1358,7 +1358,7 @@ typedef struct m8xx_ { uint16_t _pad47; uint16_t rtmr; uint8_t _pad48[0x9f0-0x9dc]; - + /* * BRG Block */ @@ -1366,7 +1366,7 @@ typedef struct m8xx_ { uint32_t brgc2; uint32_t brgc3; uint32_t brgc4; - + /* * SCC Block */ @@ -1384,7 +1384,7 @@ typedef struct m8xx_ { */ m8xxSMCRegisters_t smc1; m8xxSMCRegisters_t smc2; - + /* * SPI Block */ @@ -1397,7 +1397,7 @@ typedef struct m8xx_ { uint8_t _pad52[2]; uint8_t spcom; uint16_t _pad53[2]; - + /* * PIP Block */ @@ -1410,7 +1410,7 @@ typedef struct m8xx_ { uint16_t pbodr; uint32_t pbdat; uint32_t _pad56[6]; - + /* * SI Block */ @@ -1434,7 +1434,7 @@ typedef struct m8xx_ { uint8_t lcdram[512]; #endif uint8_t _pad62[0x2000-0x1000]; - + /* * Dual-port RAM */ @@ -1444,11 +1444,11 @@ typedef struct m8xx_ { uint8_t dpram3[0x600]; /* BD/DATA*/ uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ uint8_t _pad63[0x3c00-0x3000]; - + /* When using SCC1 for ethernet, we lose the use of I2C since * their parameters would overlap. Motorola has a microcode * patch to move parameters around so that both can be used - * together. It is available on their web site somewhere + * together. It is available on their web site somewhere * under http://www.mot.com/mpc8xx. If ethernet is used on * one (or more) of the other SCCs, then other CPM features * will be unavailable: @@ -1463,7 +1463,7 @@ typedef struct m8xx_ { uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; m8xxIDMAparms_t idma1p; uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; - + m8xxSCCparms_t scc2p; uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; m8xxSPIparms_t spip; @@ -1472,14 +1472,14 @@ typedef struct m8xx_ { uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; m8xxIDMAparms_t idma2p; uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; - + m8xxSCCparms_t scc3p; /* Not available on MPC821 */ uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; m8xxSMCparms_t smc1p; uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; m8xxDSPparms_t dsp1p; uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; - + m8xxSCCparms_t scc4p; /* Not available on MPC821 */ uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; m8xxSMCparms_t smc2p; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c index 4fa55701cd..fbf2d2eeb0 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @@ -1,7 +1,7 @@ -/* +/* * mmu.c - * - * This file contains routines for initializing + * + * This file contains routines for initializing * and manipulating the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -20,18 +20,18 @@ /* * mmu_init * - * This routine sets up the virtual memory maps on an MPC8xx. - * The MPC8xx does not support block address translation (BATs) - * and does not have segment registers. Thus, we must set up page + * This routine sets up the virtual memory maps on an MPC8xx. + * The MPC8xx does not support block address translation (BATs) + * and does not have segment registers. Thus, we must set up page * translation. However, its MMU supports variable size pages * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. * - * The MPC8xx has separate data and instruction 32-entry translation - * lookaside buffers (TLB). By mapping all of DRAM as one huge page, - * we can preload the TLBs and not have to be concerned with taking + * The MPC8xx has separate data and instruction 32-entry translation + * lookaside buffers (TLB). By mapping all of DRAM as one huge page, + * we can preload the TLBs and not have to be concerned with taking * TLB miss exceptions. * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ void mmu_init( void ) @@ -46,14 +46,14 @@ void mmu_init( void ) * We can assume the MSR has already been set this way. */ - /* + /* * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) * GPM [0] 0b0 = PowerPC mode * PPM [1] 0b0 = Page resolution of protection - * CIDEF [2] 0b0/0b0 = Default cache-inhibit attribute = + * CIDEF [2] 0b0/0b0 = Default cache-inhibit attribute = * NO for IMMU, NO for DMMU * NOTE: it is vital that data caching is ON, when - * DMMU is off, otherwise valid/dirty values in + * DMMU is off, otherwise valid/dirty values in * cache would be ignored during exception entry * reserved/WTDEF [3] 0b0 = Default write-through attribute = not * RSV4x [4] 0b0 = 4 entries not reserved @@ -62,7 +62,7 @@ void mmu_init( void ) * reserved [7-18] 0x00 * xTLB_INDX [19-23] 31 = 0x1F * reserved [24-31] 0x00 - * + * * Note: It is important that cache-inhibit be set as the default for the * data cache when the DMMU is disabled in order to prevent internal memory * mapped registers from being cached accidentally when address translation @@ -73,15 +73,15 @@ void mmu_init( void ) reg1 = M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); _mtspr( M8xx_MD_CTR, reg1 ); _isync; - - /* + + /* * Invalidate all TLB entries in both TLBs. * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so * all 32 entries are invalidated. */ __asm__ volatile ("tlbia\n"::); _isync; - + /* * Set Current Address Space ID Register (M_CASID). * Supervisor: CASID = 0 @@ -89,7 +89,7 @@ void mmu_init( void ) reg1 = 0; _mtspr( M8xx_M_CASID, reg1 ); - /* + /* * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) * We ignore the Access Protection Group (APG) mechanism globally * by setting all of the Mx_AP fields to 0b01 : client access @@ -99,10 +99,10 @@ void mmu_init( void ) _mtspr( M8xx_MI_AP, reg1 ); _mtspr( M8xx_MD_AP, reg1 ); - /* + /* * Load both 32-entry TLBs with values from the MMU_TLB_table * which is defined in the BSP. - * Note the _TLB_Table must have at most 32 entries. This code + * Note the _TLB_Table must have at most 32 entries. This code * makes no effort to enforce this restriction. */ for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { @@ -117,9 +117,9 @@ void mmu_init( void ) _mtspr( M8xx_MD_RPN, reg1 ); } - /* + /* * Turn on address translation by setting MSR[IR] and MSR[DR]. - */ + */ _CPU_MSR_GET( reg1 ); reg1 |= PPC_MSR_IR | PPC_MSR_DR; _CPU_MSR_SET( reg1 ); diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c index 517b2a90d8..3258d46b49 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c @@ -67,7 +67,7 @@ void benchmark_timer_initialize(void) /* set interrupt level and enable timebase. This should never */ /* generate an interrupt however. */ m8xx.tbscr |= M8xx_TBSCR_TBIRQ(4) | M8xx_TBSCR_TBE; - + Timer_starting = get_itimer(); } diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S b/c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S index 45a0f3ea73..bf2c5f528a 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S @@ -24,11 +24,11 @@ codemove: beq 7f /* Protect against 0 count */ mtctr r0 bge cr1,2f - + la r8,-4(r4) la r7,-4(r3) 1: lwzu r0,4(r8) - stwu r0,4(r7) + stwu r0,4(r7) bdnz 1b b 4f @@ -38,23 +38,23 @@ codemove: 3: lwzu r0,-4(r8) stwu r0,-4(r7) bdnz 3b - + /* Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. + * address. Otherwise we might miss one cache line. */ 4: cmpwi r6,0 add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ + beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 mr r4,r3 -5: cmplw r4,r5 +5: cmplw r4,r5 dcbst 0,r4 add r4,r4,r6 blt 5b sync /* Wait for all dcbst to complete on bus */ mr r4,r3 -6: cmplw r4,r5 +6: cmplw r4,r5 icbi 0,r4 add r4,r4,r6 blt 6b diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c index 96495640e3..ae38bb6471 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c @@ -40,7 +40,7 @@ SPR_RW(PPC405_TSR) /* legacy mode for bookE DEC exception; * to avoid the double layer of function calls * (dec_handler_bookE -> C_dispatch_irq_handler -> user handler) - * it is preferrable for the user to hook the DEC + * it is preferrable for the user to hook the DEC * exception directly. * However, the legacy mode works with less modifications * of user code. @@ -52,11 +52,11 @@ int C_dispatch_dec_handler_bookE (BSP_Exception_frame *frame, unsigned int excNu * re-enables MSR_EE. * Note that PPC405 uses a different SPR# for TSR */ - if ( ppc_cpu_is_bookE()==PPC_BOOKE_405) + if ( ppc_cpu_is_bookE()==PPC_BOOKE_405) _write_PPC405_TSR( BOOKE_TSR_DIS ); else _write_BOOKE_TSR( BOOKE_TSR_DIS ); - return C_dispatch_irq_handler(frame, ASM_DEC_VECTOR); + return C_dispatch_irq_handler(frame, ASM_DEC_VECTOR); } /* @@ -348,7 +348,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) for ( i = config->irqBase; i < config->irqBase + config->irqNb; i++ ) { for( vchain = &rtems_hdl_tbl[i]; - ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); + ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); vchain = (rtems_irq_connect_data*)vchain->next_handler ) { if (vchain->on) @@ -361,9 +361,9 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) /* Do NOT disable; there might be boards with cascaded * interrupt controllers where the BSP (incorrectly) does * not ignore the cascaded interrupts in BSP_disable_irq_at_pic()! - * Instead, we rely on BSP_setup_the_pic() for a good - * initial configuration. - * + * Instead, we rely on BSP_setup_the_pic() for a good + * initial configuration. + * BSP_disable_irq_at_pic(i); */ } @@ -374,7 +374,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) { ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler); - if ( ppc_cpu_is_bookE() ) { + if ( ppc_cpu_is_bookE() ) { /* bookE decrementer interrupt needs to be cleared BEFORE * dispatching the user ISR (because the user ISR is called * with EE enabled) diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h index 529c98c1f5..7573c961cf 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h @@ -8,7 +8,7 @@ #ifndef IRQ_SHARED_IRQ_C_GLUE_H #define IRQ_SHARED_IRQ_C_GLUE_H -/* +/* * This header describes the routines that are needed by the shared * version of 'irq.c' (implementing the RTEMS irq API). They * must be provided by the BSP. diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c index 45ec497bdc..048a08021e 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c @@ -21,7 +21,7 @@ * * The timer_isr prints a message then polls * the variable 'timer_poll' while it has the value - * of the timer # then sets it to -1 and prints + * of the timer # then sets it to -1 and prints * the 'leave' message. * * To test nested interrupts: @@ -49,7 +49,7 @@ * The timer IRQs can be unhooked with * timer_instdis( 0, 0, period ); * timer_instdis( 1, 0, period ); - */ + */ #include <rtems.h> #include <rtems/bspIo.h> #include <bsp/openpic.h> @@ -74,7 +74,7 @@ uint32_t lat = (OpenPIC->Global.Timer[(int)p].Current_Count & 0x7fffffff); while ( timer_poll == (int)p ) ; timer_poll = -1; - + printk("Leaving ISR (%i)\n",(int)p); } diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc-code-copy.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc-code-copy.c index 9e327e5141..d631b1268a 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc-code-copy.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc-code-copy.c @@ -36,4 +36,4 @@ void ppc_code_copy(void *dest, const void *src, size_t n) rtems_cache_invalidate_multiple_instruction_lines(dest, n); ppc_synchronize_instructions(); } -} +} diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h index f4ab803624..98ac23f347 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h @@ -59,7 +59,7 @@ * 3. load register with vector info * 4. branch * - */ + */ /* ***************************************************************************** @@ -99,7 +99,7 @@ ppc_exc_min_prolog_async_\_NAME: stw r1, ppc_exc_lock_\_PRI@sdarel(r13) /* We have no stack frame yet; store VECTOR_REGISTER in special area; * a higher-priority (critical) interrupt uses a different area - * (hence the different prologue snippets) (\PRI) + * (hence the different prologue snippets) (\PRI) */ stw VECTOR_REGISTER, ppc_exc_vector_register_\_PRI@sdarel(r13) /* Load vector. @@ -131,7 +131,7 @@ ppc_exc_min_prolog_sync_\_NAME: ba wrap_nopush_\_FLVR .endm - + /* ***************************************************************************** * MACRO: TEST_1ST_OPCODE_crit @@ -199,7 +199,7 @@ ppc_exc_min_prolog_sync_\_NAME: GET_INTERRUPT_MASK mask=SCRATCH_REGISTER_1 /* EQ(cr0) = ((interrupt_mask & MSR_CE) == 0) */ andis. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_CE@h - beq TEST_LOCK_crit_done_\_FLVR + beq TEST_LOCK_crit_done_\_FLVR /* STD interrupt could have been interrupted before executing the 1st * instruction which sets the lock; check this case by looking at the @@ -212,7 +212,7 @@ ppc_exc_min_prolog_sync_\_NAME: * *(PC) == 'stw r1, ppc_exc_lock_std@sdarel(r13)' * */ - + /* check lock */ lwz SCRATCH_REGISTER_1, ppc_exc_lock_std@sdarel(r13) cmplwi CR_LOCK, SCRATCH_REGISTER_1, 0 @@ -544,7 +544,7 @@ wrap_change_msr_done_\_FLVR: * We add FRAME_LINK_SPACE to the frame pointer because the high level * handler expects a BSP_Exception_frame structure. */ - addi r3, FRAME_REGISTER, FRAME_LINK_SPACE + addi r3, FRAME_REGISTER, FRAME_LINK_SPACE /* * Second parameter = vector number (r4 is the VECTOR_REGISTER) @@ -611,7 +611,7 @@ wrap_handler_done_\_FLVR: LA SCRATCH_REGISTER_0, ppc_exc_wrapup /* First parameter = exception frame pointer + FRAME_LINK_SPACE */ - addi r3, FRAME_REGISTER, FRAME_LINK_SPACE + addi r3, FRAME_REGISTER, FRAME_LINK_SPACE /* Call ppc_exc_wrapup() */ mtctr SCRATCH_REGISTER_0 @@ -633,7 +633,7 @@ wrap_restore_msr_done_\_FLVR: lwz FRAME_REGISTER, FRAME_OFFSET(r1) /* Restore XER and CTR */ - lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1) + lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1) lwz SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) mtxer SCRATCH_REGISTER_0 mtctr SCRATCH_REGISTER_1 @@ -728,7 +728,7 @@ wrap_restore_non_volatile_regs_\_FLVR: /* Restore small data area anchor (SYSV) */ lwz r13, GPR13_OFFSET(r1) - + /* r14 is the FRAME_REGISTER and will be restored elsewhere */ /* Restore non-volatile registers r15 .. r31 */ @@ -742,7 +742,7 @@ wrap_restore_non_volatile_regs_\_FLVR: wrap_call_global_handler_\_FLVR: /* First parameter = exception frame pointer + FRAME_LINK_SPACE */ - addi r3, FRAME_REGISTER, FRAME_LINK_SPACE + addi r3, FRAME_REGISTER, FRAME_LINK_SPACE /* Load global handler address */ LW SCRATCH_REGISTER_0, globalExceptHdl diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h index 55fe5c1a1d..446e514984 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h @@ -40,7 +40,7 @@ extern "C" { typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned int vector); /* - * Bits in MSR that are enabled during execution of exception handlers / ISRs + * Bits in MSR that are enabled during execution of exception handlers / ISRs * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should * be set to 0 during initialization) * @@ -95,7 +95,7 @@ typedef uint32_t ppc_exc_min_prolog_t[4]; /* Templates are ppc_raw_except_func BUT they must be exactly 16 bytes */ typedef rtems_raw_except_func ppc_exc_min_prolog_template_t; -/* +/* * Expand a prolog template into 'buf' using vector 'vec' */ void diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c index 5d2de9dc3e..1d635c58e9 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c @@ -12,7 +12,7 @@ * * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> * - * Copyright (C) 2009 embedded brains GmbH. + * Copyright (C) 2009 embedded brains GmbH. * * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/vectors_init.c". * Derived from file "libcpu/powerpc/new-exceptions/e500_raw_exc_init.c". diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_naked.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_naked.S index 1c4a3b8462..f0f8d3af92 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_naked.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_naked.S @@ -106,7 +106,7 @@ wrap_change_msr_done_naked: * We add FRAME_LINK_SPACE to the frame pointer because the high level * handler expects a BSP_Exception_frame structure. */ - addi r3, r1, FRAME_LINK_SPACE + addi r3, r1, FRAME_LINK_SPACE /* * Second parameter = vector number (r4 is the VECTOR_REGISTER) @@ -127,7 +127,7 @@ wrap_change_msr_done_naked: wrap_restore_msr_done_naked: /* Restore XER and CTR */ - lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1) + lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1) lwz SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) mtxer SCRATCH_REGISTER_0 mtctr SCRATCH_REGISTER_1 diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c index b259589aa6..86892fa616 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c @@ -9,7 +9,7 @@ /* * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> * - * Copyright (C) 2009 embedded brains GmbH. + * Copyright (C) 2009 embedded brains GmbH. * * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h index 63fd206f70..d1b2230a2d 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h @@ -7,29 +7,29 @@ * @brief PowerPC Exceptions API. */ -/* - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. * * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> - * - * Copyright (C) 2009 embedded brains GmbH. - * - * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> - * to support 603, 603e, 604, 604e exceptions - * - * Moved to "libcpu/powerpc/new-exceptions" and consolidated - * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> - * to be common for all PPCs with new exceptions. - * + * + * Copyright (C) 2009 embedded brains GmbH. + * + * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> + * to support 603, 603e, 604, 604e exceptions + * + * Moved to "libcpu/powerpc/new-exceptions" and consolidated + * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + * to be common for all PPCs with new exceptions. + * * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ */ /* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */ @@ -413,7 +413,7 @@ typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); /** * @brief Bits for MSR update. * - * Bits in MSR that are enabled during execution of exception handlers / ISRs + * Bits in MSR that are enabled during execution of exception handlers / ISRs * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should * be set to 0 during initialization) * diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c index 8008f3b5ea..4f42cb5b00 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c @@ -123,7 +123,7 @@ void _CPU_Context_Initialize( #if (PPC_ABI == PPC_ABI_SVR4) /* - * SVR4 says R2 is for 'system-reserved' use; it cannot hurt to + * SVR4 says R2 is for 'system-reserved' use; it cannot hurt to * propagate R2 to all task contexts. */ { uint32_t r2 = 0; @@ -171,8 +171,8 @@ void _CPU_Install_interrupt_stack( void ) void _CPU_ISR_install_vector( uint32_t vector, proc_ptr new_handler, - proc_ptr *old_handler -) + proc_ptr *old_handler +) { BSP_panic("_CPU_ISR_install_vector called\n"); } diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c index afd282acdb..c9d9243b52 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c @@ -67,7 +67,7 @@ static uint32_t pit_value, tick_time; static bool auto_restart; void Clock_exit( void ); - + rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry handler, /* isr routine */ rtems_vector_number vector, /* vector number */ @@ -77,10 +77,10 @@ rtems_isr_entry set_vector( /* returns old vector */ /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + static inline uint32_t get_itimer(void) { register uint32_t rc; @@ -117,10 +117,10 @@ void Clock_isr(void* handle) * setup for next interrupt; making sure the new value is reasonably * in the future.... in case we lost out on an interrupt somehow */ - + itimer_value = get_itimer(); tick_time += pit_value; - + /* * how far away is next interrupt *really* * It may be a long time; this subtraction works even if @@ -128,42 +128,42 @@ void Clock_isr(void* handle) * the miracle of unsigned math. */ clicks_til_next_interrupt = tick_time - itimer_value; - + /* * If it is too soon then bump it up. * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. * But setting it low is useful for debug, so... */ - + if (clicks_til_next_interrupt < 400) { tick_time = itimer_value + 1000; clicks_til_next_interrupt = 1000; /* XXX: count these! this should be rare */ } - + /* * If it is too late, that means we missed the interrupt somehow. * Rather than wait 35-50s for a wrap, we just fudge it here. */ - + if (clicks_til_next_interrupt > pit_value) { tick_time = itimer_value + 1000; clicks_til_next_interrupt = 1000; /* XXX: count these! this should never happen :-) */ } - - asm volatile ("mtspr 0x3db, %0" :: "r" + + asm volatile ("mtspr 0x3db, %0" :: "r" (clicks_til_next_interrupt)); /* PIT */ } - + asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ - + Clock_driver_ticks++; /* Give BSP a chance to say if they want to re-enable interrupts */ - + #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL) _ISR_Set_level(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL); #endif @@ -183,9 +183,9 @@ void Clock_isr(void* handle) int ClockIsOn(const rtems_irq_connect_data* unused) { register uint32_t tcr; - + asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ - + return (tcr & 0x04000000) != 0; } #endif @@ -199,12 +199,12 @@ void ClockOff( ) { register uint32_t tcr; - + asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ - + tcr &= ~ 0x04400000; - - asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ + + asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ } void ClockOn( @@ -222,9 +222,9 @@ void ClockOn( #ifdef ppc403 uint32_t pvr; #endif /* ppc403 */ - + Clock_driver_ticks = 0; - + #ifndef ppc405 /* this is a ppc403 */ asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ if (bsp_timer_internal_clock) { @@ -234,21 +234,21 @@ void ClockOn( iocr |= 4; /* select external timer clock */ } asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ - + asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */ if (((pvr & 0xffff0000) >> 16) != 0x0020) return; /* Not a ppc403 */ - + if ((pvr & 0xff00) == 0x0000) /* 403GA */ #if 0 /* FIXME: in which processor versions will "autoload" work properly? */ auto_restart = (pvr & 0x00f0) > 0x0000 ? true : false; -#else +#else /* no known chip version supports auto restart of timer... */ auto_restart = false; #endif else if ((pvr & 0xff00) == 0x0100) /* 403GB */ auto_restart = true; - + #else /* ppc405 */ asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */ if (bsp_timer_internal_clock) { @@ -268,20 +268,20 @@ void ClockOn( #endif /* ppc405 */ pit_value = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec; - + /* * Set PIT value */ asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ - - /* + + /* * Set timer to autoreload, bit TCR->ARE = 1 0x0400000 * Enable PIT interrupt, bit TCR->PIE = 1 0x4000000 */ tick_time = get_itimer() + pit_value; - asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ + asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000); #if 1 asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ @@ -304,9 +304,9 @@ void Install_clock( #ifdef ppc403 uint32_t pvr; #endif /* ppc403 */ - + Clock_driver_ticks = 0; - + /* * initialize the interval here * First tick is set to right amount of time in the future @@ -355,9 +355,9 @@ ReInstall_clock( ) { uint32_t isrlevel = 0; - + rtems_interrupt_disable(isrlevel); - + #if PPC_HAS_CLASSIC_EXCEPTIONS { rtems_isr_entry previous_isr; @@ -372,15 +372,15 @@ ReInstall_clock( #else { rtems_irq_connect_data clockIrqConnData; - + clockIrqConnData.name = BSP_PIT; if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { printk("Unable to stop system clock\n"); rtems_fatal_error_occurred(1); } - + BSP_remove_rtems_irq_handler (&clockIrqConnData); - + clockIrqConnData.on = ClockOn; clockIrqConnData.off = ClockOff; clockIrqConnData.isOn = ClockIsOn; @@ -402,15 +402,15 @@ ReInstall_clock( * Called via atexit() * Remove the clock interrupt handler by setting handler to NULL * - * This will not work on the 405GP because - * when bit's are set in TCR they can only be unset by a reset + * This will not work on the 405GP because + * when bit's are set in TCR they can only be unset by a reset */ void Clock_exit(void) { #if PPC_HAS_CLASSIC_EXCEPTIONS ClockOff(); - + (void) set_vector(0, PPC_IRQ_PIT, 1); #elif defined(BSP_PPC403_CLOCK_HOOK_EXCEPTION) ClockOff(); @@ -418,13 +418,13 @@ void Clock_exit(void) #else { rtems_irq_connect_data clockIrqConnData; - + clockIrqConnData.name = BSP_PIT; if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { printk("Unable to stop system clock\n"); rtems_fatal_error_occurred(1); } - + BSP_remove_rtems_irq_handler (&clockIrqConnData); } #endif @@ -437,13 +437,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c index 041e6f9aa9..73f629c4d0 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c +++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock_4xx.c @@ -62,7 +62,7 @@ volatile uint32_t Clock_driver_ticks; static uint32_t pit_value, tick_time; void Clock_exit( void ); - + rtems_isr_entry set_vector( /* returns old vector */ rtems_isr_entry handler, /* isr routine */ rtems_vector_number vector, /* vector number */ @@ -76,10 +76,10 @@ extern bool bsp_timer_internal_clock; /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + /* * ISR Handler */ @@ -99,7 +99,7 @@ int ClockIsOn(const rtems_irq_connect_data* unused) void ClockOff(const rtems_irq_connect_data* unused) { register uint32_t r; - + r = mfspr(TCR); mtspr(TCR, r & ~(PIE | ARE) ); } @@ -109,7 +109,7 @@ void ClockOn(const rtems_irq_connect_data* unused) uint32_t iocr, r; ppc_cpu_id_t cpu; Clock_driver_ticks = 0; - + cpu = get_ppc_cpu_type(); if (cpu==PPC_405GP) { iocr = mfdcr(CPC0_CR1); @@ -138,7 +138,7 @@ void ClockOn(const rtems_irq_connect_data* unused) void Install_clock(void (*clock_isr)(void *)) { - + /* * initialize the interval here * First tick is set to right amount of time in the future @@ -193,14 +193,14 @@ ReInstall_clock(void (*new_clock_isr)(void *)) * Called via atexit() * Remove the clock interrupt handler by setting handler to NULL * - * This will not work on the 405GP because - * when bit's are set in TCR they can only be unset by a reset + * This will not work on the 405GP because + * when bit's are set in TCR they can only be unset by a reset */ void Clock_exit(void) { rtems_irq_connect_data clockIrqConnData; - + clockIrqConnData.name = BSP_PIT; if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { printk("Unable to stop system clock\n"); @@ -217,12 +217,12 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/ppc403/console/console.c b/c/src/lib/libcpu/powerpc/ppc403/console/console.c index 617f93a0fc..a7bb3dec51 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/console/console.c +++ b/c/src/lib/libcpu/powerpc/ppc403/console/console.c @@ -5,12 +5,12 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. * changes include interrupt support and termios support - * for backward compatibility, the original polled driver has been + * for backward compatibility, the original polled driver has been * renamed to console.c.polled - * + * * This file has been initially created (polled version) by * * Author: Andrew Bray <andy@i-cubed.co.uk> @@ -205,7 +205,7 @@ spiStopRemoteTx (int minor) return 0; } -void +void spiBaudSet(uint32_t baudrate) { uint32_t tmp; @@ -266,8 +266,8 @@ spiPollRead (int minor) port->SPLS = (LSRFramingError | LSROverrunError | LSRParityError | LSRBreakInterrupt); } - } - return port->SPRB; + } + return port->SPRB; } static int @@ -278,9 +278,9 @@ spiInterruptWrite (int minor, const char *buf, int len) return 0; } -static int +static int spiPollWrite(int minor,const char *buf,int len) -{ +{ unsigned char status; while (len-- > 0) { @@ -295,18 +295,18 @@ spiPollWrite(int minor,const char *buf,int len) return 0; } -/* +/* * - * deinit SPI + * deinit SPI * */ void -spiDeInit(void) +spiDeInit(void) { extern uint32_t bsp_serial_rate; /* - * disable interrupts for serial port - * set it to state to work with polling boot monitor, if any... + * disable interrupts for serial port + * set it to state to work with polling boot monitor, if any... */ /* set up baud rate to original state */ @@ -317,8 +317,8 @@ spiDeInit(void) LSRParityError | LSRBreakInterrupt); /* set up port control: DTR/RTS active,8 bit,1 stop,no parity */ - port->SPCTL = (CRNormal | - CRDtr | CRRts | + port->SPCTL = (CRNormal | + CRDtr | CRRts | CRWordLength8 | CRParityDisable | CRStopBitsOne); /* clear handshake status bits */ @@ -330,13 +330,13 @@ spiDeInit(void) } -/* +/* * - * init SPI + * init SPI * */ -rtems_status_code -spiInitialize(void) +rtems_status_code +spiInitialize(void) { register unsigned tmp; rtems_isr_entry previous_isr; /* this is a dummy */ @@ -344,12 +344,12 @@ spiInitialize(void) extern uint32_t bsp_serial_rate; /* - * Initialise the serial port + * Initialise the serial port */ - /* - * select RTS/CTS hardware handshake lines, - * select clock source + /* + * select RTS/CTS hardware handshake lines, + * select clock source */ asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */ @@ -366,8 +366,8 @@ spiInitialize(void) spiBaudSet(bsp_serial_rate); /* set up port control: DTR/RTS active,8 bit,1 stop,no parity */ - port->SPCTL = (CRNormal | - CRDtr | CRRts | + port->SPCTL = (CRNormal | + CRDtr | CRRts | CRWordLength8 | CRParityDisable | CRStopBitsOne); /* clear handshake status bits */ @@ -445,7 +445,7 @@ rtems_device_driver console_initialize( /* * Open entry point */ - + rtems_device_driver console_open( rtems_device_major_number major, rtems_device_minor_number minor, @@ -477,7 +477,7 @@ rtems_device_driver console_open( if (ppc403_spi_interrupt) { rtems_libio_open_close_args_t *args = arg; - + sc = rtems_termios_open (major, minor, arg, &intrCallbacks); spittyp = args->iop->data1; } @@ -486,11 +486,11 @@ rtems_device_driver console_open( } return sc; } - + /* * Close entry point */ - + rtems_device_driver console_close( rtems_device_major_number major, rtems_device_minor_number minor, @@ -499,11 +499,11 @@ rtems_device_driver console_close( { return rtems_termios_close (arg); } - + /* * read bytes from the serial port. We only have stdin. */ - + rtems_device_driver console_read( rtems_device_major_number major, rtems_device_minor_number minor, @@ -512,11 +512,11 @@ rtems_device_driver console_read( { return rtems_termios_read (arg); } - + /* * write bytes to the serial port. Stdout and stderr are the same. */ - + rtems_device_driver console_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -525,11 +525,11 @@ rtems_device_driver console_write( { return rtems_termios_write (arg); } - + /* * IO Control entry point */ - + rtems_device_driver console_control( rtems_device_major_number major, rtems_device_minor_number minor, diff --git a/c/src/lib/libcpu/powerpc/ppc403/console/console405.c b/c/src/lib/libcpu/powerpc/ppc403/console/console405.c index cf54621d57..ecba975d8d 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/console/console405.c +++ b/c/src/lib/libcpu/powerpc/ppc403/console/console405.c @@ -5,12 +5,12 @@ * IMD Ingenieurbuero fuer Microcomputertechnik * * COPYRIGHT (c) 1998 by IMD - * + * * Changes from IMD are covered by the original distributions terms. * changes include interrupt support and termios support - * for backward compatibility, the original polled driver has been + * for backward compatibility, the original polled driver has been * renamed to console.c.polled - * + * * This file has been initially created (polled version) by * * Author: Andrew Bray <andy@i-cubed.co.uk> @@ -110,7 +110,7 @@ struct async { /*---------------------------------------------------------------------------+ | Alternate function registers +---------------------------------------------------------------------------*/ - #define AFR ISR + #define AFR ISR /*---------------------------------------------------------------------------+ | Line control Register. @@ -190,7 +190,7 @@ static int spiBaudRound(double x) return (int)((int)((x-(int)x)*1000)>500 ? x+1 : x); } -void +void spiBaudSet(uint32_t baudrate) { uint32_t tmp; @@ -250,13 +250,13 @@ spiPollRead (int minor) /* Wait for character */ while ((port->LSR & LSR_RSR)==0);; - return port->RBR; + return port->RBR; } -static int +static int spiPollWrite(int minor,const char *buf,int len) -{ +{ while (len-- > 0) { while (!(port->LSR & LSR_THE));; @@ -275,7 +275,7 @@ spiStartRemoteTx (int minor) rtems_interrupt_level level; rtems_interrupt_disable (level); - port->SPCTL |= CRRts; activate RTS + port->SPCTL |= CRRts; activate RTS rtems_interrupt_enable (level); */ return 0; @@ -288,7 +288,7 @@ spiStopRemoteTx (int minor) rtems_interrupt_level level; rtems_interrupt_disable (level); - port->SPCTL &= ~CRRts; deactivate RTS + port->SPCTL &= ~CRRts; deactivate RTS rtems_interrupt_enable (level); */ return 0; @@ -308,12 +308,12 @@ static rtems_isr serial_ISR(rtems_vector_number v) int res; _isr=port->ISR & 0x0E; - + if ((_isr == ISR_Rx) || (_isr==ISR_RxTO)) { ch = port->RBR; rtems_termios_enqueue_raw_characters (spittyp,&ch,1); } - + if (_isr == ISR_Tx) { res = rtems_termios_dequeue_characters (spittyp,1); if (res==0) { @@ -324,18 +324,18 @@ static rtems_isr serial_ISR(rtems_vector_number v) } -/* +/* * - * deinit SPI + * deinit SPI * */ void -spiDeInit(void) +spiDeInit(void) { extern uint32_t bsp_serial_rate; /* - * disable interrupts for serial port - * set it to state to work with polling boot monitor, if any... + * disable interrupts for serial port + * set it to state to work with polling boot monitor, if any... */ @@ -346,13 +346,13 @@ spiDeInit(void) } -/* +/* * - * init SPI + * init SPI * */ -rtems_status_code -spiInitialize(void) +rtems_status_code +spiInitialize(void) { register unsigned tmp; rtems_isr_entry previous_isr; /* this is a dummy */ @@ -361,10 +361,10 @@ spiInitialize(void) extern uint32_t bsp_serial_rate; /* - * Initialise the serial port + * Initialise the serial port */ - /* + /* * Select clock source and set uart internal clock divisor */ @@ -386,11 +386,11 @@ spiInitialize(void) /* set up baud rate */ spiBaudSet(bsp_serial_rate); - + if (ppc403_spi_interrupt) { /* add rx/tx isr to vector table */ - if (USE_UART==0) + if (USE_UART==0) ictrl_set_vector(serial_ISR,PPC_IRQ_EXT_UART0,&previous_isr); else ictrl_set_vector(serial_ISR,PPC_IRQ_EXT_UART1,&previous_isr); @@ -458,7 +458,7 @@ rtems_device_driver console_initialize( /* * Open entry point */ - + rtems_device_driver console_open( rtems_device_major_number major, rtems_device_minor_number minor, @@ -498,11 +498,11 @@ rtems_device_driver console_open( } return sc; } - + /* * Close entry point */ - + rtems_device_driver console_close( rtems_device_major_number major, rtems_device_minor_number minor, @@ -511,11 +511,11 @@ rtems_device_driver console_close( { return rtems_termios_close (arg); } - + /* * read bytes from the serial port. We only have stdin. */ - + rtems_device_driver console_read( rtems_device_major_number major, rtems_device_minor_number minor, @@ -524,11 +524,11 @@ rtems_device_driver console_read( { return rtems_termios_read (arg); } - + /* * write bytes to the serial port. Stdout and stderr are the same. */ - + rtems_device_driver console_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -537,11 +537,11 @@ rtems_device_driver console_write( { return rtems_termios_write (arg); } - + /* * IO Control entry point */ - + rtems_device_driver console_control( rtems_device_major_number major, rtems_device_minor_number minor, diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h index e64fc2d936..e1d1b67409 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405ex.h @@ -3,7 +3,7 @@ Constants for manipulating system registers of PPC 405EX in C -Michael Hamel ADInstruments May 2008 +Michael Hamel ADInstruments May 2008 */ diff --git a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h index 814f18d046..792f32193f 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h +++ b/c/src/lib/libcpu/powerpc/ppc403/include/ppc405gp.h @@ -73,7 +73,7 @@ enum { kEMACSoftRst = 0x20000000, kEMACTxEnable = 0x10000000, kEMACRxEnable = 0x08000000, - + // Mode 1 bits kEMACFullDuplex = 0x80000000, kEMACIgnoreSQE = 0x01000000, @@ -82,11 +82,11 @@ enum { kEMAC2KTxFIFO = 0x00080000, kEMACTx0Multi = 0x00008000, kEMACTxDependent= 0x00014000, - + // Tx mode bits kEMACNewPacket0 = 0x80000000, kEMACNewPacket1 = 0x40000000, - + // Receive mode bits kEMACStripPadding = 0x80000000, kEMACStripFCS = 0x40000000, @@ -99,7 +99,7 @@ enum { kEMACHashRcv = 0x00200000, kEMACBrcastRcv = 0x00100000, kEMACMultcastRcv = 0x00080000, - + // Buffer descriptor control bits kMALTxReady = 0x8000, kMALRxEmpty = 0x8000, @@ -108,7 +108,7 @@ enum { kMALLast = 0x1000, kMALRxFirst = 0x0800, kMALInterrupt = 0x0400, - + // EMAC Tx descriptor bits sent kEMACGenFCS = 0x200, kEMACGenPad = 0x100, @@ -116,7 +116,7 @@ enum { kEMACRepSrcAddr = 0x040, kEMACInsVLAN = 0x020, kEMACRepVLAN = 0x010, - + // EMAC TX descriptor bits returned kEMACErrMask = 0x3FF, kEMACFCSWrong = 0x200, @@ -129,7 +129,7 @@ enum { kEMACOneColl = 0x004, kEMACUnderrun = 0x002, kEMACSQEFail = 0x001, - + // EMAC Rx descriptor bits returned kEMACOverrun = 0x200, kEMACPausePkt = 0x100, diff --git a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c index 22580a7d06..86558485e4 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c +++ b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c @@ -18,7 +18,7 @@ * IMD makes no representations about the suitability * of this software for any purpose. * - * Modifications for PPC405GP by Dennis Ehlin + * Modifications for PPC405GP by Dennis Ehlin * */ @@ -31,101 +31,101 @@ /* * ISR vector table to dispatch external interrupts */ - + rtems_isr_entry ictrl_vector_table[PPC_IRQ_EXT_MAX]; -/* +/* * * some utilities to access the EXI* registers * */ -/* - * clear bits in EXISR that have a bit set in mask +/* + * clear bits in EXISR that have a bit set in mask */ #if defined(ppc405) -RTEMS_INLINE_ROUTINE void -clr_exisr(uint32_t mask) +RTEMS_INLINE_ROUTINE void +clr_exisr(uint32_t mask) { asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/ -} +} -/* - * get value of EXISR +/* + * get value of EXISR */ -RTEMS_INLINE_ROUTINE uint32_t -get_exisr(void) +RTEMS_INLINE_ROUTINE uint32_t +get_exisr(void) { uint32_t val; asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/ - return val; -} + return val; +} -/* - * get value of EXIER +/* + * get value of EXIER */ -RTEMS_INLINE_ROUTINE uint32_t -get_exier(void) +RTEMS_INLINE_ROUTINE uint32_t +get_exier(void) { uint32_t val; asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/ - return val; -} + return val; +} -/* - * set value of EXIER +/* + * set value of EXIER */ -RTEMS_INLINE_ROUTINE void -set_exier(uint32_t val) +RTEMS_INLINE_ROUTINE void +set_exier(uint32_t val) { asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/ -} +} #else /* not ppc405 */ -RTEMS_INLINE_ROUTINE void -clr_exisr(uint32_t mask) +RTEMS_INLINE_ROUTINE void +clr_exisr(uint32_t mask) { asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/ -} +} -/* - * get value of EXISR +/* + * get value of EXISR */ -RTEMS_INLINE_ROUTINE uint32_t -get_exisr(void) +RTEMS_INLINE_ROUTINE uint32_t +get_exisr(void) { uint32_t val; asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/ - return val; -} + return val; +} -/* - * get value of EXIER +/* + * get value of EXIER */ -RTEMS_INLINE_ROUTINE uint32_t -get_exier(void) +RTEMS_INLINE_ROUTINE uint32_t +get_exier(void) { uint32_t val; asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/ - return val; -} + return val; +} -/* - * set value of EXIER +/* + * set value of EXIER */ -RTEMS_INLINE_ROUTINE void -set_exier(uint32_t val) +RTEMS_INLINE_ROUTINE void +set_exier(uint32_t val) { asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/ -} +} #endif /* ppc405 */ -/* +/* * enable an external interrupt, make this interrupt consistent */ -RTEMS_INLINE_ROUTINE void +RTEMS_INLINE_ROUTINE void enable_ext_irq( uint32_t mask) { rtems_interrupt_level level; @@ -135,10 +135,10 @@ enable_ext_irq( uint32_t mask) rtems_interrupt_enable(level); } -/* +/* * disable an external interrupt, make this interrupt consistent */ -RTEMS_INLINE_ROUTINE void +RTEMS_INLINE_ROUTINE void disable_ext_irq( uint32_t mask) { rtems_interrupt_level level; @@ -150,19 +150,19 @@ disable_ext_irq( uint32_t mask) /* * - * this function is called, when a external interrupt is present and + * this function is called, when a external interrupt is present and * enabled but there is no handler installed. It will clear * the corresponding enable bits and call the spurious handler * present in the CPU Configuration Table, if any. * */ -void -ictrl_spurious_handler(uint32_t spurious_mask, +void +ictrl_spurious_handler(uint32_t spurious_mask, CPU_Interrupt_frame *cpu_frame) { int v; extern void (*bsp_spurious_handler)(uint32_t vector, CPU_Interrupt_frame *); - + for (v=0; v < PPC_IRQ_EXT_MAX; v++) { if (VEC_TO_EXMSK(v) & spurious_mask) { clr_exisr(VEC_TO_EXMSK(v)); @@ -182,7 +182,7 @@ ictrl_spurious_handler(uint32_t spurious_mask, /* * ISR Handler: this is called from the primary exception dispatcher */ - + void ictrl_isr(rtems_vector_number vector,CPU_Interrupt_frame *cpu_frame) { @@ -221,9 +221,9 @@ ictrl_isr(rtems_vector_number vector,CPU_Interrupt_frame *cpu_frame) /* * - * install a user vector for one of the external interrupt sources + * install a user vector for one of the external interrupt sources * - */ + */ rtems_status_code ictrl_set_vector(rtems_isr_entry new_handler, uint32_t vector, @@ -261,7 +261,7 @@ ictrl_set_vector(rtems_isr_entry new_handler, /* * Called via atexit() - * deactivate the interrupt controller + * deactivate the interrupt controller */ void @@ -270,14 +270,14 @@ ictrl_exit(void) /* mark them all unused */ disable_ext_irq(~0); clr_exisr(~0); - + } /* - * activate the interrupt controller + * activate the interrupt controller */ -rtems_status_code +rtems_status_code ictrl_init(void) { proc_ptr dummy; @@ -285,7 +285,7 @@ ictrl_init(void) /* mark them all unused */ disable_ext_irq(~0); clr_exisr(~0); - + /* install the external interrupt handler */ _CPU_ISR_install_vector(PPC_IRQ_EXTERNAL, ictrl_isr, diff --git a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.h b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.h index cda39dc5cf..102a4a0406 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.h +++ b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.h @@ -1,6 +1,6 @@ /* ictrl.h * - * This file contains definitions and declarations for the + * This file contains definitions and declarations for the * PowerPC 403 CPU built-in external interrupt controller * * @@ -35,9 +35,9 @@ extern "C" { #endif -/* +/* * definitions for second level IRQ handler support - * External Interrupts via EXTERNAL/EISR + * External Interrupts via EXTERNAL/EISR */ #define PPC_IRQ_EXT_BASE (PPC_IRQ_LAST+1) @@ -74,18 +74,18 @@ extern "C" { /* * - * install a user vector for one of the external interrupt sources + * install a user vector for one of the external interrupt sources * - */ + */ rtems_status_code ictrl_set_vector(rtems_isr_entry new_handler, uint32_t vector, rtems_isr_entry *old_handler ); /* - * activate the interrupt controller + * activate the interrupt controller */ -rtems_status_code +rtems_status_code ictrl_init(void); #ifdef __cplusplus diff --git a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c b/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c index 6aade98051..d26c8e2f3a 100644 --- a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c +++ b/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c @@ -3,7 +3,7 @@ * * Derived from /c/src/lib/libbsp/i386/shared/comm/tty_drv.c * - * Modifications to PPC405GP by Dennis Ehlin + * Modifications to PPC405GP by Dennis Ehlin * */ @@ -73,7 +73,7 @@ struct ttyasync { /*---------------------------------------------------------------------------+ | Alternate function registers +---------------------------------------------------------------------------*/ - #define AFR ISR + #define AFR ISR /*---------------------------------------------------------------------------+ | Line control Register. @@ -154,7 +154,7 @@ int tty0_round(double x) return (int)((int)((x-(int)x)*1000)>500 ? x+1 : x); } -void +void tty0BaudSet(uint32_t baudrate) { uint32_t tmp; @@ -214,13 +214,13 @@ tty0PollRead (int minor) /* Wait for character */ while ((tty0port->LSR & LSR_RSR)==0);; - return tty0port->RBR; + return tty0port->RBR; } -static int +static int tty0PollWrite(int minor,const char *buf,int len) -{ +{ while (len-- > 0) { while (!(tty0port->LSR & LSR_THE));; @@ -231,7 +231,7 @@ tty0PollWrite(int minor,const char *buf,int len) #endif /* ================ Termios support =================*/ - + static int tty0InterruptWrite (int minor, const char *buf, int len) { @@ -239,9 +239,9 @@ static int tty0InterruptWrite (int minor, const char *buf, int len) { return 0; } - + /* Write character */ - + tty0port->THR = (*buf &0xff); tty0port->IER |= IER_XMT; /* always enable tx interrupt */ @@ -259,7 +259,7 @@ static rtems_isr tty0serial_ISR(rtems_vector_number v) for(;;) { vect = tty0port->ISR & 0x0f; - if(vect & 1) + if(vect & 1) { /* no more interrupts */ if(off > 0) { @@ -273,32 +273,32 @@ static rtems_isr tty0serial_ISR(rtems_vector_number v) } vect = vect & 0xe; /*mask out all except interrupt pending*/ - + switch(vect) { case ISR_Tx : - /* - * TX holding empty: we have to disable these interrupts - * if there is nothing more to send. + /* + * TX holding empty: we have to disable these interrupts + * if there is nothing more to send. */ /* If nothing else to send disable interrupts */ ret = rtems_termios_dequeue_characters(tty0ttyp, 1); - + if ( ret == 0 ) { tty0port->IER &= ~IER_XMT; } - + break; case ISR_RxTO: case ISR_Rx : /* disable interrupts and notify termios */ - tty0port->IER &= ~IER_RCV; + tty0port->IER &= ~IER_RCV; /* read all bytes in fifo*/ - while (( off < sizeof(buf) ) && ( tty0port->LSR & LSR_RSR )) + while (( off < sizeof(buf) ) && ( tty0port->LSR & LSR_RSR )) { buf[off++] = tty0port->RBR; } @@ -318,17 +318,17 @@ static rtems_isr tty0serial_ISR(rtems_vector_number v) } -/* +/* * - * deinit TTY0 + * deinit TTY0 * */ void -tty0DeInit(void) +tty0DeInit(void) { /* - * disable interrupts for serial tty0port - * set it to state to work with polling boot monitor, if any... + * disable interrupts for serial tty0port + * set it to state to work with polling boot monitor, if any... */ /* set up baud rate to original state */ @@ -338,13 +338,13 @@ tty0DeInit(void) } -/* +/* * - * init SPI + * init SPI * */ -rtems_status_code -tty0Initialize(void) +rtems_status_code +tty0Initialize(void) { register unsigned tmp; rtems_isr_entry previous_isr; /* this is a dummy */ @@ -354,10 +354,10 @@ tty0Initialize(void) extern bool bsp_serial_external_clock; /* - * Initialise the serial tty0port + * Initialise the serial tty0port */ - /* + /* * Select clock source and set uart internal clock divisor */ @@ -379,22 +379,22 @@ tty0Initialize(void) /* set up baud rate */ tty0BaudSet(bsp_serial_rate); - + #ifdef TTY0_USE_INTERRUPT /* add rx/tx isr to vector table */ - if (TTY0_USE_UART==0) + if (TTY0_USE_UART==0) ictrl_set_vector(tty0serial_ISR,PPC_IRQ_EXT_UART0,&previous_isr); else ictrl_set_vector(tty0serial_ISR,PPC_IRQ_EXT_UART1,&previous_isr); - + /* Enable and clear FIFO */ tty0port->FCR = FCR_FE | FCR_CRF | FCR_CTF | FCR_RT14; /* Read status to clear them */ - _tmp = tty0port->LSR; + _tmp = tty0port->LSR; _tmp = tty0port->RBR; _tmp = tty0port->MSR; @@ -446,9 +446,9 @@ rtems_device_driver tty0_initialize( /* * Do device-specific initialization */ - + /*tty0Initialize (); Moved this to open instead */ - + /* * Register the device */ @@ -462,7 +462,7 @@ rtems_device_driver tty0_initialize( /* * Open entry point */ - + rtems_device_driver tty0_open( rtems_device_major_number major, rtems_device_minor_number minor, @@ -511,11 +511,11 @@ rtems_device_driver tty0_open( return sc; } - + /* * Close entry point */ - + rtems_device_driver tty0_close( rtems_device_major_number major, rtems_device_minor_number minor, @@ -524,11 +524,11 @@ rtems_device_driver tty0_close( { return rtems_termios_close (arg); } - + /* * read bytes from the serial port. We only have stdin. */ - + rtems_device_driver tty0_read( rtems_device_major_number major, rtems_device_minor_number minor, @@ -537,11 +537,11 @@ rtems_device_driver tty0_read( { return rtems_termios_read (arg); } - + /* * write bytes to the serial port. Stdout and stderr are the same. */ - + rtems_device_driver tty0_write( rtems_device_major_number major, rtems_device_minor_number minor, @@ -550,11 +550,11 @@ rtems_device_driver tty0_write( { return rtems_termios_write (arg); } - + /* * IO Control entry point */ - + rtems_device_driver tty0_control( rtems_device_major_number major, rtems_device_minor_number minor, diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h index a8a724aed0..6cdc9c6ee0 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h @@ -25,7 +25,7 @@ /* * FIXME: This is not used anywhere. */ -#if (PPC_D_CACHE != 0) +#if (PPC_D_CACHE != 0) #define _CPU_Data_Cache_Block_Invalidate( _address ) \ do { register void *__address = (_address); \ register uint32_t _zero = 0; \ diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h index fe5ad9ffbd..692a5643cc 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h @@ -40,7 +40,7 @@ /* * FIXME: This file is not used anywhere inside of RTEMS source-tree. - * Notify OAR if you actually use it, otherwise it might be removed in + * Notify OAR if you actually use it, otherwise it might be removed in * future versions of RTEMS */ @@ -65,7 +65,7 @@ extern "C" { * * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD */ - + /* * Define the debugging assistance models found in the PPC family. * diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h index 05ce800746..9609fd10d2 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @@ -51,10 +51,10 @@ extern "C" { /* Till S. 2008/07/10: - * + * * Using the macros/definitions which depend on a preprocessor * symbol defining the CPU flavor is discouraged. - * I recommend to not use definitions from this file and + * I recommend to not use definitions from this file and * in particular - not to add more bits and pieces. * * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h) @@ -79,7 +79,7 @@ extern "C" { * + PPC_HAS_EXCEPTION_PREFIX - 1 * + PPC_USE_MULTIPLE - 0 */ - + /* * Define the low power mode models * @@ -107,7 +107,7 @@ extern "C" { * predefines. */ -#if defined(ppc403) +#if defined(ppc403) /* * IBM 403 * @@ -115,7 +115,7 @@ extern "C" { * * Does not have user mode. */ - + #define PPC_CACHE_ALIGNMENT 16 #define PPC_HAS_RI 0 #define PPC_HAS_RFCI 1 @@ -146,8 +146,8 @@ extern "C" { #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD /* Based on comments by Sergei Organov <osv@Javad.RU> */ -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 0 +#define PPC_I_CACHE 0 +#define PPC_D_CACHE 0 #elif defined(mpc505) || defined(mpc509) /* @@ -168,7 +168,7 @@ extern "C" { /* * Submitted with original port -- book checked only. */ - + #define PPC_USE_MULTIPLE 1 #define PPC_I_CACHE 0 #define PPC_D_CACHE 32768 @@ -177,12 +177,12 @@ extern "C" { /* * Submitted with original port -- book checked only. */ - + #define PPC_I_CACHE 8192 #define PPC_D_CACHE 8192 #elif defined(ppc603e) - + /* * Submitted with original port. * @@ -198,15 +198,15 @@ extern "C" { /* * Submitted with original port -- book checked only. */ - + #define PPC_I_CACHE 16384 #define PPC_D_CACHE 16384 - + #elif defined(mpc860) -/* - * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 +/* + * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) - */ + */ #define PPC_I_CACHE 4096 #define PPC_D_CACHE 4096 #define PPC_CACHE_ALIGNMENT 16 @@ -219,9 +219,9 @@ extern "C" { #define PPC_MSR_3 0x00000000 #elif defined(mpc821) -/* +/* * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 - */ + */ #define PPC_I_CACHE 4096 #define PPC_D_CACHE 4096 #define PPC_CACHE_ALIGNMENT 16 @@ -265,9 +265,9 @@ extern "C" { #define PPC_CACHE_ALIGNMENT 32 #else - + #error "Unsupported CPU Model" - + #endif /* @@ -381,7 +381,7 @@ extern "C" { #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET #if defined(ppc403) || defined(ppc405) - + #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ @@ -408,10 +408,10 @@ extern "C" { #elif defined(ppc601) #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ -#define PPC_IRQ_LAST PPC_IRQ_TRACE +#define PPC_IRQ_LAST PPC_IRQ_TRACE #elif defined(ppc602) -#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) +#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) #elif defined(ppc603) || defined(ppc603e) #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ @@ -419,12 +419,12 @@ extern "C" { #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT #elif defined(mpc604) #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT #elif defined(mpc860) || defined(mpc821) #define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ @@ -507,14 +507,14 @@ extern "C" { #define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) #define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) #define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) -#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) +#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) #define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) #define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) -#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) +#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) #define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) #define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) #define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h index ba7000670c..95b8e05d2d 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h @@ -66,7 +66,7 @@ typedef enum * below. */ -typedef struct { +typedef struct { unsigned has_altivec : 1; unsigned has_fpu : 1; unsigned has_hw_ptbl_lkup : 1; diff --git a/c/src/lib/libcpu/powerpc/shared/include/io.h b/c/src/lib/libcpu/powerpc/shared/include/io.h index 1b68e069f6..3921e1855f 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/io.h +++ b/c/src/lib/libcpu/powerpc/shared/include/io.h @@ -57,7 +57,7 @@ static inline void eieio(void) } -/* Enforce in-order execution of data I/O. +/* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. */ #define iobarrier_rw() eieio() diff --git a/c/src/lib/libcpu/powerpc/shared/include/mmu.h b/c/src/lib/libcpu/powerpc/shared/include/mmu.h index c230bf0fac..db3f66aca3 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/shared/include/mmu.h @@ -35,7 +35,7 @@ typedef struct _PTE { unsigned long g:1; /* Guarded */ unsigned long :1; /* Unused */ unsigned long pp:2; /* Page protection */ -} PTE; +} PTE; /* Values for PP (assumes Ks=0, Kp=1) */ #define PP_RWXX 0 /* Supervisor read/write, User none */ @@ -71,7 +71,7 @@ typedef struct _BATU { /* Upper part of BAT (all except 601) */ unsigned long bl:11; /* Block size mask */ unsigned long vs:1; /* Supervisor valid */ unsigned long vp:1; /* User valid */ -} BATU; +} BATU; typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ unsigned long brpn:15; /* Real page index (physical address) */ @@ -139,7 +139,7 @@ typedef struct _pte { #define PT_SHIFT (12) /* Page Table */ #define PT_MASK 0x03FF #define PG_SHIFT (12) /* Page Entry */ - + /* MMU context */ @@ -156,13 +156,13 @@ typedef struct _MMU_context { #define HASH_TABLE_SIZE_1M 0x00100000 #define HASH_TABLE_SIZE_2M 0x00200000 #define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 #define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F /* invalidate a TLB entry */ static inline void _tlbie(unsigned long va) diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h index b71db63fa6..68e16b1c52 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @@ -14,7 +14,7 @@ * D-82178 Puchheim * Germany * rtems@embedded-brains.de - * + * * access function for Device Control Registers inspired by "ppc405common.h" * from Michael Hamel ADInstruments May 2008 * @@ -213,7 +213,7 @@ static inline void ppc_synchronize_instructions(void) /** * @brief Enables external exceptions. - * + * * You can use this function to enable the external exceptions and restore the * machine state with ppc_external_exceptions_disable() later. */ @@ -236,7 +236,7 @@ static inline uint32_t ppc_external_exceptions_enable(void) /** * @brief Restores machine state. - * + * * @see ppc_external_exceptions_enable() */ static inline void ppc_external_exceptions_disable(uint32_t msr) @@ -345,7 +345,7 @@ static inline void PPC_Set_timebase_register (uint64_t tbr) tbr_high = (uint32_t) (tbr >> 32); asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); - + } static inline uint32_t ppc_decrementer_register(void) @@ -606,11 +606,11 @@ void ppc_code_copy(void *dest, const void *src, size_t n); LWI \reg2, \mask and \reg1, \reg1, \reg2 cmplw \reg1, \reg2 -.endm - +.endm + .macro SETBITS reg1, reg2, mask LWI \reg2, \mask - or \reg1, \reg1, \reg2 + or \reg1, \reg1, \reg2 .endm .macro CLRBITS reg1, reg2, mask diff --git a/c/src/lib/libcpu/powerpc/shared/include/spr.h b/c/src/lib/libcpu/powerpc/shared/include/spr.h index 8a1a65c469..3501b52b74 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/spr.h +++ b/c/src/lib/libcpu/powerpc/shared/include/spr.h @@ -55,7 +55,7 @@ static inline unsigned long _read_MSR(void) unsigned long val; asm volatile("mfmsr %0" : "=r" (val)); return val; -} +} static inline void _write_MSR(unsigned long val) { @@ -68,7 +68,7 @@ static inline unsigned long _read_SR(void * va) unsigned long val; asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); return val; -} +} static inline void _write_SR(unsigned long val, void * va) { diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache.c b/c/src/lib/libcpu/powerpc/shared/src/cache.c index d998fb5016..d40e7d0f39 100644 --- a/c/src/lib/libcpu/powerpc/shared/src/cache.c +++ b/c/src/lib/libcpu/powerpc/shared/src/cache.c @@ -23,10 +23,10 @@ * They provide the basic implementation for the rtems_* cache * management routines. If a given function has no meaning for the CPU, * it does nothing by default. - * + * * FIXME: Some functions simply have not been implemented. */ - + #if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */ /* Helpful macros */ diff --git a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c b/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c index 414e8c6494..3ea5c35f9a 100644 --- a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c +++ b/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c @@ -171,7 +171,7 @@ sh4uart_set_baudrate(sh4uart *uart, speed_t baud) volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1; *smr1 &= ~SH7750_SCSMR_CKS; *smr1 |= n << SH7750_SCSMR_CKS_S; - } else { + } else { volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2; *smr2 &= ~SH7750_SCSMR_CKS; *smr2 |= n << SH7750_SCSMR_CKS_S; diff --git a/c/src/lib/libcpu/shared/include/cache.h b/c/src/lib/libcpu/shared/include/cache.h index 8a1f2c07ba..7bae1259ec 100644 --- a/c/src/lib/libcpu/shared/include/cache.h +++ b/c/src/lib/libcpu/shared/include/cache.h @@ -1,6 +1,6 @@ /* * libcpu Cache Manager Support - * + * * COPYRIGHT (c) 1989-1999. * On-Line Applications Research Corporation (OAR). * @@ -13,7 +13,7 @@ * They provide the processor specific actions to take for * implementing most of the RTEMS Cache Manager directives, * and should only ever be called by these directives. - * + * * The API for the RTEMS Cache Manager can be found in * c/src/exec/rtems/include/rtems/rtems/cache.h * diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 4c87caf49c..8e8ba25d2c 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -8,7 +8,7 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * - * + * * The functions in this file implement the API to the RTEMS Cache Manager and * are divided into data cache and instruction cache functions. Data cache * functions only have bodies if a data cache is supported. Instruction @@ -16,14 +16,14 @@ * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is * defined, where x E {DATA, INSTRUCTION}. These definitions are found in * the Cache Manager Wrapper header files, often - * + * * rtems/c/src/lib/libcpu/CPU/cache_.h - * + * * The functions below are implemented with CPU dependent inline routines * found in the cache.c files for each CPU. In the event that a CPU does * not support a specific function for a cache it has, the CPU dependent * routine does nothing (but does exist). - * + * * At this point, the Cache Manager makes no considerations, and provides no * support for BSP specific issues such as a secondary cache. In such a system, * the CPU dependent routines would have to be modified, or a BSP layer added @@ -60,7 +60,7 @@ rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) if( n_bytes == 0 ) /* Do nothing if number of bytes to flush is zero */ return; - + final_address = (void *)((size_t)d_addr + n_bytes - 1); d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); while( d_addr <= final_address ) { @@ -92,7 +92,7 @@ rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes if( n_bytes == 0 ) /* Do nothing if number of bytes to invalidate is zero */ return; - + final_address = (void *)((size_t)d_addr + n_bytes - 1); d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); while( final_address >= d_addr ) { @@ -219,7 +219,7 @@ rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n if( n_bytes == 0 ) /* Do nothing if number of bytes to invalidate is zero */ return; - + final_address = (void *)((size_t)i_addr + n_bytes - 1); i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); while( final_address > i_addr ) { diff --git a/c/src/lib/libcpu/sparc/reg_win/window.S b/c/src/lib/libcpu/sparc/reg_win/window.S index 4af985a826..e28774d74e 100644 --- a/c/src/lib/libcpu/sparc/reg_win/window.S +++ b/c/src/lib/libcpu/sparc/reg_win/window.S @@ -1,19 +1,19 @@ /* * window.s * - * This file contains the register window management routines for the + * This file contains the register window management routines for the * SPARC architecture. Trap handlers for the following capabilities * are included in this file: * * + Window Overflow * + Window Underflow * + Flushing All Windows - * + * * COPYRIGHT: * - * This file includes the window overflow and underflow handlers from - * the file srt0.s provided with the binary distribution of the SPARC - * Instruction Simulator (SIS) found at + * This file includes the window overflow and underflow handlers from + * the file srt0.s provided with the binary distribution of the SPARC + * Instruction Simulator (SIS) found at * ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. * * COPYRIGHT (c) 1995. European Space Agency. @@ -41,7 +41,7 @@ SYM(window_overflow_trap_handler): /* - * Calculate new WIM by "rotating" the valid bits in the WIM right + * Calculate new WIM by "rotating" the valid bits in the WIM right * by one position. The following shows how the bits move for a SPARC * cpu implementation where SPARC_NUMBER_OF_REGISTER_WINDOWS is 8. * @@ -49,7 +49,7 @@ SYM(window_overflow_trap_handler): * NEW WIM = 07654321 * * NOTE: New WIM must be stored in a global register since the - * "save" instruction just prior to the load of the wim + * "save" instruction just prior to the load of the wim * register will result in the local register set changing. */ @@ -58,7 +58,7 @@ SYM(window_overflow_trap_handler): srl %l3, 1, %g1 ! g1 = WIM >> 1 sll %l3, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4 ! l4 = WIM << (Number Windows - 1) - or %l4, %g1, %g1 ! g1 = (WIM >> 1) | + or %l4, %g1, %g1 ! g1 = (WIM >> 1) | ! (WIM << (Number Windows - 1)) save ! Get into window to be saved. @@ -92,7 +92,7 @@ SYM(window_overflow_trap_handler): SYM(window_underflow_trap_handler): /* - * Calculate new WIM by "rotating" the valid bits in the WIM left + * Calculate new WIM by "rotating" the valid bits in the WIM left * by one position. The following shows how the bits move for a SPARC * cpu implementation where SPARC_NUMBER_OF_REGISTER_WINDOWS is 8. * @@ -100,7 +100,7 @@ SYM(window_underflow_trap_handler): * NEW WIM = 07654321 * * NOTE: New WIM must be stored in a global register since the - * "save" instruction just prior to the load of the wim + * "save" instruction just prior to the load of the wim * register will result in the local register set changing. */ @@ -170,9 +170,9 @@ SYM(window_underflow_trap_handler): * l1 = pc * l2 = npc */ - + PUBLIC(window_flush_trap_handler) - + SYM(window_flush_trap_handler): /* * Save the global registers we will be using @@ -195,47 +195,47 @@ SYM(window_flush_trap_handler): sll %g4, %g5, %g4 ! g4 = WIM mask for CWP+1 invalid restore ! go back one register window - + save_frame_loop: sll %g4, 1, %g5 ! rotate the "wim" left 1 srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4 or %g4, %g5, %g4 ! g4 = wim if we do one restore - + /* * If a restore would not underflow, then continue. */ - + andcc %g4, %g2, %g0 ! Any windows to flush? bnz done_flushing ! No, then continue nop - + restore ! back one window - + /* * Now save the window just as if we overflowed to it. */ - + std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - + std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] - + ba save_frame_loop nop - + done_flushing: - + add %g3, 2, %g3 ! calculate desired WIM and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3 mov 1, %g4 sll %g4, %g3, %g4 ! g4 = new WIM mov %g4, %wim - + mov %g1, %psr ! restore PSR nop nop diff --git a/c/src/lib/libcpu/sparc/syscall/syscall.S b/c/src/lib/libcpu/sparc/syscall/syscall.S index 5beccfab63..aa69f45d48 100644 --- a/c/src/lib/libcpu/sparc/syscall/syscall.S +++ b/c/src/lib/libcpu/sparc/syscall/syscall.S @@ -7,7 +7,7 @@ * + SYS_exit (halt) * + SYS_irqdis (disable interrupts) * + SYS_irqset (set interrupt level) - * + * * COPYRIGHT: * * COPYRIGHT (c) 1995. European Space Agency. @@ -50,10 +50,10 @@ SYM(syscall): mov %l4, %psr ba,a 9f -1: - ta 0 ! halt +1: + ta 0 ! halt 9: ! leave - mov 0, %g1 ! clear %g1 + mov 0, %g1 ! clear %g1 jmpl %l2, %g0 rett %l2 + 4 |