diff options
| author | ragunath <ragunath3252@gmail.com> | 2015-05-03 15:25:55 +0530 |
|---|---|---|
| committer | Ben Gras <beng@rtems.org> | 2015-05-28 14:41:37 +0200 |
| commit | d55d7a067fedd9feb48fcd9755205da1558ab709 (patch) | |
| tree | ff97c48ceffcbe87e351eb156de36acf22b6a96a /c/src/lib/libcpu | |
| parent | dosfs: avoid buffer-overread. closes #2292. (diff) | |
| download | rtems-d55d7a067fedd9feb48fcd9755205da1558ab709.tar.bz2 | |
beagle bsp: RTC support for BBB
Diffstat (limited to 'c/src/lib/libcpu')
| -rw-r--r-- | c/src/lib/libcpu/arm/shared/include/am335x.h | 20 | ||||
| -rw-r--r-- | c/src/lib/libcpu/arm/shared/include/omap3.h | 6 |
2 files changed, 26 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/arm/shared/include/am335x.h b/c/src/lib/libcpu/arm/shared/include/am335x.h index 1f638bda76..37c5eeb666 100644 --- a/c/src/lib/libcpu/arm/shared/include/am335x.h +++ b/c/src/lib/libcpu/arm/shared/include/am335x.h @@ -280,3 +280,23 @@ /* Command posted status */ #define AM335X_WDT_WSPR 0x48 /* Activate/deactivate sequence */ + +/* RTC registers */ +#define AM335X_RTC_BASE 0x44E3E000 +#define AM335X_RTC_SECS 0x0 +#define AM335X_RTC_MINS 0x4 +#define AM335X_RTC_HOURS 0x8 +#define AM335X_RTC_DAYS 0xc +#define AM335X_RTC_MONTHS 0x10 +#define AM335X_RTC_YEARS 0x14 +#define AM335X_RTC_WEEKS 0x18 +#define AM335X_RTC_CTRL_REG 0x40 +#define AM335X_RTC_STATUS_REG 0x44 +#define AM335X_RTC_REV_REG 0x74 +#define AM335X_RTC_SYSCONFIG 0x78 +#define AM335X_RTC_KICK0 0x6c +#define AM335X_RTC_KICK1 0x70 +#define AM335X_RTC_OSC_CLOCK 0x54 + +#define AM335X_RTC_KICK0_KEY 0x83E70B13 +#define AM335X_RTC_KICK1_KEY 0x95A4F1E0 diff --git a/c/src/lib/libcpu/arm/shared/include/omap3.h b/c/src/lib/libcpu/arm/shared/include/omap3.h index 1316f6d4b0..f28e5e5406 100644 --- a/c/src/lib/libcpu/arm/shared/include/omap3.h +++ b/c/src/lib/libcpu/arm/shared/include/omap3.h @@ -288,6 +288,12 @@ #define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */ #define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */ +/*RTC CLOCK BASE & Registers*/ +#define CM_RTC_BASE 0x44E00800 +#define CM_RTC_RTC_CLKCTRL 0x0 +#define CM_RTC_CLKSTCTRL 0x4 + + #define OMAP3_CLKSEL_GPT1 (1 << 0) #define OMAP3_CLKSEL_GPT10 (1 << 6) #define OMAP3_CLKSEL_GPT11 (1 << 7) |