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authorSebastian Huber <sebastian.huber@embedded-brains.de>2014-12-19 12:12:08 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2015-01-09 14:03:33 +0100
commit5175ac6a87e40c22a4aaf4a70e9ced375a76fe98 (patch)
tree7129228788b41b614a58e4805a67f0e5a48e24cb /c/src/lib/libcpu
parentbsps/powerpc: Support e6500 indentification (diff)
downloadrtems-5175ac6a87e40c22a4aaf4a70e9ced375a76fe98.tar.bz2
bsps/powerpc: Support a cache alignment of 64
Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
Diffstat (limited to 'c/src/lib/libcpu')
-rw-r--r--c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
index 9b9f738c6c..2a895e1201 100644
--- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
+++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
@@ -62,6 +62,12 @@ extern "C" {
#include <rtems/score/powerpc.h>
/*
+ * Unfortunately it is very inefficient to use run-time detection for the cache
+ * line size, so give the BSP the opportunity to define it here.
+ */
+#include <bspopts.h>
+
+/*
* This file contains the information required to build
* RTEMS for a particular member of the PowerPC family. It does
* this by setting variables to indicate which implementation
@@ -271,7 +277,6 @@ extern "C" {
#define PPC_USE_MULTIPLE 1
#elif defined(__ppc_generic)
-#define PPC_CACHE_ALIGNMENT 32
#else
@@ -302,6 +307,8 @@ extern "C" {
#define PPC_CACHE_ALIGN_POWER 4
#elif (PPC_CACHE_ALIGNMENT == 32)
#define PPC_CACHE_ALIGN_POWER 5
+#elif (PPC_CACHE_ALIGNMENT == 64)
+#define PPC_CACHE_ALIGN_POWER 6
#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT)
#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER
#else