diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-02-18 15:16:37 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-02-18 15:16:37 +0000 |
commit | e029467dac9a09bc07babe9b3f1330e32b91f1d0 (patch) | |
tree | 897f13fd06dd29b2454a76ba03c7a1d308cba27e /c/src/lib/libcpu | |
parent | GLobal reentrancy structure is now dynamically initialized. (diff) | |
download | rtems-e029467dac9a09bc07babe9b3f1330e32b91f1d0.tar.bz2 |
Patch from Emmanuel Raguet <raguet@crf.canon.fr>:
You will find enclosed a patch which contains, for Intel PC386 target :
- an Ethernet driver for DEC21140 device based boards.
- a simple cache management with paging mechanism.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libcpu/i386/Makefile.in | 2 | ||||
-rw-r--r-- | c/src/lib/libcpu/i386/cpu.h | 147 | ||||
-rw-r--r-- | c/src/lib/libcpu/i386/registers.h | 25 |
3 files changed, 173 insertions, 1 deletions
diff --git a/c/src/lib/libcpu/i386/Makefile.in b/c/src/lib/libcpu/i386/Makefile.in index 3d339e036b..c380bed5c6 100644 --- a/c/src/lib/libcpu/i386/Makefile.in +++ b/c/src/lib/libcpu/i386/Makefile.in @@ -10,7 +10,7 @@ PROJECT_ROOT = @PROJECT_ROOT@ # C source names, if any, go here -- minus the .c -C_PIECES=cpu displayCpu +C_PIECES=cpu displayCpu page C_FILES=$(C_PIECES:%=%.c) C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) diff --git a/c/src/lib/libcpu/i386/cpu.h b/c/src/lib/libcpu/i386/cpu.h index be25929a0e..fa0c510a2b 100644 --- a/c/src/lib/libcpu/i386/cpu.h +++ b/c/src/lib/libcpu/i386/cpu.h @@ -134,6 +134,47 @@ static inline unsigned short i386_get_gs() } /* + * Added for pagination management + */ + +static inline unsigned int i386_get_cr0() +{ + register unsigned int segment = 0; + + asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline void i386_set_cr0(unsigned int segment) +{ + asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); +} + +static inline unsigned int i386_get_cr2() +{ + register unsigned int segment = 0; + + asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline unsigned int i386_get_cr3() +{ + register unsigned int segment = 0; + + asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); + + return segment; +} + +static inline void i386_set_cr3(unsigned int segment) +{ + asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); +} + +/* * IO Port Access Routines */ @@ -363,6 +404,112 @@ extern void i386_set_GDTR (segment_descriptors*, extern int i386_set_gdt_entry (unsigned short segment_selector, unsigned base, unsigned limit); +/* + * See page 11.18 Figure 11-12. + * + */ + +typedef struct { + unsigned int offset : 12; + unsigned int page : 10; + unsigned int directory : 10; +}la_bits; + +typedef union { + la_bits bits; + unsigned int address; +}linear_address; + + +/* + * See page 11.20 Figure 11-14. + * + */ + +typedef struct { + unsigned int present : 1; + unsigned int writable : 1; + unsigned int user : 1; + unsigned int write_through : 1; + unsigned int cache_disable : 1; + unsigned int accessed : 1; + unsigned int reserved1 : 1; + unsigned int page_size : 1; + unsigned int reserved2 : 1; + unsigned int available : 3; + unsigned int page_frame_address : 20; +}page_dir_bits; + +typedef union { + page_dir_bits bits; + unsigned int dir_entry; +}page_dir_entry; + +typedef struct { + unsigned int present : 1; + unsigned int writable : 1; + unsigned int user : 1; + unsigned int write_through : 1; + unsigned int cache_disable : 1; + unsigned int accessed : 1; + unsigned int dirty : 1; + unsigned int reserved2 : 2; + unsigned int available : 3; + unsigned int page_frame_address : 20; +}page_table_bits; + +typedef union { + page_table_bits bits; + unsigned int table_entry; +}page_table_entry; + +/* + * definitions related to page table entry + */ +#define PG_SIZE 0x1000 +#define MASK_OFFSET 0xFFF +#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry)) +#define FOUR_MB 0x400000 +#define MASK_FLAGS 0x1A + +#define PTE_PRESENT 0x01 +#define PTE_WRITABLE 0x02 +#define PTE_USER 0x04 +#define PTE_WRITE_THROUGH 0x08 +#define PTE_CACHE_DISABLE 0x10 + +typedef struct { + page_dir_entry pageDirEntry[MAX_ENTRY]; +}page_directory; + +typedef struct { + page_table_entry pageTableEntry[MAX_ENTRY]; +}page_table; + +static inline void flush_cache(){ + asm volatile ("wbinvd"); +} + + +/* C declaration for paging management */ + +extern int _CPU_is_cache_enabled(); +extern int _CPU_is_paging_enabled(); +extern int init_paging(); +extern void _CPU_enable_paging(); +extern void _CPU_disable_paging(); +extern void _CPU_disable_cache(); +extern void _CPU_enable_cache(); +extern int _CPU_map_phys_address + (void **mappedAddress, void *physAddress, + int size, int flag); +extern int _CPU_unmap_virt_address (void *mappedAddress, int size); +extern int _CPU_change_memory_mapping_attribute + (void **newAddress, void *mappedAddress, + unsigned int size, unsigned int flag); +extern int _CPU_display_memory_attribute(); + # endif /* ASM */ #endif + diff --git a/c/src/lib/libcpu/i386/registers.h b/c/src/lib/libcpu/i386/registers.h index 142516ca94..ab783fd329 100644 --- a/c/src/lib/libcpu/i386/registers.h +++ b/c/src/lib/libcpu/i386/registers.h @@ -58,6 +58,14 @@ #define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 #define CR0_PAGING 0x80000000 +/* + * definitions related to CR3 + */ + +#define CR3_PAGE_CACHE_DISABLE 0x10 +#define CR3_PAGE_WRITE_THROUGH 0x8 + + #ifndef ASM /* @@ -153,6 +161,23 @@ typedef union { unsigned int i; }cr0; +/* + * definition of cr3 registers has a bit field structure + */ +typedef struct { + + unsigned int : 3; + unsigned int page_write_transparent : 1; + unsigned int page_cache_disable : 1; + unsigned int : 7; + unsigned int page_directory_base :20; +}cr3_bits; + +typedef union { + cr3_bits cr3; + unsigned int i; +}cr3; + #endif #endif |