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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-08 17:38:12 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-10-09 10:11:58 -0500 |
| commit | 78a38fa2ae36b68b1adf461354721188f9a6e8a2 (patch) | |
| tree | e5651aa38de4e526fc8a5c0f263fc33234765404 /c/src/lib/libcpu/sparc64 | |
| parent | libchip/rtc/mc146818a*: Fix prototypes to use uintptr_t and fix set but unuse... (diff) | |
| download | rtems-78a38fa2ae36b68b1adf461354721188f9a6e8a2.tar.bz2 | |
Eliminate use of /*PAGE and clean up formatting
Diffstat (limited to 'c/src/lib/libcpu/sparc64')
| -rw-r--r-- | c/src/lib/libcpu/sparc64/shared/score/cpu.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/c/src/lib/libcpu/sparc64/shared/score/cpu.c b/c/src/lib/libcpu/sparc64/shared/score/cpu.c index 81478538d4..8fa5898360 100644 --- a/c/src/lib/libcpu/sparc64/shared/score/cpu.c +++ b/c/src/lib/libcpu/sparc64/shared/score/cpu.c @@ -1,6 +1,8 @@ /* * SPARC-v9 Dependent Source - * + */ + +/* * COPYRIGHT (c) 1989-2007. * On-Line Applications Research Corporation (OAR). * @@ -45,8 +47,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = { }; -/*PAGE - * +/* * _CPU_ISR_Get_level * * Input Parameters: NONE @@ -54,7 +55,6 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = { * Output Parameters: * returns the current interrupt level (PIL field of the PSR) */ - uint32_t _CPU_ISR_Get_level( void ) { uint32_t level; @@ -64,8 +64,7 @@ uint32_t _CPU_ISR_Get_level( void ) return level; } -/*PAGE - * +/* * _CPU_ISR_install_raw_handler * * This routine installs the specified handler as a "raw" non-executive @@ -203,8 +202,7 @@ void _CPU_ISR_install_raw_handler( } -/*PAGE - * +/* * _CPU_ISR_install_vector * * This kernel routine installs the RTEMS handler for the @@ -217,9 +215,7 @@ void _CPU_ISR_install_raw_handler( * * Output parameters: * *old_handler - former ISR for this vector number - * */ - void _CPU_ISR_install_vector( uint64_t vector, proc_ptr new_handler, |