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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-11-15 21:40:05 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-11-15 21:40:05 +0000 |
commit | ca4060826dead6c97983821a3222238d86136a0c (patch) | |
tree | ea20f412ee8d78b1033f191a0e047167499757a3 /c/src/lib/libcpu/sparc/cache/cache_.h | |
parent | 2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl> (diff) | |
download | rtems-ca4060826dead6c97983821a3222238d86136a0c.tar.bz2 |
2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl>
* Makefile.am, configure.in: Added support for instruction
cache enabling based on CPU model.
* cache/.cvsignore, cache/Makefile.am, cache/cache.c,
cache/cache_.h: New files.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libcpu/sparc/cache/cache_.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/sparc/cache/cache_.h b/c/src/lib/libcpu/sparc/cache/cache_.h new file mode 100644 index 0000000000..8d54d37e2d --- /dev/null +++ b/c/src/lib/libcpu/sparc/cache/cache_.h @@ -0,0 +1,24 @@ +/* + * SPARC Cache Manager Support + */ + +#ifndef __SPARC_CACHE_h +#define __SPARC_CACHE_h + +/* + * CACHE MANAGER: The following functions are CPU-specific. + * They provide the basic implementation for the rtems_* cache + * management routines. If a given function has no meaning for the CPU, + * it does nothing by default. + * + * FIXME: Some functions simply have not been implemented. + */ + +#if defined(HAS_INSTRUCTION_CACHE) +#define CPU_INSTRUCTION_CACHE_ALIGNMENT 0 +#endif + +#include <libcpu/cache.h> + +#endif +/* end of include file */ |