summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libcpu/sh/sh7750
diff options
context:
space:
mode:
authorSebastian Huber <sebastian.huber@embedded-brains.de>2017-12-08 13:37:19 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2017-12-08 13:44:17 +0100
commitf2969b5392e131528ac76b3d3ca877faf3535e34 (patch)
treec0cf77eec5653bea2478ba994f77309d5b7050f3 /c/src/lib/libcpu/sh/sh7750
parentbsp/gensh2: Move libcpu files to BSP (diff)
downloadrtems-f2969b5392e131528ac76b3d3ca877faf3535e34.tar.bz2
bsp/gensh4: Move libcpu files to BSP
Update #3254.
Diffstat (limited to 'c/src/lib/libcpu/sh/sh7750')
-rw-r--r--c/src/lib/libcpu/sh/sh7750/clock/ckinit.c244
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h47
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h73
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h62
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h51
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h1613
-rw-r--r--c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h174
-rw-r--r--c/src/lib/libcpu/sh/sh7750/sci/console.c460
-rw-r--r--c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c910
-rw-r--r--c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c105
-rw-r--r--c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c318
-rw-r--r--c/src/lib/libcpu/sh/sh7750/timer/timer.c269
12 files changed, 0 insertions, 4326 deletions
diff --git a/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c b/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
deleted file mode 100644
index 795203d2d9..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * This file contains the generic RTEMS clock driver the Hitachi SH 7750
- */
-
-/*
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Victor V. Vengerov <vvv@oktet.ru>
- *
- * COPYRIGHT (c) 2001
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems.h>
-
-#include <stdlib.h>
-
-#include <rtems/clockdrv.h>
-#include <rtems/score/sh_io.h>
-#include <rtems/score/sh.h>
-#include <rtems/score/ispsh7750.h>
-#include <rtems/score/iosh7750.h>
-
-extern uint32_t bsp_clicks_per_second;
-
-#ifndef CLOCKPRIO
-#define CLOCKPRIO 10
-#endif
-
-/* Clock timer prescaler division ratio */
-#define CLOCK_PRESCALER 4
-#define TCR0_TPSC SH7750_TCR_TPSC_DIV4
-
-/*
- * The interrupt vector number associated with the clock tick device
- * driver.
- */
-#define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0)
-
-/*
- * Clock_driver_ticks is a monotonically increasing counter of the
- * number of clock ticks since the driver was initialized.
- */
-volatile uint32_t Clock_driver_ticks;
-
-static rtems_isr Clock_isr( rtems_vector_number vector );
-
-/*
- * The previous ISR on this clock tick interrupt vector.
- */
-rtems_isr_entry Old_ticker;
-
-/*
- * Isr Handler
- */
-
-/*
- * Clock_isr
- *
- * Clock interrupt handling routine.
- */
-static rtems_isr Clock_isr(rtems_vector_number vector)
-{
- uint16_t tcr;
-
- /* reset the timer underflow flag */
- tcr = read16(SH7750_TCR0);
- write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0);
-
- /* Increment the clock interrupt counter */
- Clock_driver_ticks++ ;
-
- /* Invoke rtems clock service routine */
- rtems_clock_tick();
-}
-
-/*
- * Install_clock
- *
- * Install a clock tick handler and reprograms the chip. This
- * is used to initially establish the clock tick.
- *
- * SIDE EFFECTS:
- * Establish clock interrupt handler, configure Timer 0 hardware
- */
-static void Install_clock(rtems_isr_entry clock_isr)
-{
- int cpudiv = 1; /* CPU frequency divider */
- int tidiv = 1; /* Timer input frequency divider */
- uint32_t timer_divider; /* Calculated Timer Divider value */
- uint8_t temp8;
- uint16_t temp16;
-
- /*
- * Initialize the clock tick device driver variables
- */
-
- Clock_driver_ticks = 0;
-
- /* Get CPU frequency divider from clock unit */
- switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) {
- case SH7750_FRQCR_IFCDIV1:
- cpudiv = 1;
- break;
-
- case SH7750_FRQCR_IFCDIV2:
- cpudiv = 2;
- break;
-
- case SH7750_FRQCR_IFCDIV3:
- cpudiv = 3;
- break;
-
- case SH7750_FRQCR_IFCDIV4:
- cpudiv = 4;
- break;
-
- case SH7750_FRQCR_IFCDIV6:
- cpudiv = 6;
- break;
-
- case SH7750_FRQCR_IFCDIV8:
- cpudiv = 8;
- break;
-
- default:
- rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
- }
-
- /* Get peripheral module frequency divider from clock unit */
- switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) {
- case SH7750_FRQCR_PFCDIV2:
- tidiv = 2 * CLOCK_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV3:
- tidiv = 3 * CLOCK_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV4:
- tidiv = 4 * CLOCK_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV6:
- tidiv = 6 * CLOCK_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV8:
- tidiv = 8 * CLOCK_PRESCALER;
- break;
-
- default:
- rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
- }
- timer_divider =
- (bsp_clicks_per_second * cpudiv / (tidiv*1000000)) *
- rtems_configuration_get_microseconds_per_tick();
-
- /*
- * Hardware specific initialization
- */
-
- /* Stop the Timer 0 */
- temp8 = read8(SH7750_TSTR);
- temp8 &= ~SH7750_TSTR_STR0;
- write8(temp8, SH7750_TSTR);
-
- /* Establish interrupt handler */
- rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
-
- /* Reset counter */
- write32(timer_divider, SH7750_TCNT0);
-
- /* Load divider */
- write32(timer_divider, SH7750_TCOR0);
-
- write16(
- SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
- SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
- TCR0_TPSC, /* Timer prescaler ratio */
- SH7750_TCR0);
-
- /* Set clock interrupt priority */
- temp16 = read16(SH7750_IPRA);
- temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S);
- write16(temp16, SH7750_IPRA);
-
- /* Start the Timer 0 */
- temp8 = read8(SH7750_TSTR);
- temp8 |= SH7750_TSTR_STR0;
- write8(temp8, SH7750_TSTR);
-
- /*
- * Schedule the clock cleanup routine to execute if the application exits.
- */
- atexit( Clock_exit );
-}
-
-/*
- * Clock_exit
- *
- * Clean up before the application exits
- *
- * SIDE EFFECTS:
- * Stop Timer 0 counting, set timer 0 interrupt priority level to 0.
- */
-void
-Clock_exit(void)
-{
- uint8_t temp8 = 0;
- uint16_t temp16 = 0;
-
- /* turn off the timer interrupts */
- /* Stop the Timer 0 */
- temp8 = read8(SH7750_TSTR);
- temp8 &= ~SH7750_TSTR_STR0;
- write8(temp8, SH7750_TSTR);
-
- /* Lower timer interrupt priority to 0 */
- temp16 = read16(SH7750_IPRA);
- temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S);
- write16(temp16, SH7750_IPRA);
-
- /* old vector shall not be installed */
-}
-
-/*
- * Clock_initialize
- *
- * Device driver entry point for clock tick driver initialization.
- */
-rtems_device_driver Clock_initialize(
- rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *pargp
-)
-{
- Install_clock( Clock_isr );
-
- return RTEMS_SUCCESSFUL;
-}
diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h
deleted file mode 100644
index c5c532dbc2..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
- * contained no copyright notice.
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Modified to reflect on-chip registers for sh7045 processor, based on
- * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
- * contained no copyright notice:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- * August, 1999
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- */
-
-#ifndef __IOSH7750_H
-#define __IOSH7750_H
-
-#include <rtems/score/sh7750_regs.h>
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h
deleted file mode 100644
index 9ce2d87e0e..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* ipl.h
- *
- * IPL console driver
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Victor V. Vengerov <vvv@oktet.ru>
- *
- * Based on work:
- * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1989-1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __IPL_DRIVER_h
-#define __IPL_DRIVER_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define IPL_DRIVER_TABLE_ENTRY \
- { ipl_console_initialize, ipl_console_open, ipl_console_close, \
- ipl_console_read, ipl_console_write, ipl_console_control }
-
-
-#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
-
-rtems_device_driver ipl_console_initialize(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-rtems_device_driver ipl_console_open(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-rtems_device_driver ipl_console_close(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-rtems_device_driver ipl_console_read(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-rtems_device_driver ipl_console_write(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-rtems_device_driver ipl_console_control(
- rtems_device_major_number,
- rtems_device_minor_number,
- void *
-);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/* end of include file */
diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h
deleted file mode 100644
index 396644a241..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi
- * SH7750 processor.
- *
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Victor V. Vengerov <vvv@oktet.ru>
- *
- * Based on work of:
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Modified to reflect isp entries for sh7045 processor:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- *
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- */
-
-#ifndef __CPU_ISPS_H
-#define __CPU_ISPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-
-/* dummy ISP */
-extern void _dummy_isp( void );
-
-extern void __ISR_Handler( uint32_t vector );
-
-/* This variable contains VBR value used to pass control when debug, error
- * or virtual memory exceptions occured.
- */
-extern void *_VBR_Saved;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h
deleted file mode 100644
index 074dc6d7a1..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Bits on SH-4 registers.
- * See SH-4 Programming manual for more details.
- *
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Alexandra Kossovsky <sasha@oktet.ru>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __SH4_REGS_H__
-#define __SH4_REGS_H__
-
-/* SR -- Status Register */
-#define SH4_SR_MD 0x40000000 /* Priveleged mode */
-#define SH4_SR_RB 0x20000000 /* General register bank specifier */
-#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */
-#define SH4_SR_FD 0x00008000 /* FPU disable bit */
-#define SH4_SR_M 0x00000200 /* For signed division:
- divisor (module) is negative */
-#define SH4_SR_Q 0x00000100 /* For signed division:
- dividend (and quotient) is negative */
-#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */
-#define SH4_SR_IMASK_S 4
-#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction:
- if set, data in MACH/L register
- is restricted to 48/32 bits
- for MAC.W/L instructions */
-#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */
-#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */
-
-/* FPSCR -- FPU Starus/Control Register */
-#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */
-#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */
-#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point
- operations flag */
- /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
-#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */
-#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */
-#define SH4_FPSCR_CAUSE_S 12
-#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */
-#define SH4_FPSCR_ENABLE_s 7
-#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */
-#define SH4_FPSCR_FLAG_S 2
-#define SH4_FPSCR_RM 0x00000001 /* Rounding mode:
- 1/0 -- round to zero/nearest */
-#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h b/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h
deleted file mode 100644
index b65f9b6e51..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h
+++ /dev/null
@@ -1,1613 +0,0 @@
-/*
- * SH-7750 memory-mapped registers
- * This file based on information provided in the following document:
- * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S)
- * Hardware Manual"
- * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
- *
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Alexandra Kossovsky <sasha@oktet.ru>
- * Victor V. Vengerov <vvv@oktet.ru>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __SH7750_REGS_H__
-#define __SH7750_REGS_H__
-
-/*
- * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
- * in 0x1f000000 - 0x1fffffff (area 7 address)
- */
-#define SH7750_P4_BASE 0xff000000 /* Accessable only in
- priveleged mode */
-#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */
-
-#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
-#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
-
-/*
- * MMU Registers
- */
-
-/* Page Table Entry High register - PTEH */
-#define SH7750_PTEH_REGOFS 0x000000 /* offset */
-#define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS)
-#define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS)
-#define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
-#define SH7750_PTEH_VPN_S 10
-#define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
-#define SH7750_PTEH_ASID_S 0
-
-/* Page Table Entry Low register - PTEL */
-#define SH7750_PTEL_REGOFS 0x000004 /* offset */
-#define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS)
-#define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS)
-#define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
-#define SH7750_PTEL_PPN_S 10
-#define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
-#define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */
-#define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */
-#define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
-#define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
-#define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */
-#define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */
-#define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */
-#define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */
-#define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
-#define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/
-#define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/
-#define SH7750_PTEL_C 0x00000008 /* Cacheability
- (0 - page not cacheable) */
-#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
- performed to a page) */
-#define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are
- shared by processes) */
-#define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the
- cache write mode:
- 0 - Copy-back mode
- 1 - Write-through mode */
-
-/* Page Table Entry Assistance register - PTEA */
-#define SH7750_PTEA_REGOFS 0x000034 /* offset */
-#define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS)
-#define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS)
-#define SH7750_PTEA_TC 0x00000008 /* Timing Control bit
- 0 - use area 5 wait states
- 1 - use area 6 wait states */
-#define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */
-#define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */
-#define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */
-#define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */
-#define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */
-#define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space*/
-#define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space*/
-#define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */
-#define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */
-
-
-/* Translation table base register */
-#define SH7750_TTB_REGOFS 0x000008 /* offset */
-#define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS)
-#define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS)
-
-/* TLB exeption address register - TEA */
-#define SH7750_TEA_REGOFS 0x00000c /* offset */
-#define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS)
-#define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS)
-
-/* MMU control register - MMUCR */
-#define SH7750_MMUCR_REGOFS 0x000010 /* offset */
-#define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
-#define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
-#define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */
-#define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */
-#define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */
-#define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */
-#define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */
-#define SH7750_MMUCR_URC_S 10
-#define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */
-#define SH7750_MMUCR_URB_S 18
-#define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */
-#define SH7750_MMUCR_LRUI_S 26
-
-
-
-
-/*
- * Cache registers
- * IC -- instructions cache
- * OC -- operand cache
- */
-
-/* Cache Control Register - CCR */
-#define SH7750_CCR_REGOFS 0x00001c /* offset */
-#define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS)
-#define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS)
-
-#define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */
-#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
- set it to clear IC */
-#define SH7750_CCR_ICE 0x00000100 /* IC enable bit */
-#define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */
-#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
- if you set OCE = 0,
- you should set ORA = 0 */
-#define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */
-#define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
-#define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */
-#define SH7750_CCR_OCE 0x00000001 /* OC enable bit */
-
-/* Queue address control register 0 - QACR0 */
-#define SH7750_QACR0_REGOFS 0x000038 /* offset */
-#define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS)
-#define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS)
-
-/* Queue address control register 1 - QACR1 */
-#define SH7750_QACR1_REGOFS 0x00003c /* offset */
-#define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS)
-#define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS)
-
-
-/*
- * Exeption-related registers
- */
-
-/* Immediate data for TRAPA instuction - TRA */
-#define SH7750_TRA_REGOFS 0x000020 /* offset */
-#define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS)
-#define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS)
-
-#define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */
-#define SH7750_TRA_IMM_S 2
-
-/* Exeption event register - EXPEVT */
-#define SH7750_EXPEVT_REGOFS 0x000024
-#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
-#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
-
-#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */
-#define SH7750_EXPEVT_EX_S 0
-
-/* Interrupt event register */
-#define SH7750_INTEVT_REGOFS 0x000028
-#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
-#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
-#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
-#define SH7750_INTEVT_EX_S 0
-
-/*
- * Exception/interrupt codes
- */
-#define SH7750_EVT_TO_NUM(evt) ((evt) >> 5)
-
-/* Reset exception category */
-#define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */
-#define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */
-#define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */
-
-/* General exception category */
-#define SH7750_EVT_USER_BREAK 0x1E0 /* User break */
-#define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */
-#define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception /
- DTLB miss exception (read) */
-#define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation /
- DTLB protection violation (read)*/
-#define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction
- exception */
-#define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction
- exception */
-#define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception*/
-#define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */
-#define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */
-#define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */
-#define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */
-#define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation
- exception (write) */
-#define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */
-#define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */
-#define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */
-
-/* Interrupt exception category */
-#define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */
-#define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */
-#define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */
-#define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */
-#define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */
-#define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */
-#define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */
-#define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */
-#define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */
-#define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */
-#define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */
-#define SH7750_EVT_IRQA 0x340 /* External Interrupt A */
-#define SH7750_EVT_IRQB 0x360 /* External Interrupt B */
-#define SH7750_EVT_IRQC 0x380 /* External Interrupt C */
-#define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */
-#define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */
-
-/* Peripheral Module Interrupts - Timer Unit (TMU) */
-#define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */
-#define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */
-#define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */
-#define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2*/
-
-/* Peripheral Module Interrupts - Real-Time Clock (RTC) */
-#define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */
-#define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */
-#define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */
-
-/* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
-#define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */
-#define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */
-#define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */
-#define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */
-
-/* Peripheral Module Interrupts - Watchdog Timer (WDT) */
-#define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt
- (used when WDT operates in
- interval timer mode) */
-
-/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
-#define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
-#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
- interrupt */
-
-/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
-#define SH7750_EVT_HUDI 0x600 /* UDI interrupt */
-
-/* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
-#define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */
-
-/* Peripheral Module Interrupts - DMA Controller (DMAC) */
-#define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt*/
-#define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt*/
-#define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt*/
-#define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt*/
-#define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */
-
-/* Peripheral Module Interrupts - Serial Communication Interface with FIFO */
-/* (SCIF) */
-#define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */
-#define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or
- Receive Data ready interrupt */
-#define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */
-#define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */
-
-/*
- * Power Management
- */
-#define SH7750_STBCR_REGOFS 0xC00004 /* offset */
-#define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS)
-#define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS)
-
-#define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode:
- 0 - Transition to SLEEP mode on SLEEP
- 1 - Transition to STANDBY mode on SLEEP*/
-#define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in
- standby mode:
- 0 - normal state
- 1 - high-impendance state */
-
-#define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/
-#define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */
-#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
-#define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */
-#define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
-#define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */
-#define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2
-#define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */
-#define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1
-#define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */
-#define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0
-
-#define SH7750_STBCR_STBY 0x80
-
-
-#define SH7750_STBCR2_REGOFS 0xC00010 /* offset */
-#define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
-#define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
-
-#define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode:
- 0 - transition to sleep or standby mode
- as it is specified in STBY bit
- 1 - transition to deep sleep mode on
- execution of SLEEP instruction */
-#define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue
- in the cache controller */
-#define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6
-#define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User
- Break Controller (UBC) */
-#define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
-
-/*
- * Clock Pulse Generator (CPG)
- */
-#define SH7750_FRQCR_REGOFS 0xC00000 /* offset */
-#define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
-#define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
-
-#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
- 0 - CKIO pin goes to HiZ/pullup
- 1 - Clock is output from CKIO */
-#define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
-#define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */
-
-#define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */
-#define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */
-#define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */
-#define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */
-#define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */
-#define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */
-#define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */
-
-#define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */
-#define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */
-#define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */
-#define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */
-#define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */
-#define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */
-#define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */
-
-#define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency
- division ratio: */
-#define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */
-#define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */
-#define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */
-#define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */
-#define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */
-
-/*
- * Watchdog Timer (WDT)
- */
-
-/* Watchdog Timer Counter register - WTCNT */
-#define SH7750_WTCNT_REGOFS 0xC00008 /* offset */
-#define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
-#define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
-#define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written,
- you have to set the upper byte to
- 0x5A */
-
-/* Watchdog Timer Control/Status register - WTCSR */
-#define SH7750_WTCSR_REGOFS 0xC0000C /* offset */
-#define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
-#define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
-#define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written,
- you have to set the upper byte to
- 0xA5 */
-#define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */
-#define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */
-#define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */
-#define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */
-#define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */
-#define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */
-#define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */
-#define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */
-#define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */
-#define SH7750_WTCSR_CKS 0x07 /* Clock Select: */
-#define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */
-#define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */
-#define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */
-#define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */
-#define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */
-#define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */
-#define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */
-#define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */
-
-/*
- * Real-Time Clock (RTC)
- */
-/* 64-Hz Counter Register (byte, read-only) - R64CNT */
-#define SH7750_R64CNT_REGOFS 0xC80000 /* offset */
-#define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
-#define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
-
-/* Second Counter Register (byte, BCD-coded) - RSECCNT */
-#define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */
-#define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
-#define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
-
-/* Minute Counter Register (byte, BCD-coded) - RMINCNT */
-#define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */
-#define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
-#define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
-
-/* Hour Counter Register (byte, BCD-coded) - RHRCNT */
-#define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */
-#define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
-#define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
-
-/* Day-of-Week Counter Register (byte) - RWKCNT */
-#define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */
-#define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
-#define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
-
-#define SH7750_RWKCNT_SUN 0 /* Sunday */
-#define SH7750_RWKCNT_MON 1 /* Monday */
-#define SH7750_RWKCNT_TUE 2 /* Tuesday */
-#define SH7750_RWKCNT_WED 3 /* Wednesday */
-#define SH7750_RWKCNT_THU 4 /* Thursday */
-#define SH7750_RWKCNT_FRI 5 /* Friday */
-#define SH7750_RWKCNT_SAT 6 /* Saturday */
-
-/* Day Counter Register (byte, BCD-coded) - RDAYCNT */
-#define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */
-#define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
-#define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
-
-/* Month Counter Register (byte, BCD-coded) - RMONCNT */
-#define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */
-#define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
-#define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
-
-/* Year Counter Register (half, BCD-coded) - RYRCNT */
-#define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */
-#define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
-#define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
-
-/* Second Alarm Register (byte, BCD-coded) - RSECAR */
-#define SH7750_RSECAR_REGOFS 0xC80020 /* offset */
-#define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
-#define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
-#define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */
-
-/* Minute Alarm Register (byte, BCD-coded) - RMINAR */
-#define SH7750_RMINAR_REGOFS 0xC80024 /* offset */
-#define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
-#define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
-#define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */
-
-/* Hour Alarm Register (byte, BCD-coded) - RHRAR */
-#define SH7750_RHRAR_REGOFS 0xC80028 /* offset */
-#define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
-#define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
-#define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */
-
-/* Day-of-Week Alarm Register (byte) - RWKAR */
-#define SH7750_RWKAR_REGOFS 0xC8002C /* offset */
-#define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
-#define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
-#define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */
-
-#define SH7750_RWKAR_SUN 0 /* Sunday */
-#define SH7750_RWKAR_MON 1 /* Monday */
-#define SH7750_RWKAR_TUE 2 /* Tuesday */
-#define SH7750_RWKAR_WED 3 /* Wednesday */
-#define SH7750_RWKAR_THU 4 /* Thursday */
-#define SH7750_RWKAR_FRI 5 /* Friday */
-#define SH7750_RWKAR_SAT 6 /* Saturday */
-
-/* Day Alarm Register (byte, BCD-coded) - RDAYAR */
-#define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */
-#define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
-#define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
-#define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */
-
-/* Month Counter Register (byte, BCD-coded) - RMONAR */
-#define SH7750_RMONAR_REGOFS 0xC80034 /* offset */
-#define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
-#define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
-#define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */
-
-/* RTC Control Register 1 (byte) - RCR1 */
-#define SH7750_RCR1_REGOFS 0xC80038 /* offset */
-#define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS)
-#define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS)
-#define SH7750_RCR1_CF 0x80 /* Carry Flag */
-#define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */
-#define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */
-#define SH7750_RCR1_AF 0x01 /* Alarm Flag */
-
-/* RTC Control Register 2 (byte) - RCR2 */
-#define SH7750_RCR2_REGOFS 0xC8003C /* offset */
-#define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS)
-#define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS)
-#define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */
-#define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */
-#define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */
-#define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */
-#define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */
-#define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */
-#define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */
-#define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */
-#define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */
-#define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */
-#define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */
-#define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */
-#define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset*/
-#define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month,
- year counters are stopped
- 1 - sec, min, hr, day-of-week, month,
- year counters operate normally */
-
-
-/*
- * Timer Unit (TMU)
- */
-/* Timer Output Control Register (byte) - TOCR */
-#define SH7750_TOCR_REGOFS 0xD80000 /* offset */
-#define SH7750_TOCR SH7750_P4_REG32(SH7750_TOCR_REGOFS)
-#define SH7750_TOCR_A7 SH7750_A7_REG32(SH7750_TOCR_REGOFS)
-#define SH7750_TOCR_TCOE 0x01 /* Timer Clock Pin Control:
- 0 - TCLK is used as external clock
- input or input capture control
- 1 - TCLK is used as on-chip RTC
- output clock pin */
-
-/* Timer Start Register (byte) - TSTR */
-#define SH7750_TSTR_REGOFS 0xD80004 /* offset */
-#define SH7750_TSTR SH7750_P4_REG32(SH7750_TSTR_REGOFS)
-#define SH7750_TSTR_A7 SH7750_A7_REG32(SH7750_TSTR_REGOFS)
-#define SH7750_TSTR_STR2 0x04 /* TCNT2 performs count operations */
-#define SH7750_TSTR_STR1 0x02 /* TCNT1 performs count operations */
-#define SH7750_TSTR_STR0 0x01 /* TCNT0 performs count operations */
-#define SH7750_TSTR_STR(n) (1 << (n))
-
-/* Timer Constant Register - TCOR0, TCOR1, TCOR2 */
-#define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */
-#define SH7750_TCOR(n) SH7750_P4_REG32(SH7750_TCOR_REGOFS(n))
-#define SH7750_TCOR_A7(n) SH7750_A7_REG32(SH7750_TCOR_REGOFS(n))
-#define SH7750_TCOR0 SH7750_TCOR(0)
-#define SH7750_TCOR1 SH7750_TCOR(1)
-#define SH7750_TCOR2 SH7750_TCOR(2)
-#define SH7750_TCOR0_A7 SH7750_TCOR_A7(0)
-#define SH7750_TCOR1_A7 SH7750_TCOR_A7(1)
-#define SH7750_TCOR2_A7 SH7750_TCOR_A7(2)
-
-/* Timer Counter Register - TCNT0, TCNT1, TCNT2 */
-#define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */
-#define SH7750_TCNT(n) SH7750_P4_REG32(SH7750_TCNT_REGOFS(n))
-#define SH7750_TCNT_A7(n) SH7750_A7_REG32(SH7750_TCNT_REGOFS(n))
-#define SH7750_TCNT0 SH7750_TCNT(0)
-#define SH7750_TCNT1 SH7750_TCNT(1)
-#define SH7750_TCNT2 SH7750_TCNT(2)
-#define SH7750_TCNT0_A7 SH7750_TCNT_A7(0)
-#define SH7750_TCNT1_A7 SH7750_TCNT_A7(1)
-#define SH7750_TCNT2_A7 SH7750_TCNT_A7(2)
-
-/* Timer Control Register (half) - TCR0, TCR1, TCR2 */
-#define SH7750_TCR_REGOFS(n) (0xD80010 + ((n)*12)) /* offset */
-#define SH7750_TCR(n) SH7750_P4_REG32(SH7750_TCR_REGOFS(n))
-#define SH7750_TCR_A7(n) SH7750_A7_REG32(SH7750_TCR_REGOFS(n))
-#define SH7750_TCR0 SH7750_TCR(0)
-#define SH7750_TCR1 SH7750_TCR(1)
-#define SH7750_TCR2 SH7750_TCR(2)
-#define SH7750_TCR0_A7 SH7750_TCR_A7(0)
-#define SH7750_TCR1_A7 SH7750_TCR_A7(1)
-#define SH7750_TCR2_A7 SH7750_TCR_A7(2)
-
-#define SH7750_TCR2_ICPF 0x200 /* Input Capture Interrupt Flag
- (1 - input capture has occured) */
-#define SH7750_TCR_UNF 0x100 /* Underflow flag */
-#define SH7750_TCR2_ICPE 0x0C0 /* Input Capture Control: */
-#define SH7750_TCR2_ICPE_DIS 0x000 /* Input Capture function is not used*/
-#define SH7750_TCR2_ICPE_NOINT 0x080 /* Input Capture function is used, but
- input capture interrupt is not
- enabled */
-#define SH7750_TCR2_ICPE_INT 0x0C0 /* Input Capture function is used,
- input capture interrupt enabled */
-#define SH7750_TCR_UNIE 0x020 /* Underflow Interrupt Control
- (1 - underflow interrupt enabled) */
-#define SH7750_TCR_CKEG 0x018 /* Clock Edge selection: */
-#define SH7750_TCR_CKEG_RAISE 0x000 /* Count/capture on rising edge */
-#define SH7750_TCR_CKEG_FALL 0x008 /* Count/capture on falling edge */
-#define SH7750_TCR_CKEG_BOTH 0x018 /* Count/capture on both rising and
- falling edges */
-#define SH7750_TCR_TPSC 0x007 /* Timer prescaler */
-#define SH7750_TCR_TPSC_DIV4 0x000 /* Counts on peripheral clock/4 */
-#define SH7750_TCR_TPSC_DIV16 0x001 /* Counts on peripheral clock/16 */
-#define SH7750_TCR_TPSC_DIV64 0x002 /* Counts on peripheral clock/64 */
-#define SH7750_TCR_TPSC_DIV256 0x003 /* Counts on peripheral clock/256 */
-#define SH7750_TCR_TPSC_DIV1024 0x004 /* Counts on peripheral clock/1024 */
-#define SH7750_TCR_TPSC_RTC 0x006 /* Counts on on-chip RTC output clk*/
-#define SH7750_TCR_TPSC_EXT 0x007 /* Counts on external clock */
-
-/* Input Capture Register (read-only) - TCPR2 */
-#define SH7750_TCPR2_REGOFS 0xD8002C /* offset */
-#define SH7750_TCPR2 SH7750_P4_REG32(SH7750_TCPR2_REGOFS)
-#define SH7750_TCPR2_A7 SH7750_A7_REG32(SH7750_TCPR2_REGOFS)
-
-/*
- * Bus State Controller - BSC
- */
-/* Bus Control Register 1 - BCR1 */
-#define SH7750_BCR1_REGOFS 0x800000 /* offset */
-#define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS)
-#define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS)
-#define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */
-#define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */
-#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/
-#define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control:
- 0 - pull-up resistor is on for
- control input pins
- 1 - pull-up resistor is off */
-#define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control:
- 0 - pull-up resistor is on for
- control output pins
- 1 - pull-up resistor is off */
-#define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode:
- 0 - Area 1 SRAM is set to
- normal mode
- 1 - Area 1 SRAM is set to byte
- control mode */
-#define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode:
- 0 - Area 4 SRAM is set to
- normal mode
- 1 - Area 4 SRAM is set to byte
- control mode */
-#define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable:
- 0 - External requests are not
- accepted
- 1 - External requests are
- accepted */
-#define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit:
- 0 - Master Mode
- 1 - Partial-sharing Mode */
-#define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface:
- 0 - SRAM/burst ROM interface
- 1 - MPX interface */
-#define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies
- the state of A[25:0], BS\, CSn\,
- RD/WR\, CE2A\, CE2B\ in standby
- mode and when bus is released:
- 0 - signals go to High-Z mode
- 1 - signals driven */
-#define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies
- the state of the RAS\, RAS2\, WEn\,
- CASn\, DQMn, RD\, CASS\, FRAME\,
- RD2\ signals in standby mode and
- when bus is released:
- 0 - signals go to High-Z mode
- 1 - signals driven */
-#define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */
-#define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */
-#define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM
- interface, 4 cosequtive access*/
-#define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM
- interface, 8 cosequtive access*/
-#define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM
- interface, 16 cosequtive access*/
-#define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM
- interface, 32 cosequtive access*/
-
-#define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */
-#define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */
-#define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM
- interface, 4 cosequtive access*/
-#define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM
- interface, 8 cosequtive access*/
-#define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM
- interface, 16 cosequtive access*/
-#define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM
- interface, 32 cosequtive access*/
-
-#define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */
-#define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */
-#define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM
- interface, 4 cosequtive access*/
-#define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM
- interface, 8 cosequtive access*/
-#define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM
- interface, 16 cosequtive access*/
-#define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM
- interface, 32 cosequtive access*/
-
-#define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */
-#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX
- interface. */
-#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 -
- synchronous DRAM */
-#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous
- DRAM interface */
-#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 -
- DRAM interface */
-#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM
- interface */
-
-#define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type:
- 0 - SRAM interface
- 1 - PCMCIA interface */
-
-/* Bus Control Register 2 (half) - BCR2 */
-#define SH7750_BCR2_REGOFS 0x800004 /* offset */
-#define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS)
-#define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS)
-
-#define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */
-#define SH7750_BCR2_A0SZ_S 14
-#define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */
-#define SH7750_BCR2_A6SZ_S 12
-#define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */
-#define SH7750_BCR2_A5SZ_S 10
-#define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */
-#define SH7750_BCR2_A4SZ_S 8
-#define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */
-#define SH7750_BCR2_A3SZ_S 6
-#define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */
-#define SH7750_BCR2_A2SZ_S 4
-#define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */
-#define SH7750_BCR2_A1SZ_S 2
-#define SH7750_BCR2_SZ_64 0 /* 64 bits */
-#define SH7750_BCR2_SZ_8 1 /* 8 bits */
-#define SH7750_BCR2_SZ_16 2 /* 16 bits */
-#define SH7750_BCR2_SZ_32 3 /* 32 bits */
-#define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable :
- 0 - D51-D32 are not used as a port
- 1 - D51-D32 are used as a port */
-
-/* Wait Control Register 1 - WCR1 */
-#define SH7750_WCR1_REGOFS 0x800008 /* offset */
-#define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS)
-#define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS)
-#define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle
- specification */
-#define SH7750_WCR1_DMAIW_S 28
-#define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A6IW_S 24
-#define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A5IW_S 20
-#define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A4IW_S 16
-#define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A3IW_S 12
-#define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A2IW_S 8
-#define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A1IW_S 4
-#define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
-#define SH7750_WCR1_A0IW_S 0
-
-/* Wait Control Register 2 - WCR2 */
-#define SH7750_WCR2_REGOFS 0x80000C /* offset */
-#define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS)
-#define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS)
-
-#define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */
-#define SH7750_WCR2_A6W_S 29
-#define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */
-#define SH7750_WCR2_A6B_S 26
-#define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */
-#define SH7750_WCR2_A5W_S 23
-#define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */
-#define SH7750_WCR2_A5B_S 20
-#define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */
-#define SH7750_WCR2_A4W_S 17
-#define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */
-#define SH7750_WCR2_A3W_S 13
-#define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */
-#define SH7750_WCR2_A2W_S 9
-#define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */
-#define SH7750_WCR2_A1W_S 6
-#define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */
-#define SH7750_WCR2_A0W_S 3
-#define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */
-#define SH7750_WCR2_A0B_S 0
-
-#define SH7750_WCR2_WS0 0 /* 0 wait states inserted */
-#define SH7750_WCR2_WS1 1 /* 1 wait states inserted */
-#define SH7750_WCR2_WS2 2 /* 2 wait states inserted */
-#define SH7750_WCR2_WS3 3 /* 3 wait states inserted */
-#define SH7750_WCR2_WS6 4 /* 6 wait states inserted */
-#define SH7750_WCR2_WS9 5 /* 9 wait states inserted */
-#define SH7750_WCR2_WS12 6 /* 12 wait states inserted */
-#define SH7750_WCR2_WS15 7 /* 15 wait states inserted */
-
-#define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */
-#define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */
-
-/* DRAM CAS\ Assertion Delay (area 3,2) */
-#define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */
-#define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */
-#define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */
-
-/* SDRAM CAS\ Latency Cycles */
-#define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */
-#define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */
-#define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */
-#define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */
-#define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */
-
-/* Wait Control Register 3 - WCR3 */
-#define SH7750_WCR3_REGOFS 0x800010 /* offset */
-#define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS)
-#define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS)
-
-#define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */
-#define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */
-#define SH7750_WCR3_A6H_S 24
-#define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */
-#define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */
-#define SH7750_WCR3_A5H_S 20
-#define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */
-#define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */
-#define SH7750_WCR3_A4H_S 16
-#define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */
-#define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */
-#define SH7750_WCR3_A3H_S 12
-#define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */
-#define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */
-#define SH7750_WCR3_A2H_S 8
-#define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */
-#define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */
-#define SH7750_WCR3_A1H_S 4
-#define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */
-#define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */
-#define SH7750_WCR3_A0H_S 0
-
-#define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */
-#define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */
-#define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */
-#define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */
-
-#define SH7750_MCR_REGOFS 0x800014 /* offset */
-#define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS)
-#define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS)
-
-#define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */
-#define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */
-#define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */
-#define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of
- Refresh: */
-#define SH7750_MCR_TRC_0 0x00000000 /* 0 */
-#define SH7750_MCR_TRC_3 0x08000000 /* 3 */
-#define SH7750_MCR_TRC_6 0x10000000 /* 6 */
-#define SH7750_MCR_TRC_9 0x18000000 /* 9 */
-#define SH7750_MCR_TRC_12 0x20000000 /* 12 */
-#define SH7750_MCR_TRC_15 0x28000000 /* 15 */
-#define SH7750_MCR_TRC_18 0x30000000 /* 18 */
-#define SH7750_MCR_TRC_21 0x38000000 /* 21 */
-
-#define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */
-#define SH7750_MCR_TCAS_1 0x00000000 /* 1 */
-#define SH7750_MCR_TCAS_2 0x00800000 /* 2 */
-
-#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
- SDRAM: minimum number of cycles
- until the next bank active cmd
- is output after precharging */
-#define SH7750_MCR_TPC_S 19
-#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
-#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
-#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
-#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
-#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
-#define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
-#define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */
-#define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */
-
-#define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time
- SDRAM: bank active-read/write cmd
- delay time */
-#define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */
-#define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */
-#define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */
-#define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */
-#define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */
-#define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */
-#define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */
-
-#define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */
-#define SH7750_MCR_TRWL_1 0x00000000 /* 1 */
-#define SH7750_MCR_TRWL_2 0x00002000 /* 2 */
-#define SH7750_MCR_TRWL_3 0x00004000 /* 3 */
-#define SH7750_MCR_TRWL_4 0x00006000 /* 4 */
-#define SH7750_MCR_TRWL_5 0x00008000 /* 5 */
-
-#define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS
- asserting period
- SDRAM: Command interval after
- synchronous DRAM refresh */
-#define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */
-#define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */
-#define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */
-#define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */
-#define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */
-#define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */
-#define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */
-#define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */
-
-#define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */
-#define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */
-
-#define SH7750_MCR_BE 0x00000200 /* Burst Enable */
-#define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */
-#define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */
-#define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */
-#define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */
-
-#define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */
-#define SH7750_MCR_AMX_S 3
-#define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */
-#define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */
-#define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */
-#define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */
-#define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */
-/* See SH7750 Hardware Manual for SDRAM address multiplexor selection */
-
-#define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */
-#define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */
-#define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */
-#define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */
-#define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */
-
-/* SDRAM Mode Set address */
-#define SH7750_SDRAM_MODE_A2_BASE 0xFF900000
-#define SH7750_SDRAM_MODE_A3_BASE 0xFF940000
-#define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
-#define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
-#define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
-#define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
-
-
-/* PCMCIA Control Register (half) - PCR */
-#define SH7750_PCR_REGOFS 0x800018 /* offset */
-#define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS)
-#define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS)
-
-#define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait
- states to be added to the number of
- waits specified by WCR2 in a low-speed
- PCMCIA wait cycle */
-#define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */
-#define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */
-#define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */
-#define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */
-
-#define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait
- states to be added to the number of
- waits specified by WCR2 in a low-speed
- PCMCIA wait cycle */
-#define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */
-#define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */
-#define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */
-#define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */
-
-#define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay,
- delay time from address output to
- OE\/WE\ assertion on the connected
- PCMCIA interface */
-#define SH7750_PCR_A5TED_S 9
-#define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/
-#define SH7750_PCR_A6TED_S 6
-
-#define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */
-#define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */
-#define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */
-#define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */
-#define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */
-#define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */
-#define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */
-#define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */
-
-#define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay,
- address hold delay time from OE\/WE\
- negation in a write on the connected
- PCMCIA interface */
-#define SH7750_PCR_A5TEH_S 3
-
-#define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay*/
-#define SH7750_PCR_A6TEH_S 0
-
-#define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */
-#define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */
-#define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */
-#define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */
-#define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */
-#define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */
-#define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */
-#define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */
-
-/* Refresh Timer Control/Status Register (half) - RTSCR */
-#define SH7750_RTCSR_REGOFS 0x80001C /* offset */
-#define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
-#define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
-
-#define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */
-#define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a
- match between the refresh timer
- counter and refresh time constant) */
-#define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */
-#define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */
-#define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */
-#define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */
-#define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */
-#define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */
-#define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */
-#define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */
-#define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */
-#define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */
-
-#define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */
-#define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt
- Enable */
-#define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */
-#define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */
-#define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */
-
-/* Refresh Timer Counter (half) - RTCNT */
-#define SH7750_RTCNT_REGOFS 0x800020 /* offset */
-#define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
-#define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
-
-#define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */
-
-/* Refresh Time Constant Register (half) - RTCOR */
-#define SH7750_RTCOR_REGOFS 0x800024 /* offset */
-#define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
-#define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
-
-#define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */
-
-/* Refresh Count Register (half) - RFCR */
-#define SH7750_RFCR_REGOFS 0x800028 /* offset */
-#define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS)
-#define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS)
-
-#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
-
-/*
- * Direct Memory Access Controller (DMAC)
- */
-
-/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
-#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */
-#define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
-#define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
-#define SH7750_SAR0 SH7750_SAR(0)
-#define SH7750_SAR1 SH7750_SAR(1)
-#define SH7750_SAR2 SH7750_SAR(2)
-#define SH7750_SAR3 SH7750_SAR(3)
-#define SH7750_SAR0_A7 SH7750_SAR_A7(0)
-#define SH7750_SAR1_A7 SH7750_SAR_A7(1)
-#define SH7750_SAR2_A7 SH7750_SAR_A7(2)
-#define SH7750_SAR3_A7 SH7750_SAR_A7(3)
-
-/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
-#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */
-#define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
-#define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
-#define SH7750_DAR0 SH7750_DAR(0)
-#define SH7750_DAR1 SH7750_DAR(1)
-#define SH7750_DAR2 SH7750_DAR(2)
-#define SH7750_DAR3 SH7750_DAR(3)
-#define SH7750_DAR0_A7 SH7750_DAR_A7(0)
-#define SH7750_DAR1_A7 SH7750_DAR_A7(1)
-#define SH7750_DAR2_A7 SH7750_DAR_A7(2)
-#define SH7750_DAR3_A7 SH7750_DAR_A7(3)
-
-/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
-#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */
-#define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
-#define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
-#define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
-#define SH7750_DMATCR1_P4 SH7750_DMATCR(1)
-#define SH7750_DMATCR2_P4 SH7750_DMATCR(2)
-#define SH7750_DMATCR3_P4 SH7750_DMATCR(3)
-#define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0)
-#define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1)
-#define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2)
-#define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3)
-
-/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
-#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */
-#define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
-#define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
-#define SH7750_CHCR0 SH7750_CHCR(0)
-#define SH7750_CHCR1 SH7750_CHCR(1)
-#define SH7750_CHCR2 SH7750_CHCR(2)
-#define SH7750_CHCR3 SH7750_CHCR(3)
-#define SH7750_CHCR0_A7 SH7750_CHCR_A7(0)
-#define SH7750_CHCR1_A7 SH7750_CHCR_A7(1)
-#define SH7750_CHCR2_A7 SH7750_CHCR_A7(2)
-#define SH7750_CHCR3_A7 SH7750_CHCR_A7(3)
-
-#define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */
-#define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
-#define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */
-#define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */
-#define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */
-#define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */
-#define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */
-#define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */
-#define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */
-
-#define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select,
- specifies CS5 or CS6 space wait
- control for PCMCIA access */
-
-#define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */
-#define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
-#define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */
-#define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */
-#define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */
-#define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */
-#define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */
-#define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */
-#define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
-
-#define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control
- Select, specifies CS5 or CS6
- space wait control for PCMCIA
- access */
-
-#define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */
-#define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */
-#define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */
-
-#define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */
-#define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */
-#define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */
-
-#define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */
-#define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */
-#define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle*/
-
-#define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */
-#define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */
-#define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */
-
-#define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */
-#define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */
-#define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */
-#define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */
-
-#define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */
-#define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */
-#define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */
-#define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */
-
-#define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */
-#define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address
- Mode (External Addr Space->
- External Addr Space) */
-#define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single
- Address Mode (External Addr
- Space -> External Device) */
-#define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single
- Address Mode, (External
- Device -> External Addr
- Space)*/
-#define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr
- Space -> External Addr Space)*/
-
-#define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr
- Space -> On-chip Peripheral
- Module) */
-#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
- Peripheral Module ->
- External Addr Space */
-#define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr
- transfer request (external
- address space -> SCTDR1) */
-#define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr
- transfer request (SCRDR1 ->
- External Addr Space) */
-#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr
- transfer request (external
- address space -> SCFTDR1) */
-#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr
- transfer request (SCFRDR2 ->
- External Addr Space) */
-#define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture
- interrupt), (external address
- space -> external address
- space) */
-#define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture
- interrupt), (external address
- space -> on-chip peripheral
- module) */
-#define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture
- interrupt), (on-chip
- peripheral module -> external
- address space) */
-
-#define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */
-#define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */
-#define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */
-
-#define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */
-#define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */
-#define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */
-#define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */
-#define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */
-#define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */
-
-#define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */
-#define SH7750_CHCR_TE 0x00000002 /* Transfer End */
-#define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */
-
-/* DMA Operation Register - DMAOR */
-#define SH7750_DMAOR_REGOFS 0xA00040 /* offset */
-#define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
-#define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
-
-#define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */
-
-#define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */
-#define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */
-#define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */
-#define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */
-#define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */
-
-#define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */
-#define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */
-#define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */
-#define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */
-
-/*
- * Serial Communication Interface - SCI
- * Serial Communication Interface with FIFO - SCIF
- */
-/* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */
-#define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */
-#define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n))
-#define SH7750_SCRDR1 SH7750_SCRDR(1)
-#define SH7750_SCRDR2 SH7750_SCRDR(2)
-#define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n))
-#define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1)
-#define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2)
-
-/* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */
-#define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */
-#define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n))
-#define SH7750_SCTDR1 SH7750_SCTDR(1)
-#define SH7750_SCTDR2 SH7750_SCTDR(2)
-#define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n))
-#define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1)
-#define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2)
-
-/* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */
-#define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */
-#define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n))
-#define SH7750_SCSMR1 SH7750_SCSMR(1)
-#define SH7750_SCSMR2 SH7750_SCSMR(2)
-#define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n))
-#define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1)
-#define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2)
-
-#define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */
-#define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */
-#define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */
-#define SH7750_SCSMR_CHR 0x40 /* Character Length: */
-#define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */
-#define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */
-#define SH7750_SCSMR_PE 0x20 /* Parity Enable */
-#define SH7750_SCSMR_PM 0x10 /* Parity Mode: */
-#define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */
-#define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */
-#define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */
-#define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */
-#define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */
-#define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */
-#define SH7750_SCSMR_CKS 0x03 /* Clock Select */
-#define SH7750_SCSMR_CKS_S 0
-#define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */
-#define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */
-#define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */
-#define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */
-
-/* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */
-#define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */
-#define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n))
-#define SH7750_SCSCR1 SH7750_SCSCR(1)
-#define SH7750_SCSCR2 SH7750_SCSCR(2)
-#define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n))
-#define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1)
-#define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2)
-
-#define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */
-#define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */
-#define SH7750_SCSCR_TE 0x20 /* Transmit Enable */
-#define SH7750_SCSCR_RE 0x10 /* Receive Enable */
-#define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */
-#define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */
-#define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */
-#define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */
-#define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */
-#define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK*/
-#define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output
- in asynchronous mode */
-
-/* SCI Serial Status Register - SCSSR1(byte), SCSSR2(half) */
-#define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */
-#define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n))
-#define SH7750_SCSSR1 SH7750_SCSSR(1)
-#define SH7750_SCSSR2 SH7750_SCSSR(2)
-#define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n))
-#define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1)
-#define SH7750_SCSSR2_A7 SH7750_SCSSR_A7(2)
-
-#define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */
-#define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */
-#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */
-#define SH7750_SCSSR1_FER 0x10 /* Framing Error */
-#define SH7750_SCSSR1_PER 0x08 /* Parity Error */
-#define SH7750_SCSSR1_TEND 0x04 /* Transmit End */
-#define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */
-#define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */
-
-#define SH7750_SCSSR2_PERN 0xF000 /* Number of Parity Errors */
-#define SH7750_SCSSR2_PERN_S 12
-#define SH7750_SCSSR2_FERN 0x0F00 /* Number of Framing Errors */
-#define SH7750_SCSSR2_FERN_S 8
-#define SH7750_SCSSR2_ER 0x0080 /* Receive Error */
-#define SH7750_SCSSR2_TEND 0x0040 /* Transmit End */
-#define SH7750_SCSSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */
-#define SH7750_SCSSR2_BRK 0x0010 /* Break Detect */
-#define SH7750_SCSSR2_FER 0x0008 /* Framing Error */
-#define SH7750_SCSSR2_PER 0x0004 /* Parity Error */
-#define SH7750_SCSSR2_RDF 0x0002 /* Receive FIFO Data Full */
-#define SH7750_SCSSR2_DR 0x0001 /* Receive Data Ready */
-
-/* SCI Serial Port Register - SCSPTR1(byte) */
-#define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */
-#define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS)
-#define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS)
-
-#define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */
-#define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */
-#define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */
-#define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */
-#define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */
-
-/* SCIF Serial Port Register - SCSPTR2(half) */
-#define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */
-#define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS)
-#define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS)
-
-#define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */
-#define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */
-#define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */
-#define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */
-#define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */
-#define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */
-
-/* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */
-#define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */
-#define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n))
-#define SH7750_SCBRR1 SH7750_SCBRR_P4(1)
-#define SH7750_SCBRR2 SH7750_SCBRR_P4(2)
-#define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n))
-#define SH7750_SCBRR1_A7 SH7750_SCBRR(1)
-#define SH7750_SCBRR2_A7 SH7750_SCBRR(2)
-
-/* SCIF FIFO Control Register - SCFCR2(half) */
-#define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */
-#define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS)
-#define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS)
-
-#define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\
- signal goes to high level when the
- number of received data stored in
- FIFO exceeds the trigger number */
-#define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */
-#define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */
-#define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */
-#define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */
-#define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */
-#define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */
-#define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */
-
-#define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger,
- Receive Data Full (RDF) Flag sets
- when number of receive data bytes is
- equal or greater than the trigger
- number */
-#define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */
-#define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */
-#define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */
-#define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */
-
-#define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger,
- Transmit FIFO Data Register Empty (TDFE)
- flag sets when the number of remaining
- transmit data bytes is equal or less
- than the trigger number */
-#define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */
-#define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */
-#define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */
-#define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */
-
-#define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */
-#define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset,
- invalidates the transmit data in the
- transmit FIFO */
-#define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset,
- invalidates the receive data in the
- receive FIFO data register and resets
- it to the empty state */
-#define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */
-
-/* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */
-#define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */
-#define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS)
-#define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS)
-
-#define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes
- in transmit FIFO */
-#define SH7750_SCFDR2_T_S 8
-#define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in
- receive FIFO */
-#define SH7750_SCFDR2_R_S 0
-
-/* SCIF Line Status Register - SCLSR2(half, read-only) */
-#define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */
-#define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS)
-#define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS)
-
-#define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */
-
-/*
- * SCI-based Smart Card Interface
- */
-/* Smart Card Mode Register - SCSCMR1(byte) */
-#define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */
-#define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS)
-#define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS)
-
-#define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */
-#define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */
-#define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */
-
-#define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */
-#define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */
-
-/* Smart-card specific bits in other registers */
-/* SCSMR1: */
-#define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */
-
-/* SCSSR1: */
-#define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */
-
-/*
- * I/O Ports
- */
-/* Port Control Register A - PCTRA */
-#define SH7750_PCTRA_REGOFS 0x80002C /* offset */
-#define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
-#define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
-
-#define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
-#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */
-#define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
-#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */
-
-/* Port Data Register A - PDTRA(half) */
-#define SH7750_PDTRA_REGOFS 0x800030 /* offset */
-#define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
-#define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
-
-#define SH7750_PDTRA_BIT(n) (1 << (n))
-
-/* Port Control Register B - PCTRB */
-#define SH7750_PCTRB_REGOFS 0x800040 /* offset */
-#define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
-#define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
-
-#define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
-#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */
-#define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
-#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */
-
-/* Port Data Register B - PDTRB(half) */
-#define SH7750_PDTRB_REGOFS 0x800044 /* offset */
-#define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
-#define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
-
-#define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
-
-/* GPIO Interrupt Control Register - GPIOIC(half) */
-#define SH7750_GPIOIC_REGOFS 0x800048 /* offset */
-#define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
-#define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
-
-#define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */
-
-/*
- * Interrupt Controller - INTC
- */
-/* Interrupt Control Register - ICR (half) */
-#define SH7750_ICR_REGOFS 0xD00000 /* offset */
-#define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS)
-#define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS)
-
-#define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */
-#define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */
-
-#define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */
-#define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while
- SR.BL bit is set to 1 */
-#define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit
- set to 1 */
-
-#define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */
-#define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling
- edge of NMI input */
-#define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising
- edge of NMI input */
-
-#define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */
-#define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded
- interrupt requests */
-#define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent
- interrupt requests */
-
-/* Interrupt Priority Register A - IPRA (half) */
-#define SH7750_IPRA_REGOFS 0xD00004 /* offset */
-#define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS)
-#define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS)
-
-#define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */
-#define SH7750_IPRA_TMU0_S 12
-#define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */
-#define SH7750_IPRA_TMU1_S 8
-#define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */
-#define SH7750_IPRA_TMU2_S 4
-#define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */
-#define SH7750_IPRA_RTC_S 0
-
-/* Interrupt Priority Register B - IPRB (half) */
-#define SH7750_IPRB_REGOFS 0xD00008 /* offset */
-#define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS)
-#define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS)
-
-#define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */
-#define SH7750_IPRB_WDT_S 12
-#define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt
- priority */
-#define SH7750_IPRB_REF_S 8
-#define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */
-#define SH7750_IPRB_SCI1_S 4
-
-/* Interrupt Priority Register C - IPRC (half) */
-#define SH7750_IPRC_REGOFS 0xD00004 /* offset */
-#define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS)
-#define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS)
-
-#define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */
-#define SH7750_IPRC_GPIO_S 12
-#define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */
-#define SH7750_IPRC_DMAC_S 8
-#define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */
-#define SH7750_IPRC_SCIF_S 4
-#define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */
-#define SH7750_IPRC_HUDI_S 0
-
-
-/*
- * User Break Controller registers
- */
-#define SH7750_BARA 0x200000 /* Break address regiser A */
-#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */
-#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */
-#define SH7750_BARB 0x20000c /* Break address regiser B */
-#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */
-#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */
-#define SH7750_BASRB 0x000018 /* Break ASID regiser B */
-#define SH7750_BDRB 0x200018 /* Break data regiser B */
-#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */
-#define SH7750_BRCR 0x200020 /* Break control register */
-
-#define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h b/c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h
deleted file mode 100644
index 1e7a486eb8..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Generic UART Serial driver for SH-4 processors definitions
- *
- * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed.
- * Author: Alexandra Kossovsky <sasha@oktet.ru>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __SH4UART_H__
-#define __SH4UART_H__
-
-#include <rtems/score/sh7750_regs.h>
-
-
-/*
- * Define this to work from gdb stub
- */
-
-/* FIXME: This is BSP-specific */
-#define SH4_WITH_IPL
-
-#define SH4_SCI 1 /* Serial Communication Interface - SCI */
-#define SH4_SCIF 2 /* Serial Communication Interface with FIFO - SCIF */
-#define TRANSMIT_TRIGGER_VALUE(ttrg) ((ttrg) == SH7750_SCFCR2_RTRG_1 ? 1 : \
- (ttrg) == SH7750_SCFCR2_RTRG_4 ? 4 : \
- (ttrg) == SH7750_SCFCR2_RTRG_8 ? 8 : 14)
-
-/*
- * Macros to call UART registers
- */
-#define SCRDR(n) (*(volatile uint8_t*)SH7750_SCRDR(n))
-#define SCRDR1 SCRDR(1)
-#define SCRDR2 SCRDR(2)
-#define SCTDR(n) (*(volatile uint8_t*)SH7750_SCTDR(n))
-#define SCTDR1 SCTDR(1)
-#define SCTDR2 SCTDR(2)
-#define SCSMR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSMR1 : \
- *(volatile uint16_t*)SH7750_SCSMR2)
-#define SCSMR1 SCSMR(1)
-#define SCSMR2 SCSMR(2)
-#define SCSCR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSCR1 : \
- *(volatile uint16_t*)SH7750_SCSCR2)
-#define SCSCR1 SCSCR(1)
-#define SCSCR2 SCSCR(2)
-#define SCSSR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSSR1 : \
- *(volatile uint16_t*)SH7750_SCSSR2)
-#define SCSSR1 SCSSR(1)
-#define SCSSR2 SCSSR(2)
-#define SCSPTR1 (*(volatile uint8_t*)SH7750_SCSPTR1)
-#define SCSPTR2 (*(volatile uint16_t*)SH7750_SCSPTR2)
-#define SCBRR(n) (*(volatile uint8_t*)SH7750_SCBRR(n))
-#define SCBRR1 SCBRR(1)
-#define SCBRR2 SCBRR(2)
-#define SCFCR2 (*(volatile uint16_t*)SH7750_SCFCR2)
-#define SCFDR2 (*(volatile uint16_t*)SH7750_SCFDR2)
-#define SCLSR2 (*(volatile uint16_t*)SH7750_SCLSR2)
-
-#define IPRB (*(volatile uint16_t*)SH7750_IPRB)
-#define IPRC (*(volatile uint16_t*)SH7750_IPRC)
-
-/*
- * The following structure is a descriptor of single UART channel.
- * It contains the initialization information about channel and
- * current operating values
- */
-typedef struct sh4uart {
- uint8_t chn; /* UART channel number */
- uint8_t int_driven; /* UART interrupt vector number, or
- 0 if polled I/O */
- void *tty; /* termios channel descriptor */
-
- volatile const char *tx_buf; /* Transmit buffer from termios */
- volatile uint32_t tx_buf_len; /* Transmit buffer length */
- volatile uint32_t tx_ptr; /* Index of next char to transmit*/
-
- rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */
- rtems_isr_entry old_handler_receive;
-
- tcflag_t c_iflag; /* termios input mode flags */
- bool parerr_mark_flag; /* Parity error processing state */
-} sh4uart;
-
-/*
- * Functions from sh4uart.c
- */
-
-/* sh4uart_init --
- * This function verifies the input parameters and perform initialization
- * of the Motorola Coldfire on-chip UART descriptor structure.
- *
- */
-rtems_status_code
-sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven);
-
-/* sh4uart_reset --
- * This function perform the hardware initialization of Motorola
- * Coldfire processor on-chip UART controller using parameters
- * filled by the sh4uart_init function.
- */
-rtems_status_code
-sh4uart_reset(sh4uart *uart);
-
-/* sh4uart_disable --
- * This function disable the operations on Motorola Coldfire UART
- * controller
- */
-rtems_status_code
-sh4uart_disable(sh4uart *uart, int disable_port);
-
-/* sh4uart_set_attributes --
- * This function parse the termios attributes structure and perform
- * the appropriate settings in hardware.
- */
-rtems_status_code
-sh4uart_set_attributes(sh4uart *mcf, const struct termios *t);
-
-/* sh4uart_poll_read --
- * This function tried to read character from MCF UART and perform
- * error handling.
- */
-int
-sh4uart_poll_read(sh4uart *uart);
-
-#ifdef SH4_WITH_IPL
-/* ipl_console_poll_read --
- * This function tried to read character from MCF UART over SH-IPL.
- */
-int
-ipl_console_poll_read(int minor);
-
-/* sh4uart_interrupt_write --
- * This function initiate transmitting of the buffer in interrupt mode.
- */
-rtems_status_code
-sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len);
-
-/* sh4uart_poll_write --
- * This function transmit buffer byte-by-byte in polling mode.
- */
-int
-sh4uart_poll_write(sh4uart *uart, const char *buf, int len);
-
-/* ipl_console_poll_write --
- * This function transmit buffer byte-by-byte in polling mode over SH-IPL.
- */
-int
-ipl_console_poll_write(int minor, const char *buf, int len);
-
-/*
- * ipl_finish --
- * Says gdb that program finished to get out from it.
- */
-extern void ipl_finish(void);
-#endif
-
-/* sh4uart_stop_remote_tx --
- * This function stop data flow from remote device.
- */
-rtems_status_code
-sh4uart_stop_remote_tx(sh4uart *uart);
-
-/* sh4uart_start_remote_tx --
- * This function resume data flow from remote device.
- */
-rtems_status_code
-sh4uart_start_remote_tx(sh4uart *uart);
-
-/* Descriptor structures for two on-chip UART channels */
-extern sh4uart sh4_uarts[2];
-
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/sci/console.c b/c/src/lib/libcpu/sh/sh7750/sci/console.c
deleted file mode 100644
index 0325813266..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/sci/console.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * Console driver for SH-4 UART modules
- *
- * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
- * Author: Alexandra Kossovsky <sasha@oktet.ru>
- *
- * COPYRIGHT (c) 1989-1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <termios.h>
-#include <rtems/libio.h>
-#include "sh/sh4uart.h"
-
-/* Descriptor structures for two on-chip UART channels */
-sh4uart sh4_uarts[2];
-
-/* Console operations mode:
- * 0 - raw (non-termios) polled input/output
- * 1 - termios-based polled input/output
- * 2 - termios-based interrupt-driven input/output
- * 3 - non-termios over gdb stub
- */
-int console_mode = 3;
-#define CONSOLE_MODE_RAW (0)
-#define CONSOLE_MODE_POLL (1)
-#define CONSOLE_MODE_INT (2)
-#define CONSOLE_MODE_IPL (3)
-
-/* Wrapper functions for SH-4 UART generic driver */
-
-/* console_poll_read --
- * wrapper for poll read function
- *
- * PARAMETERS:
- * minor - minor device number
- *
- * RETURNS:
- * character code readed from UART, or -1 if there is no characters
- * available
- */
-static int
-console_poll_read(int minor)
-{
- return sh4uart_poll_read(&sh4_uarts[minor]);
-}
-
-/* console_interrupt_write --
- * wrapper for interrupt write function
- *
- * PARAMETERS:
- * minor - minor device number
- * buf - output buffer
- * len - output buffer length
- *
- * RETURNS:
- * result code
- */
-static int
-console_interrupt_write(int minor, const char *buf, int len)
-{
- return sh4uart_interrupt_write(&sh4_uarts[minor], buf, len);
-}
-
-/* console_poll_write --
- * wrapper for polling mode write function
- *
- * PARAMETERS:
- * minor - minor device number
- * buf - output buffer
- * len - output buffer length
- *
- * RETURNS:
- * result code
- */
-static int
-console_poll_write(int minor, const char *buf, int len)
-{
- return sh4uart_poll_write(&sh4_uarts[minor], buf, len);
-}
-
-/* console_set_attributes --
- * wrapper for hardware-dependent termios attributes setting
- *
- * PARAMETERS:
- * minor - minor device number
- * t - pointer to the termios structure
- *
- * RETURNS:
- * result code
- */
-static int
-console_set_attributes(int minor, const struct termios *t)
-{
- return sh4uart_set_attributes(&sh4_uarts[minor], t);
-}
-
-/* console_stop_remote_tx --
- * wrapper for stopping data flow from remote party.
- *
- * PARAMETERS:
- * minor - minor device number
- *
- * RETURNS:
- * result code
- */
-static int
-console_stop_remote_tx(int minor)
-{
- if (minor < sizeof(sh4_uarts)/sizeof(sh4_uarts[0]))
- return sh4uart_stop_remote_tx(&sh4_uarts[minor]);
- else
- return RTEMS_INVALID_NUMBER;
-}
-
-/* console_start_remote_tx --
- * wrapper for resuming data flow from remote party.
- *
- * PARAMETERS:
- * minor - minor device number
- *
- */
-static int
-console_start_remote_tx(int minor)
-{
- if (minor < sizeof(sh4_uarts)/sizeof(sh4_uarts[0]))
- return sh4uart_start_remote_tx(&sh4_uarts[minor]);
- else
- return RTEMS_INVALID_NUMBER;
-}
-
-/* console_first_open --
- * wrapper for UART controller initialization functions
- *
- * PARAMETERS:
- * major - major device number
- * minor - minor device number
- * arg - libio device open argument
- *
- * RETURNS:
- * error code
- */
-static int
-console_first_open(int major, int minor, void *arg)
-{
- rtems_libio_open_close_args_t *args = arg;
- rtems_status_code sc;
-
- sc = sh4uart_init(&sh4_uarts[minor], /* uart */
- args->iop->data1, /* tty */
- minor+1, /* channel */
- (console_mode == CONSOLE_MODE_INT));
-
- if (sc == RTEMS_SUCCESSFUL)
- sc = sh4uart_reset(&sh4_uarts[minor]);
-
- return sc;
-}
-
-/* console_last_close --
- * wrapper for UART controller close function
- *
- * PARAMETERS:
- * major - major device number
- * minor - minor device number
- * arg - libio device close argument
- *
- * RETURNS:
- * error code
- */
-static int
-console_last_close(int major, int minor, void *arg)
-{
- return sh4uart_disable(&sh4_uarts[minor]);
-}
-
-/* console_initialize --
- * This routine initializes the console IO drivers and register devices
- * in RTEMS I/O system.
- *
- * PARAMETERS:
- * major - major console device number
- * minor - minor console device number (not used)
- * arg - device initialize argument
- *
- * RETURNS:
- * RTEMS error code (RTEMS_SUCCESSFUL if device initialized successfuly)
- */
-rtems_device_driver
-console_initialize(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- rtems_status_code status;
-
-#ifdef SH4_WITH_IPL
- /* booting from flash we cannot have IPL console */
- if (boot_mode != SH4_BOOT_MODE_IPL && console_mode == CONSOLE_MODE_IPL)
- console_mode = CONSOLE_MODE_INT;
-
- /* break out from gdb if neccessary */
- if (boot_mode == SH4_BOOT_MODE_IPL && console_mode != CONSOLE_MODE_IPL)
- ipl_finish();
-#endif
-
- /*
- * Set up TERMIOS
- */
- if ((console_mode != CONSOLE_MODE_RAW) &&
- (console_mode != CONSOLE_MODE_IPL))
- rtems_termios_initialize ();
-
- /*
- * Register the devices
- */
- status = rtems_io_register_name ("/dev/console", major, 0);
- if (status != RTEMS_SUCCESSFUL)
- rtems_fatal_error_occurred (status);
-
- status = rtems_io_register_name ("/dev/aux", major, 1);
- if (status != RTEMS_SUCCESSFUL)
- rtems_fatal_error_occurred (status);
-
- if (console_mode == CONSOLE_MODE_RAW)
- {
- rtems_status_code sc;
- sc = sh4uart_init(&sh4_uarts[0], /* uart */
- NULL, /* tty */
- 1, /* UART channel number */
- 0); /* Poll-mode */
-
- if (sc == RTEMS_SUCCESSFUL)
- sc = sh4uart_reset(&sh4_uarts[0]);
-
- sc = sh4uart_init(&sh4_uarts[1], /* uart */
- NULL, /* tty */
- 2, /* UART channel number */
- 0); /* Poll-mode */
-
- if (sc == RTEMS_SUCCESSFUL)
- sc = sh4uart_reset(&sh4_uarts[1]);
-
- return sc;
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-/* console_open --
- * Open console device driver. Pass appropriate termios callback
- * functions to termios library.
- *
- * PARAMETERS:
- * major - major device number for console devices
- * minor - minor device number for console
- * arg - device opening argument
- *
- * RETURNS:
- * RTEMS error code
- */
-rtems_device_driver
-console_open(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- static const rtems_termios_callbacks intr_callbacks = {
- console_first_open, /* firstOpen */
- console_last_close, /* lastClose */
- NULL, /* pollRead */
- console_interrupt_write, /* write */
- console_set_attributes, /* setAttributes */
- console_stop_remote_tx, /* stopRemoteTx */
- console_start_remote_tx, /* startRemoteTx */
- 1 /* outputUsesInterrupts */
- };
- static const rtems_termios_callbacks poll_callbacks = {
- console_first_open, /* firstOpen */
- console_last_close, /* lastClose */
- console_poll_read, /* pollRead */
- console_poll_write, /* write */
- console_set_attributes, /* setAttributes */
- console_stop_remote_tx, /* stopRemoteTx */
- console_start_remote_tx, /* startRemoteTx */
- 0 /* outputUsesInterrupts */
- };
-
- switch (console_mode)
- {
- case CONSOLE_MODE_RAW:
- case CONSOLE_MODE_IPL:
- return RTEMS_SUCCESSFUL;
-
- case CONSOLE_MODE_INT:
- return rtems_termios_open(major, minor, arg, &intr_callbacks);
-
- case CONSOLE_MODE_POLL:
- return rtems_termios_open(major, minor, arg, &poll_callbacks);
-
- default:
- rtems_fatal_error_occurred(0xC07A1310);
- }
-
- return RTEMS_INTERNAL_ERROR;
-}
-
-/* console_close --
- * Close console device.
- *
- * PARAMETERS:
- * major - major device number for console devices
- * minor - minor device number for console
- * arg - device close argument
- *
- * RETURNS:
- * RTEMS error code
- */
-rtems_device_driver
-console_close(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- if ((console_mode != CONSOLE_MODE_RAW) &&
- (console_mode != CONSOLE_MODE_IPL))
- return rtems_termios_close (arg);
- else
- return RTEMS_SUCCESSFUL;
-}
-
-/* console_read --
- * Read from the console device
- *
- * PARAMETERS:
- * major - major device number for console devices
- * minor - minor device number for console
- * arg - device read argument
- *
- * RETURNS:
- * RTEMS error code
- */
-rtems_device_driver
-console_read(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- if ((console_mode != CONSOLE_MODE_RAW) &&
- (console_mode != CONSOLE_MODE_IPL))
- {
- return rtems_termios_read (arg);
- }
- else
- {
- rtems_libio_rw_args_t *argp = arg;
- char *buf = argp->buffer;
- int count = argp->count;
- int n = 0;
- int c;
- while (n < count)
- {
- do {
- c = (console_mode == CONSOLE_MODE_RAW) ?
- sh4uart_poll_read(&sh4_uarts[minor]) :
- ipl_console_poll_read(minor);
- } while (c == -1);
- if (c == '\r')
- c = '\n';
- *(buf++) = c;
- n++;
- if (c == '\n')
- break;
- }
- argp->bytes_moved = n;
- return RTEMS_SUCCESSFUL;
- }
-}
-
-/* console_write --
- * Write to the console device
- *
- * PARAMETERS:
- * major - major device number for console devices
- * minor - minor device number for console
- * arg - device write argument
- *
- * RETURNS:
- * RTEMS error code
- */
-rtems_device_driver
-console_write(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- switch (console_mode)
- {
- case CONSOLE_MODE_POLL:
- case CONSOLE_MODE_INT:
- return rtems_termios_write (arg);
- case CONSOLE_MODE_RAW:
- {
- rtems_libio_rw_args_t *argp = arg;
- char cr = '\r';
- char *buf = argp->buffer;
- int count = argp->count;
- int i;
-
- for (i = 0; i < count; i++)
- {
- if (*buf == '\n')
- sh4uart_poll_write(&sh4_uarts[minor], &cr, 1);
- sh4uart_poll_write(&sh4_uarts[minor], buf, 1);
- buf++;
- }
- argp->bytes_moved = count;
- return RTEMS_SUCCESSFUL;
- }
-#ifdef SH4_WITH_IPL
- case CONSOLE_MODE_IPL:
- {
- rtems_libio_rw_args_t *argp = arg;
- char *buf = argp->buffer;
- int count = argp->count;
- ipl_console_poll_write(minor, buf, count);
- argp->bytes_moved = count;
- return RTEMS_SUCCESSFUL;
- }
-#endif
- default: /* Unreachable */
- return RTEMS_NOT_DEFINED;
- }
-}
-
-/* console_control --
- * Handle console device I/O control (IOCTL)
- *
- * PARAMETERS:
- * major - major device number for console devices
- * minor - minor device number for console
- * arg - device ioctl argument
- *
- * RETURNS:
- * RTEMS error code
- */
-rtems_device_driver
-console_control(rtems_device_major_number major,
- rtems_device_minor_number minor,
- void *arg)
-{
- if ((console_mode != CONSOLE_MODE_RAW) &&
- (console_mode != CONSOLE_MODE_IPL))
- {
- return rtems_termios_ioctl (arg);
- }
- else
- {
- return RTEMS_SUCCESSFUL;
- }
-}
diff --git a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c b/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
deleted file mode 100644
index 7acc1de337..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
+++ /dev/null
@@ -1,910 +0,0 @@
-/*
- * Generic UART Serial driver for SH-4 processors
- *
- * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed.
- * Author: Alexandra Kossovsky <sasha@oktet.ru>
- *
- * COPYRIGHT (c) 1989-2000.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#include <rtems.h>
-#include <termios.h>
-#include <rtems/libio.h>
-#include <bsp.h>
-#include "sh/sh4uart.h"
-
-#ifndef SH4_UART_INTERRUPT_LEVEL
-#define SH4_UART_INTERRUPT_LEVEL 4
-#endif
-
-/* Forward function declarations */
-static rtems_isr
-sh4uart1_interrupt_transmit(rtems_vector_number vec);
-static rtems_isr
-sh4uart1_interrupt_receive(rtems_vector_number vec);
-static rtems_isr
-sh4uart2_interrupt_transmit(rtems_vector_number vec);
-static rtems_isr
-sh4uart2_interrupt_receive(rtems_vector_number vec);
-
-/*
- * sh4uart_init --
- * This function verifies the input parameters and perform initialization
- * of the SH-4 on-chip UART descriptor structure.
- *
- * PARAMETERS:
- * uart - pointer to the UART channel descriptor structure
- * tty - pointer to termios structure
- * chn - channel number (SH4_SCI/SH4_SCIF -- 1/2)
- * int_driven - interrupt-driven (1) or polled (0) I/O mode
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL if all parameters are valid, or error code
- */
-rtems_status_code
-sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven)
-{
- if (uart == NULL)
- return RTEMS_INVALID_ADDRESS;
-
- if ((chn != SH4_SCI) && (chn != SH4_SCIF))
- return RTEMS_INVALID_NUMBER;
-
- uart->chn = chn;
- uart->tty = tty;
- uart->int_driven = int_driven;
-
-#if 0
- sh4uart_poll_write(uart, "init", 4);
-#endif
- return RTEMS_SUCCESSFUL;
-}
-
-/*
- * sh4uart_get_Pph --
- * Get current peripheral module clock.
- *
- * PARAMETERS: none;
- * Cpu clock is get from CPU_CLOCK_RATE_HZ marco
- * (defined in bspopts.h, included from bsp.h)
- *
- * RETURNS:
- * peripheral module clock in Hz.
- */
-static uint32_t
-sh4uart_get_Pph(void)
-{
- uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR;
- uint32_t Pph = CPU_CLOCK_RATE_HZ;
-
- switch (frqcr & SH7750_FRQCR_IFC) {
- case SH7750_FRQCR_IFCDIV1: break;
- case SH7750_FRQCR_IFCDIV2: Pph *= 2; break;
- case SH7750_FRQCR_IFCDIV3: Pph *= 3; break;
- case SH7750_FRQCR_IFCDIV4: Pph *= 4; break;
- case SH7750_FRQCR_IFCDIV6: Pph *= 6; break;
- case SH7750_FRQCR_IFCDIV8: Pph *= 8; break;
- default: /* unreachable */
- break;
- }
-
- switch (frqcr & SH7750_FRQCR_PFC) {
- case SH7750_FRQCR_PFCDIV2: Pph /= 2; break;
- case SH7750_FRQCR_PFCDIV3: Pph /= 3; break;
- case SH7750_FRQCR_PFCDIV4: Pph /= 4; break;
- case SH7750_FRQCR_PFCDIV6: Pph /= 6; break;
- case SH7750_FRQCR_PFCDIV8: Pph /= 8; break;
- default: /* unreachable */
- break;
- }
-
- return Pph;
-}
-
-/*
- * sh4uart_set_baudrate --
- * Program the UART timer to specified baudrate
- *
- * PARAMETERS:
- * uart - pointer to UART descriptor structure
- * baud - termios baud rate (B50, B9600, etc...)
- *
- * ALGORITHM:
- * see SH7750 Hardware Manual.
- *
- * RETURNS:
- * none
- */
-static void
-sh4uart_set_baudrate(sh4uart *uart, speed_t baud)
-{
- uint32_t rate;
- int16_t div;
- int n;
- uint32_t Pph = sh4uart_get_Pph();
-
- switch (baud) {
- case B50: rate = 50; break;
- case B75: rate = 75; break;
- case B110: rate = 110; break;
- case B134: rate = 134; break;
- case B150: rate = 150; break;
- case B200: rate = 200; break;
- case B300: rate = 300; break;
- case B600: rate = 600; break;
- case B1200: rate = 1200; break;
- case B2400: rate = 2400; break;
- case B4800: rate = 4800; break;
- case B9600: rate = 9600; break;
- case B19200: rate = 19200; break;
- case B38400: rate = 38400; break;
- case B57600: rate = 57600; break;
-#ifdef B115200
- case B115200: rate = 115200; break;
-#endif
-#ifdef B230400
- case B230400: rate = 230400; break;
-#endif
- default: rate = 9600; break;
- }
-
- for (n = 0; n < 4; n++) {
- div = Pph / (32 * (1 << (2 * n)) * rate) - 1;
- if (div < 0x100)
- break;
- }
-
- /* Set default baudrate if specified baudrate is impossible */
- if (n >= 4)
- sh4uart_set_baudrate(uart, B9600);
-
- if ( uart->chn == 1 ) {
- volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1;
- *smr1 &= ~SH7750_SCSMR_CKS;
- *smr1 |= n << SH7750_SCSMR_CKS_S;
- } else {
- volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2;
- *smr2 &= ~SH7750_SCSMR_CKS;
- *smr2 |= n << SH7750_SCSMR_CKS_S;
- }
-
- SCBRR(uart->chn) = div;
- /* Wait at least 1 bit interwal */
- rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate));
-}
-
-/*
- * sh4uart_reset --
- * This function perform the hardware initialization of SH-4
- * on-chip UART controller using parameters
- * filled by the sh4uart_init function.
- *
- * PARAMETERS:
- * uart - pointer to UART channel descriptor structure
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL if channel is initialized successfully, error
- * code in other case
- */
-rtems_status_code
-sh4uart_reset(sh4uart *uart)
-{
- register int chn;
- register int int_driven;
- rtems_status_code rc;
- uint16_t tmp;
-
- if (uart == NULL)
- return RTEMS_INVALID_ADDRESS;
-
- chn = uart->chn;
- int_driven = uart->int_driven;
-
- if ( chn == 1 ) {
- volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
- volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1;
- *scr1 = 0x0; /* Is set properly at the end of this function */
- *smr1 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
- } else {
- volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
- volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2;
- *scr2 = 0x0; /* Is set properly at the end of this function */
- *smr2 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
- }
-
- if (chn == SH4_SCIF)
- SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
- SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
-
- if (chn == SH4_SCI)
- SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO;
- else
- SCSPTR2 = SH7750_SCSPTR2_RTSDT;
-
- if (int_driven) {
- uint16_t ipr;
-
- if (chn == SH4_SCI) {
- ipr = IPRB;
- ipr &= ~SH7750_IPRB_SCI1;
- ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S;
- IPRB = ipr;
-
- rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
- SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
- &uart->old_handler_transmit);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
-
- rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
- SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
- &uart->old_handler_receive);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
- } else {
- ipr = IPRC;
- ipr &= ~SH7750_IPRC_SCIF;
- ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S;
- IPRC = ipr;
-
- rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
- SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
- &uart->old_handler_transmit);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
- rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
- SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
- &uart->old_handler_receive);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
- }
- uart->tx_buf = NULL;
- uart->tx_ptr = uart->tx_buf_len = 0;
- }
-
- sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately,
- it is differ to termios default */
-
- tmp = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
- (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
- (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
-
- if ( chn == 1 ) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr = tmp;
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr = tmp;
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-/*
- * sh4uart_disable --
- * This function disable the operations on SH-4 UART controller
- *
- * PARAMETERS:
- * uart - pointer to UART channel descriptor structure
- * disable_port - disable receive and transmit on the port
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL if UART closed successfuly, or error code in
- * other case
- */
-rtems_status_code
-sh4uart_disable(sh4uart *uart, int disable_port)
-{
- rtems_status_code rc;
-
- if (disable_port) {
- if ( uart->chn == 1 ) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
- }
- }
-
- if (uart->int_driven) {
- rc = rtems_interrupt_catch(uart->old_handler_transmit,
- uart->chn == SH4_SCI ? SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
- NULL);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
- rc = rtems_interrupt_catch(uart->old_handler_receive,
- uart->chn == SH4_SCI ? SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
- NULL);
- if (rc != RTEMS_SUCCESSFUL)
- return rc;
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-/*
- * sh4uart_set_attributes --
- * This function parse the termios attributes structure and perform
- * the appropriate settings in hardware.
- *
- * PARAMETERS:
- * uart - pointer to the UART descriptor structure
- * t - pointer to termios parameters
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL
- */
-rtems_status_code
-sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
-{
- int level;
- speed_t baud;
- uint16_t smr;
-
- smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn));
-
- baud = cfgetospeed(t);
-
- /* Set flow control XXX*/
- if ((t->c_cflag & CRTSCTS) != 0) {
- }
-
- /* Set character size -- only 7 or 8 bit */
- switch (t->c_cflag & CSIZE) {
- case CS5:
- case CS6:
- case CS7: smr |= SH7750_SCSMR_CHR_7; break;
- case CS8: smr &= ~SH7750_SCSMR_CHR_7; break;
- }
-
- /* Set number of stop bits */
- if ((t->c_cflag & CSTOPB) != 0)
- smr |= SH7750_SCSMR_STOP_2;
- else
- smr &= ~SH7750_SCSMR_STOP_2;
-
- /* Set parity mode */
- if ((t->c_cflag & PARENB) != 0) {
- smr |= SH7750_SCSMR_PE;
- if ((t->c_cflag & PARODD) != 0)
- smr |= SH7750_SCSMR_PM_ODD;
- else
- smr &= ~SH7750_SCSMR_PM_ODD;
- } else
- smr &= ~SH7750_SCSMR_PE;
-
- rtems_interrupt_disable(level);
- /* wait untill all data is transmitted */
- /* XXX JOEL says this is broken -- interrupts are OFF so NO ticks */
- rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100));
-
- if ( uart->chn == 1 ) {
- volatile uint8_t *scrP = (volatile uint8_t *)SH7750_SCSCR1;
- volatile uint8_t *smrP = (volatile uint8_t *)SH7750_SCSMR1;
-
- *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */
- sh4uart_set_baudrate(uart, baud);
- *smrP = (uint8_t)smr;
- *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */
- } else {
- volatile uint16_t *scrP = (volatile uint16_t *)SH7750_SCSCR2;
- volatile uint16_t *smrP = (volatile uint16_t *)SH7750_SCSMR2;
-
- *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */
- sh4uart_set_baudrate(uart, baud);
- *smrP = (uint8_t)smr;
- *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */
- }
-
- rtems_interrupt_enable(level);
-
- return RTEMS_SUCCESSFUL;
-}
-
-/*
- * sh4uart_handle_error --
- * Perfoms error (Overrun, Framing & Parity) handling
- *
- * PARAMETERS:
- * uart - pointer to UART descriptor structure
- *
- * RETURNS:
- * nothing
- */
-static void
-sh4uart_handle_error(sh4uart *uart)
-{
- if (uart->chn == SH4_SCI) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER);
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER);
- *scr &= ~(SH7750_SCLSR2_ORER);
- }
-}
-
-/*
- * sh4uart_poll_read --
- * This function tried to read character from SH-4 UART and perform
- * error handling. When parity or framing error occured, return
- * value dependent on termios input mode flags:
- * - received character, if IGNPAR == 1
- * - 0, if IGNPAR == 0 and PARMRK == 0
- * - 0xff and 0x00 on next poll_read invocation, if IGNPAR == 0 and
- * PARMRK == 1
- *
- * PARAMETERS:
- * uart - pointer to UART descriptor structure
- *
- * RETURNS:
- * code of received character or -1 if no characters received.
- */
-int
-sh4uart_poll_read(sh4uart *uart)
-{
- int chn = uart->chn;
- int parity_error = 0;
- int break_occured = 0;
- int ch;
-
- if (uart->parerr_mark_flag == true) {
- uart->parerr_mark_flag = false;
- return 0;
- }
-
- if (chn == SH4_SCI) {
- if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
- SH7750_SCSSR1_ORER)) != 0) {
- if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
- parity_error = 1;
- sh4uart_handle_error(uart);
- }
- if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0)
- return -1;
- } else {
- if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
- SH7750_SCSSR2_BRK)) != 0 ||
- (SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
- if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
- parity_error = 1;
- if (SCSSR2 & SH7750_SCSSR2_BRK)
- break_occured = 1;
- sh4uart_handle_error(uart);
- }
- if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0)
- return -1;
- }
-
- if (parity_error && !(uart->c_iflag & IGNPAR)) {
- if (uart->c_iflag & PARMRK) {
- uart->parerr_mark_flag = true;
- return 0xff;
- } else
- return 0;
- }
-
- if (break_occured && !(uart->c_iflag & BRKINT)) {
- if (uart->c_iflag & IGNBRK)
- return 0;
- else
- return 0; /* XXX -- SIGINT */
- }
-
- ch = SCRDR(chn);
-
- if (uart->chn == SH4_SCI) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr &= ~SH7750_SCSSR1_RDRF;
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr &= ~SH7750_SCSSR2_RDF;
- }
-
- return ch;
-}
-
-/*
- * sh4uart_poll_write --
- * This function transmit buffer byte-by-byte in polling mode.
- *
- * PARAMETERS:
- * uart - pointer to the UART descriptor structure
- * buf - pointer to transmit buffer
- * len - transmit buffer length
- *
- * RETURNS:
- * 0
- */
-int
-sh4uart_poll_write(sh4uart *uart, const char *buf, int len)
-{
- volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
- volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2;
-
- while (len) {
- if (uart->chn == SH4_SCI) {
- while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) {
- SCTDR1 = *buf++;
- len--;
- *ssr1 &= ~SH7750_SCSSR1_TDRE;
- }
- } else {
- while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) {
- int i;
- for (i = 0;
- i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
- SH7750_SCFCR2_TTRG);
- i++) {
- SCTDR2 = *buf++;
- len--;
- }
- while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
- (SCSSR2 & SH7750_SCSSR2_TEND) == 0);
- *ssr2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
- }
- }
- }
- return 0;
-}
-
-/**********************************
- * Functions to handle interrupts *
- **********************************/
-/* sh4uart1_interrupt_receive --
- * UART interrupt handler routine -- SCI
- * Receiving data
- *
- * PARAMETERS:
- * vec - interrupt vector number
- *
- * RETURNS:
- * none
- */
-static rtems_isr
-sh4uart1_interrupt_receive(rtems_vector_number vec)
-{
- register int bp = 0;
- char buf[32];
- volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
-
-
- /* Find UART descriptor from vector number */
- sh4uart *uart = &sh4_uarts[0];
-
- while (1) {
- if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) {
- /* Receive character and handle frame/parity errors */
- if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
- SH7750_SCSSR1_ORER)) != 0) {
- if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) {
- if (!(uart->c_iflag & IGNPAR)) {
- if (uart->c_iflag & PARMRK) {
- buf[bp++] = 0xff;
- buf[bp++] = 0x00;
- } else
- buf[bp++] = 0x00;
- } else
- buf[bp++] = SCRDR1;
- }
- sh4uart_handle_error(uart);
- } else
- buf[bp++] = SCRDR1;
- *ssr1 &= ~SH7750_SCSSR1_RDRF;
- } else {
- if (bp != 0)
- rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
- break;
- }
- }
-}
-
-/* sh4uart2_interrupt_receive --
- * UART interrupt handler routine -- SCIF
- * Receiving data
- *
- * PARAMETERS:
- * vec - interrupt vector number
- *
- * RETURNS:
- * none
- */
-static rtems_isr
-sh4uart2_interrupt_receive(rtems_vector_number vec)
-{
- register int bp = 0;
- char buf[32];
- volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2;
-
-
- /* Find UART descriptor from vector number */
- sh4uart *uart = &sh4_uarts[1];
-
- while (1) {
- if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) {
- if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
- SH7750_SCSSR2_BRK)) != 0 ||
- (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
- if (SCSSR2 & SH7750_SCSSR2_ER) {
- if (!(uart->c_iflag & IGNPAR)) {
- if (uart->c_iflag & PARMRK) {
- buf[bp++] = 0xff;
- buf[bp++] = 0x00;
- } else
- buf[bp++] = 0x00;
- } else
- buf[bp++] = SCRDR1;
- }
-
- if (SCSSR2 & SH7750_SCSSR2_BRK) {
- if (uart->c_iflag & IGNBRK)
- buf[bp++] = 0x00;
- else
- buf[bp++] = 0x00; /* XXX -- SIGINT */
- }
-
- sh4uart_handle_error(uart);
- } else
- buf[bp++] = SCRDR1;
- *ssr2 &= ~SH7750_SCSSR2_RDF;
- } else {
- if (bp != 0)
- rtems_termios_enqueue_raw_characters(uart->tty, buf, bp);
- break;
- }
- }
-}
-
-
-/* sh4uart1_interrupt_transmit --
- * UART interrupt handler routine -- SCI
- * It continues transmit data when old part of data is transmitted
- *
- * PARAMETERS:
- * vec - interrupt vector number
- *
- * RETURNS:
- * none
- */
-static rtems_isr
-sh4uart1_interrupt_transmit(rtems_vector_number vec)
-{
- volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
- volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
-
- /* Find UART descriptor from vector number */
- sh4uart *uart = &sh4_uarts[0];
-
- if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) {
- while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
- uart->tx_ptr < uart->tx_buf_len) {
- SCTDR1 = uart->tx_buf[uart->tx_ptr++];
- *ssr1 &= ~SH7750_SCSSR1_TDRE;
- }
- } else {
- register int dequeue = uart->tx_buf_len;
-
- uart->tx_buf = NULL;
- uart->tx_ptr = uart->tx_buf_len = 0;
-
- /* Disable interrupts while we do not have any data to transmit */
- *scr1 &= ~SH7750_SCSCR_TIE;
-
- rtems_termios_dequeue_characters(uart->tty, dequeue);
- }
-}
-
-/* sh4uart2_interrupt_transmit --
- * UART interrupt handler routine -- SCI
- * It continues transmit data when old part of data is transmitted
- *
- * PARAMETERS:
- * vec - interrupt vector number
- *
- * RETURNS:
- * none
- */
-static rtems_isr
-sh4uart2_interrupt_transmit(rtems_vector_number vec)
-{
- volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1;
- volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
-
- /* Find UART descriptor from vector number */
- sh4uart *uart = &sh4_uarts[1];
-
- if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) {
- while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) {
- int i;
- for (i = 0;
- i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & SH7750_SCFCR2_TTRG);
- i++)
- SCTDR2 = uart->tx_buf[uart->tx_ptr++];
- while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 ||
- (SCSSR1 & SH7750_SCSSR1_TEND) == 0);
- *ssr1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
- }
- } else {
- register int dequeue = uart->tx_buf_len;
-
- uart->tx_buf = NULL;
- uart->tx_ptr = uart->tx_buf_len = 0;
-
- /* Disable interrupts while we do not have any data to transmit */
- *scr2 &= ~SH7750_SCSCR_TIE;
-
- rtems_termios_dequeue_characters(uart->tty, dequeue);
- }
-}
-
-/* sh4uart_interrupt_write --
- * This function initiate transmitting of the buffer in interrupt mode.
- *
- * PARAMETERS:
- * uart - pointer to the UART descriptor structure
- * buf - pointer to transmit buffer
- * len - transmit buffer length
- *
- * RETURNS:
- * 0
- */
-rtems_status_code
-sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len)
-{
- if (len > 0) {
- volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1;
- volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2;
-
- while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
-
- uart->tx_buf = buf;
- uart->tx_buf_len = len;
- uart->tx_ptr = 0;
-
- if (uart->chn == SH4_SCI)
- *scr1 |= SH7750_SCSCR_TIE;
- else
- *scr2 |= SH7750_SCSCR_TIE;
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-/* sh4uart_stop_remote_tx --
- * This function stop data flow from remote device.
- *
- * PARAMETERS:
- * uart - pointer to the UART descriptor structure
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL
- */
-rtems_status_code
-sh4uart_stop_remote_tx(sh4uart *uart)
-{
- if ( uart->chn == 1 ) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE);
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE);
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-/* sh4uart_start_remote_tx --
- * This function resume data flow from remote device.
- *
- * PARAMETERS:
- * uart - pointer to the UART descriptor structure
- *
- * RETURNS:
- * RTEMS_SUCCESSFUL
- */
-rtems_status_code
-sh4uart_start_remote_tx(sh4uart *uart)
-{
- if ( uart->chn == 1 ) {
- volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1;
- *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE;
- } else {
- volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2;
- *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE;
- }
-
- return RTEMS_SUCCESSFUL;
-}
-
-#ifdef SH4_WITH_IPL
-/*********************************
- * Functions for SH-IPL gdb stub *
- *********************************/
-
-/*
- * ipl_finish --
- * Says gdb that program finished to get out from it.
- */
-extern void ipl_finish(void);
-__asm__ (
-" .global _ipl_finish\n"
-"_ipl_finish:\n"
-" mov.l __ipl_finish_value, r0\n"
-" trapa #0x3f\n"
-" nop\n"
-" rts\n"
-" nop\n"
-" .align 4\n"
-"__ipl_finish_value:\n"
-" .long 255"
-);
-
-extern int ipl_serial_input(int poll_count);
-__asm__ (
-" .global _ipl_serial_input\n"
-"_ipl_serial_input:\n"
-" mov #1,r0\n"
-" trapa #0x3f\n"
-" nop\n"
-" rts\n"
-" nop\n");
-
-extern void ipl_serial_output(const char *buf, int len);
-__asm__ (
-" .global _ipl_serial_output\n"
-"_ipl_serial_output:\n"
-" mov #0,r0\n"
-" trapa #0x3f\n"
-" nop\n"
-" rts\n"
-" nop\n");
-
-/* ipl_console_poll_read --
- * poll read operation for simulator console through ipl mechanism.
- *
- * PARAMETERS:
- * minor - minor device number
- *
- * RETURNS:
- * character code red from UART, or -1 if there is no characters
- * available
- */
-int
-ipl_console_poll_read(int minor)
-{
- unsigned char buf;
- buf = ipl_serial_input(0x100000);
- return buf;
-}
-
-/* ipl_console_poll_write --
- * wrapper for polling mode write function
- *
- * PARAMETERS:
- * minor - minor device number
- * buf - output buffer
- * len - output buffer length
- *
- * RETURNS:
- * result code (0)
- */
-int
-ipl_console_poll_write(int minor, const char *buf, int len)
-{
- int c;
- while (len > 0) {
- c = (len < 64 ? len : 64);
- ipl_serial_output(buf, c);
- len -= c;
- buf += c;
- }
- return 0;
-}
-#endif
diff --git a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
deleted file mode 100644
index 52a033bb75..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file contains the basic algorithms for all assembly code used
- * in an specific CPU port of RTEMS. These algorithms must be implemented
- * in assembly language
- *
- * NOTE: This port uses a C file with inline assembler instructions
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-/*
- * This is supposed to be an assembly file. This means that system.h
- * and cpu.h should not be included in a "real" cpu_asm file. An
- * implementation in assembly should include "cpu_asm.h"
- */
-
-#include <rtems/system.h>
-#include <rtems/score/cpu.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/threaddispatch.h>
-#include <rtems/score/sh.h>
-#include <rtems/score/ispsh7750.h>
-#include <rtems/score/iosh7750.h>
-#include <rtems/score/sh4_regs.h>
-#include <rtems/score/sh_io.h>
-
-/* from cpu_isps.c */
-extern proc_ptr _Hardware_isr_Table[];
-
-#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
- unsigned long *_old_stack_ptr;
-#endif
-
-register unsigned long *stack_ptr __asm__ ("r15");
-
-/*
- * This routine provides the RTEMS interrupt management.
- */
-
-void __ISR_Handler( uint32_t vector)
-{
- ISR_Level level;
-
- _ISR_Local_disable( level );
-
- _Thread_Dispatch_disable();
-
-#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
- if ( _ISR_Nest_level == 0 )
- {
- /* Install irq stack */
- _old_stack_ptr = stack_ptr;
- stack_ptr = _CPU_Interrupt_stack_high;
- }
-
-#endif
-
- _ISR_Nest_level++;
-
- _ISR_Local_enable( level );
-
- /* call isp */
- if ( _ISR_Vector_table[ vector])
- (*_ISR_Vector_table[ vector ])( vector );
-
- _ISR_Local_disable( level );
-
- _Thread_Dispatch_enable( _Per_CPU_Get() );
-
- _ISR_Nest_level--;
-
-#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
- if ( _ISR_Nest_level == 0 )
- /* restore old stack pointer */
- stack_ptr = _old_stack_ptr;
-#endif
-
- _ISR_Local_enable( level );
-
- if ( _ISR_Nest_level )
- return;
-
- if ( !_Thread_Dispatch_is_enabled() ) {
- return;
- }
-
- if ( _Thread_Dispatch_necessary ) {
- _Thread_Dispatch();
- }
-}
diff --git a/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c b/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
deleted file mode 100644
index 33fce3f461..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * SH7750 interrupt support.
- *
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Victor V. Vengerov <vvv@oktet.ru>
- *
- * Based on work:
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- * Modified to reflect isp entries for sh7045 processor:
- * John M. Mills (jmills@tga.com)
- * TGA Technologies, Inc.
- * 100 Pinnacle Way, Suite 140
- * Norcross, GA 30071 U.S.A.
- * August, 1999
- *
- * This modified file may be copied and distributed in accordance
- * the above-referenced license. It is provided for critique and
- * developmental purposes without any warranty nor representation
- * by the authors or by TGA Technologies.
- */
-
-#include <rtems/system.h>
-#include <rtems/score/types.h>
-#include <rtems/score/isr.h>
-
-/*
- * This is a exception vector table
- *
- * It has the same structure as the actual vector table (vectab)
- */
-
-
-#include <rtems/score/ispsh7750.h>
-#include <rtems/score/sh4_regs.h>
-#include <rtems/score/sh7750_regs.h>
-
-/* VBR register contents saved on startup -- used to hook exception by debug
- * agent */
-void *_VBR_Saved;
-
-#define __STRINGIFY1__(x) #x
-#define __STRINGIFY__(x) __STRINGIFY1__(x)
-
-#define STOP_TIMER \
- " mov.l TSTR_k,r0 \n" \
- " mov.b @r0,r1 \n" \
- " and #" __STRINGIFY__(~SH7750_TSTR_STR0) ",r1\n" \
- " mov.b r1,@r0 \n"
-
-#define START_TIMER \
- " mov.l TSTR_k,r0 \n" \
- " mov.b @r0,r1 \n" \
- " or #" __STRINGIFY__(SH7750_TSTR_STR0) ",r1\n" \
- " mov.b r1,@r0 \n"
-
-__asm__ (" .text\n"
- " .balign 256\n"
- " .global __vbr_base\n"
- "__vbr_base:\n"
- " .org __vbr_base + 0x100\n"
- "vbr_100:\n"
- " mov.l r0,@-r15\n"
- " mov.l r1,@-r15\n"
- " mov.l __VBR_Saved100_k, r0\n"
- " mov.l offset100_k,r1\n"
- " mov.l @r0,r0\n"
- " add r1,r0\n"
- " mov.l @r15+,r1\n"
- " jmp @r0\n"
- " mov.l @r15+,r0\n"
- " .align 2\n"
- "__VBR_Saved100_k:\n"
- " .long __VBR_Saved\n"
- "offset100_k:\n"
- " .long 0x100\n"
-
- " .org __vbr_base + 0x400\n"
- "vbr_400:\n"
- " mov.l r0,@-r15\n"
- " mov.l r1,@-r15\n"
- " mov.l __VBR_Saved400_k, r0\n"
- " mov.l offset400_k,r1\n"
- " mov.l @r0,r0\n"
- " add r1,r0\n"
- " mov.l @r15+,r1\n"
- " jmp @r0\n"
- " mov.l @r15+,r0\n"
- " .align 2\n"
- "__VBR_Saved400_k:\n"
- " .long __VBR_Saved\n"
- "offset400_k:\n"
- " .long 0x400\n"
-
- " .org __vbr_base + 0x600\n"
- "vbr_600:\n"
- " mov.l r0,@-r15 \n"
- " mov.l r1,@-r15 \n"
- " stc sr,r0 \n"
- " mov.l __vbr_600_sr_and_k,r1\n"
- " and r1,r0 \n"
- " mov.l __vbr_600_sr_or_k,r1\n"
- " or r1,r0 \n"
- " ldc r0,sr \n"
- " ldc.l @r15+,r1_bank\n"
- " ldc.l @r15+,r0_bank\n"
- " mov.l r0,@-r15 \n"
- " mov.l r1,@-r15 \n"
- " mov.l r2,@-r15 \n"
- " mov.l r3,@-r15 \n"
- " mov.l r4,@-r15 \n"
- " mov.l r5,@-r15 \n"
- " mov.l r6,@-r15 \n"
- " mov.l r7,@-r15 \n"
-#if 0
- " mov.l r8,@-r15 \n"
- " mov.l r9,@-r15 \n"
- " mov.l r10,@-r15 \n"
- " mov.l r11,@-r15 \n"
- " mov.l r12,@-r15 \n"
- " mov.l r13,@-r15 \n"
-#endif
- " mov.l r14,@-r15 \n"
- " sts.l fpscr,@-r15\n"
- " sts.l fpul,@-r15 \n"
- " mov.l __ISR_temp_fpscr_k,r0 \n"
- " lds r0,fpscr \n"
- " fmov fr0,@-r15 \n"
- " fmov fr1,@-r15 \n"
- " fmov fr2,@-r15 \n"
- " fmov fr3,@-r15 \n"
- " fmov fr4,@-r15 \n"
- " fmov fr5,@-r15 \n"
- " fmov fr6,@-r15 \n"
- " fmov fr7,@-r15 \n"
- " fmov fr8,@-r15 \n"
- " fmov fr9,@-r15 \n"
- " fmov fr10,@-r15 \n"
- " fmov fr11,@-r15 \n"
- " fmov fr12,@-r15 \n"
- " fmov fr13,@-r15 \n"
- " fmov fr14,@-r15 \n"
- " fmov fr15,@-r15 \n"
-
- " sts.l pr,@-r15 \n"
- " sts.l mach,@-r15 \n"
- " sts.l macl,@-r15 \n"
- " stc.l spc,@-r15 \n"
- " stc.l ssr,@-r15 \n"
- " mov r15,r14 \n"
-#if 0
- " stc ssr,r0 \n"
- " ldc r0,sr \n"
-#endif
- " mov.l __ISR_Handler_k, r1\n"
- " mov.l _INTEVT_k,r4\n"
- " mov.l @r4,r4 \n"
- " shlr2 r4 \n"
- " shlr r4 \n"
-
- " mov.l _ISR_Table_k,r0\n"
- " mov.l @r0,r0 \n"
- " add r4,r0 \n"
- " mov.l @r0,r0 \n"
- " cmp/eq #0,r0 \n"
- " bt _ipl_hook \n"
-
-
- " jsr @r1 \n"
- " shlr2 r4 \n"
- " mov r14,r15 \n"
- " ldc.l @r15+,ssr \n"
- " ldc.l @r15+,spc \n"
- " lds.l @r15+,macl \n"
- " lds.l @r15+,mach \n"
- " lds.l @r15+,pr \n"
- " mov.l __ISR_temp_fpscr_k,r0 \n"
- " lds r0,fpscr \n"
-
- " fmov @r15+,fr15 \n"
- " fmov @r15+,fr14 \n"
- " fmov @r15+,fr13 \n"
- " fmov @r15+,fr12 \n"
- " fmov @r15+,fr11 \n"
- " fmov @r15+,fr10 \n"
- " fmov @r15+,fr9 \n"
- " fmov @r15+,fr8 \n"
- " fmov @r15+,fr7 \n"
- " fmov @r15+,fr6 \n"
- " fmov @r15+,fr5 \n"
- " fmov @r15+,fr4 \n"
- " fmov @r15+,fr3 \n"
- " fmov @r15+,fr2 \n"
- " fmov @r15+,fr1 \n"
- " fmov @r15+,fr0 \n"
- " lds.l @r15+,fpul \n"
- " lds.l @r15+,fpscr\n"
- " mov.l @r15+,r14 \n"
-#if 0
- " mov.l @r15+,r13 \n"
- " mov.l @r15+,r12 \n"
- " mov.l @r15+,r11 \n"
- " mov.l @r15+,r10 \n"
- " mov.l @r15+,r9 \n"
- " mov.l @r15+,r8 \n"
-#endif
-
- " mov.l @r15+,r7 \n"
- " mov.l @r15+,r6 \n"
- " mov.l @r15+,r5 \n"
- " mov.l @r15+,r4 \n"
- " mov.l @r15+,r3 \n"
- " mov.l @r15+,r2 \n"
- " mov.l @r15+,r1 \n"
- " mov.l @r15+,r0 \n"
- " rte \n"
- " nop \n"
- " .align 2 \n"
- "__vbr_600_sr_and_k: \n"
- " .long " __STRINGIFY__(~(SH4_SR_RB | SH4_SR_BL)) "\n"
- "__vbr_600_sr_or_k: \n"
- " .long " __STRINGIFY__(SH4_SR_IMASK) "\n"
- "__ISR_Handler_k: \n"
- " .long ___ISR_Handler\n"
- "_INTEVT_k: \n"
- " .long " __STRINGIFY__(SH7750_INTEVT) "\n"
- "_ISR_Table_k: \n"
- " .long __ISR_Vector_table\n"
-
- "_ipl_hook: \n"
- " mov r14,r15 \n"
- " ldc.l @r15+,ssr \n"
- " ldc.l @r15+,spc \n"
- " lds.l @r15+,macl \n"
- " lds.l @r15+,mach \n"
- " lds.l @r15+,pr \n"
- " mov.l __ISR_temp_fpscr_k,r0 \n"
- " lds r0,fpscr \n"
- " fmov @r15+,fr15 \n"
- " fmov @r15+,fr14 \n"
- " fmov @r15+,fr13 \n"
- " fmov @r15+,fr12 \n"
- " fmov @r15+,fr11 \n"
- " fmov @r15+,fr10 \n"
- " fmov @r15+,fr9 \n"
- " fmov @r15+,fr8 \n"
- " fmov @r15+,fr7 \n"
- " fmov @r15+,fr6 \n"
- " fmov @r15+,fr5 \n"
- " fmov @r15+,fr4 \n"
- " fmov @r15+,fr3 \n"
- " fmov @r15+,fr2 \n"
- " fmov @r15+,fr1 \n"
- " fmov @r15+,fr0 \n"
- " lds.l @r15+,fpul \n"
- " lds.l @r15+,fpscr\n"
- " mov.l @r15+,r14 \n"
-
- " mov.l @r15+,r13 \n"
- " mov.l @r15+,r12 \n"
- " mov.l @r15+,r11 \n"
- " mov.l @r15+,r10 \n"
- " mov.l @r15+,r9 \n"
- " mov.l @r15+,r8 \n"
-
-
- " mov.l @r15+,r7 \n"
- " mov.l @r15+,r6 \n"
- " mov.l @r15+,r5 \n"
- " mov.l @r15+,r4 \n"
- " mov.l @r15+,r3 \n"
- " mov.l @r15+,r2 \n"
- " mov.l __VBR_Saved600_k, r0\n"
- " mov.l offset600_k,r1\n"
- " mov.l @r0,r0\n"
- " add r1,r0\n"
- " mov.l @r15+,r1\n"
- " jmp @r0\n"
- " mov.l @r15+,r0\n"
- " .align 2\n"
- "__ISR_temp_fpscr_k: \n"
- " .long " __STRINGIFY__(SH4_FPSCR_PR) " \n"
- "__VBR_Saved600_k:\n"
- " .long __VBR_Saved\n"
- "offset600_k:\n"
- " .long 0x600\n"
-
- );
-
-
-/************************************************
- * Dummy interrupt service procedure for
- * interrupts being not allowed --> Trap 2
- ************************************************/
-__asm__ (" .section .text\n\
-.global __dummy_isp\n\
-__dummy_isp:\n\
- mov.l r14,@-r15\n\
- mov r15, r14\n\
- trapa #2\n\
- mov.l @r15+,r14\n\
- rte\n\
- nop");
diff --git a/c/src/lib/libcpu/sh/sh7750/timer/timer.c b/c/src/lib/libcpu/sh/sh7750/timer/timer.c
deleted file mode 100644
index ef462c780c..0000000000
--- a/c/src/lib/libcpu/sh/sh7750/timer/timer.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- * @file
- * @brief Timer driver for the Hitachi SH 7750
- */
-
-/*
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Author: Victor V. Vengerov <vvv@oktet.ru>
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems.h>
-#include <rtems/btimer.h>
-
-#include <rtems/score/sh_io.h>
-#include <rtems/score/iosh7750.h>
-
-extern uint32_t bsp_clicks_per_second;
-
-#ifndef TIMER_PRIO
-#define TIMER_PRIO 15
-#endif
-
-/* Timer prescaler division ratio */
-#define TIMER_PRESCALER 4
-#define TCR1_TPSC SH7750_TCR_TPSC_DIV4
-
-#define TIMER_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI1)
-
-extern rtems_isr timerisr(void);
-
-static uint32_t Timer_interrupts;
-
-/* Counter should be divided to this value to obtain time in microseconds */
-static uint32_t microseconds_divider;
-
-/* Interrupt period in microseconds */
-static uint32_t microseconds_per_int;
-
-bool benchmark_timer_find_average_overhead;
-
-/* benchmark_timer_initialize --
- * Initialize Timer 1 to operate as a RTEMS benchmark timer:
- * - determine timer clock frequency
- * - install timer interrupt handler
- * - configure the Timer 1 hardware
- * - start the timer
- *
- * PARAMETERS:
- * none
- *
- * RETURNS:
- * none
- */
-void
-benchmark_timer_initialize(void)
-{
- uint8_t temp8;
- uint16_t temp16;
- rtems_interrupt_level level;
- rtems_isr *ignored;
- int cpudiv = 1;
- int tidiv = 1;
-
- Timer_interrupts = 0;
- rtems_interrupt_disable(level);
-
- /* Get CPU frequency divider from clock unit */
- switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC)
- {
- case SH7750_FRQCR_IFCDIV1:
- cpudiv = 1;
- break;
-
- case SH7750_FRQCR_IFCDIV2:
- cpudiv = 2;
- break;
-
- case SH7750_FRQCR_IFCDIV3:
- cpudiv = 3;
- break;
-
- case SH7750_FRQCR_IFCDIV4:
- cpudiv = 4;
- break;
-
- case SH7750_FRQCR_IFCDIV6:
- cpudiv = 6;
- break;
-
- case SH7750_FRQCR_IFCDIV8:
- cpudiv = 8;
- break;
-
- default:
- rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
- }
-
- /* Get peripheral module frequency divider from clock unit */
- switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC)
- {
- case SH7750_FRQCR_PFCDIV2:
- tidiv = 2 * TIMER_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV3:
- tidiv = 3 * TIMER_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV4:
- tidiv = 4 * TIMER_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV6:
- tidiv = 6 * TIMER_PRESCALER;
- break;
-
- case SH7750_FRQCR_PFCDIV8:
- tidiv = 8 * TIMER_PRESCALER;
- break;
-
- default:
- rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
- }
-
- microseconds_divider = bsp_clicks_per_second * cpudiv / (tidiv * 1000000);
- microseconds_per_int = 0xFFFFFFFF / microseconds_divider;
-
- /*
- * Hardware specific initialization
- */
-
- /* Stop the Timer 0 */
- temp8 = read8(SH7750_TSTR);
- temp8 &= ~SH7750_TSTR_STR1;
- write8(temp8, SH7750_TSTR);
-
- /* Establish interrupt handler */
- _CPU_ISR_install_raw_handler( TIMER_VECTOR, timerisr, &ignored );
-
- /* Reset timer constant and counter */
- write32(0xFFFFFFFF, SH7750_TCOR1);
- write32(0xFFFFFFFF, SH7750_TCNT1);
-
- /* Select timer mode */
- write16(
- SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
- SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
- TCR1_TPSC, /* Timer prescaler ratio */
- SH7750_TCR1);
-
- /* Set timer interrupt priority */
- temp16 = read16(SH7750_IPRA);
- temp16 = (temp16 & ~SH7750_IPRA_TMU1) | (TIMER_PRIO << SH7750_IPRA_TMU1_S);
- write16(temp16, SH7750_IPRA);
-
-
- rtems_interrupt_enable(level);
-
- /* Start the Timer 1 */
- temp8 = read8(SH7750_TSTR);
- temp8 |= SH7750_TSTR_STR1;
- write8(temp8, SH7750_TSTR);
-
-}
-
-/*
- * The following controls the behavior of benchmark_timer_read().
- *
- * AVG_OVERHEAD is the overhead for starting and stopping the timer. It
- * is usually deducted from the number returned.
- *
- * LEAST_VALID is the lowest number this routine should trust. Numbers
- * below this are "noise" and zero is returned.
- */
-
-#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */
- /* (Y countdowns) to start/stop the timer. */
- /* This value is in microseconds. */
-#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */
-
-/* benchmark_timer_read --
- * Read timer value in microsecond units since timer start.
- *
- * PARAMETERS:
- * none
- *
- * RETURNS:
- * number of microseconds since timer has been started
- */
-benchmark_timer_t
-benchmark_timer_read(void)
-{
- uint32_t clicks;
- uint32_t ints;
- uint32_t total;
- rtems_interrupt_level level;
- uint32_t tcr;
-
-
- rtems_interrupt_disable(level);
-
- clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
- tcr = read32(SH7750_TCR1);
- ints = Timer_interrupts;
-
- rtems_interrupt_enable(level);
-
- /* Handle the case when timer overflowed but interrupt was not processed */
- if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))
- {
- ints++;
- }
-
- total = microseconds_per_int * ints + (clicks / microseconds_divider);
-
- if ( benchmark_timer_find_average_overhead )
- return total; /* in microsecond units */
- else
- {
- if ( total < LEAST_VALID )
- return 0; /* below timer resolution */
- /*
- * Somehow convert total into microseconds
- */
- return (total - AVG_OVERHEAD) ;
- }
-}
-
-/* benchmark_timer_disable_subtracting_average_overhead --
- * This routine is invoked by the "Check Timer" (tmck) test in the
- * RTEMS Timing Test Suite. It makes the benchmark_timer_read routine not
- * subtract the overhead required to initialize and read the benchmark
- * timer.
- *
- * PARAMETERS:
- * find_flag - boolean flag, true if overhead must not be subtracted.
- *
- * RETURNS:
- * none
- */
-void
-benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
-{
- benchmark_timer_find_average_overhead = find_flag;
-}
-
-/* timerisr --
- * Timer interrupt handler routine. This function invoked on timer
- * underflow event; once per 2^32 clocks. It should reset the timer
- * event and increment timer interrupts counter.
- */
-void
-timerisr(void)
-{
- uint8_t temp8;
-
- /* reset the flags of the status register */
- temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF;
- write8(temp8, SH7750_TCR1);
-
- Timer_interrupts += 1;
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-24 18:38:13 +0000