Patch from "John M. Mills" <jmills@tga.com> with subsequent cleanup from

Ralf Corsepius <corsepiu@faw.uni-ulm.de> that adds initial Hitachi SH-2
support to RTEMS.  Ralf's comments are:

    Changes:
    ------
    1. SH-Port:
    * Many files renamed.
    * CONSOLE_DEVNAME  and MHZ defines removed from libcpu.
    * console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console
      applying VPATH.
    * CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
    * MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
    * -DHZ=HZ  used in bspstart.c, only
    * Makefile variable HZ used in bsp-dependent directories only.

    2. SH1-Port
    * clock-driver rewritten to provide better resolution for odd CPU
      frequencies. This driver is only partially tested on hardware, ie.
      sightly experimental, but I don't expect severe problems with it.
    * Polling SCI-driver added. This driver is experimental and completly
      untested yet. Therefore it is not yet used for the console (/dev/console
      is still pointing to /dev/null, cf. gensh1/bsp.h).
    * minor changes to the timer driver
    * SH1 specific delay()/CPU_delay() now is implemented as a function

    3. SH2-Port
    * Merged
    * IMO, the code is still in its infancy. Therefore I have interspersed
      comments (FIXME) it for items which I think John should look after.
    * sci and console drivers partially rewritten and extended (John, I hope
      you don't mind).
    * Copyright notices are not yet adapted

1 files changed, 91 insertions, 0 deletions

diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h
new file mode 100644
index 0000000000..cf33c0ebdd
--- /dev/null
+++ b/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h
@@ -0,0 +1,91 @@
+/*
+ * Bit values for the serial control registers of the Hitachi SH704X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh7_sci_h
+#define _sh7_sci_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Serial mode register bits
+ */
+
+#define SCI_SYNC_MODE               0x80
+#define SCI_SEVEN_BIT_DATA          0x40
+#define SCI_PARITY_ON               0x20
+#define SCI_ODD_PARITY              0x10
+#define SCI_STOP_BITS_2             0x08
+#define SCI_ENABLE_MULTIP           0x04
+#define SCI_PHI_64                  0x03
+#define SCI_PHI_16                  0x02
+#define SCI_PHI_4                   0x01
+#define SCI_PHI_0                   0x00
+
+/*
+ * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
+ */
+
+#define SCI_SMR			0x00
+#define SCI_BRR			0x01
+#define SCI_SCR			0x02
+#define SCI_TDR			0x03
+#define SCI_SSR			0x04
+#define SCI_RDR			0x05
+
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE                 0x80    /* Transmit interrupt enable */
+#define SCI_RIE                 0x40    /* Receive interrupt enable */
+#define SCI_TE                  0x20    /* Transmit enable */
+#define SCI_RE                  0x10    /* Receive enable */
+#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
+#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
+#define SCI_CKE1                0x02    /* Clock enable 1 */
+#define SCI_CKE0                0x01    /* Clock enable 0 */
+
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE                0x80    /* Transmit data register empty */
+#define SCI_RDRF                0x40    /* Receive data register full */
+#define SCI_ORER                0x20    /* Overrun error */
+#define SCI_FER                 0x10    /* Framing error */
+#define SCI_PER                 0x08    /* Parity error */
+#define SCI_TEND                0x04    /* Transmit end */
+#define SCI_MPB                 0x02    /* Multiprocessor bit */
+#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
+
+/*
+ * INTC Priority Settings
+ */
+
+#define SCI0_IPMSK	0x00F0
+#define SCI0_LOWIP	0x0010
+#define SCI1_IPMSK	0x000F
+#define SCI1_LOWIP	0x0001
+
+#endif /* _sh7_sci_h */