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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-09-29 12:40:33 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-09-29 12:40:33 +0000 |
| commit | 21bfd93aaff71a70ca426adb5ccd8397e7d8e5ef (patch) | |
| tree | e40c0ed97a4fb9be2d60851600abc4adc22976a3 /c/src/lib/libcpu/sh/sh7032/timer | |
| parent | Patch from Eric Norum <eric@skatter.usask.ca>: (diff) | |
| download | rtems-21bfd93aaff71a70ca426adb5ccd8397e7d8e5ef.tar.bz2 | |
Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:
Please find enclosed a patch which enables me to build the bare-bsp for
sh-rtems.
Changes:
1. Add preinstall to libbsp/bare/include/Makefile.in
2. Removed FORCEIT, add preinstall to
libbsp/sh/gensh1/include/Makefile.in
3. Disabled support of set_vector from sh code (shared/setvec.c is still
present but isn't used anymore), set_vector replaced with standard rtems
functions.
Problems still present:
1. Support of spin-delays in bare bsp
2. Proper support of cpu frequency
To configure I used:
<srcdir>/configure \
--target=sh-rtems \
--prefix=<instdir>/sh-bare \
--enable-bare-cpu-model=sh7032 \
--enable-bare-cpu-cflags='-Wall -m1 -DMHZ=20
-DCPU_CONSOLE_DEVNAME="\"/dev/null\""'
--enable-rtemsbsp=bare \
--disable-networking \
--disable-cxx \
--disable-posix \
--disable-tests
IMO, if there are no objections to this patch, a similar approach should
be applied to all CPUs/BSPs (esp. hppa1.1, mips64orion, ppc403, because
they apply set_vector inside of libcpu).
Diffstat (limited to 'c/src/lib/libcpu/sh/sh7032/timer')
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7032/timer/timer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/c/src/lib/libcpu/sh/sh7032/timer/timer.c b/c/src/lib/libcpu/sh/sh7032/timer/timer.c index 8aa6cb9b27..ddf8bfc06b 100644 --- a/c/src/lib/libcpu/sh/sh7032/timer/timer.c +++ b/c/src/lib/libcpu/sh/sh7032/timer/timer.c @@ -62,10 +62,10 @@ rtems_boolean Timer_driver_Find_average_overhead; void Timer_initialize( void ) { - rtems_unsigned8 temp8; + rtems_unsigned8 temp8; rtems_unsigned16 temp16; rtems_unsigned32 level; - rtems_isr* ignored; + rtems_isr *ignored; /* * Timer has never overflowed. This may not be necessary on some @@ -117,7 +117,7 @@ void Timer_initialize( void ) write16( temp16, INTC_IPRC); /* initialize ISR */ - ignored = set_vector( timerisr, ITU1_VECTOR, 0); + _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored ); _CPU_ISR_Enable( level); /* start timer 1 */ |