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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-09-12 15:23:49 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-09-12 15:23:49 +0000 |
| commit | 3d7fa72bc2ba2f723e6bcf84180637fb8c84f713 (patch) | |
| tree | 4b542c612d352d8924e5ca59a921623d937ed754 /c/src/lib/libcpu/sh/sh7032/score | |
| parent | 2007-09-12 Joel Sherrill <joel.sherrill@OARcorp.com> (diff) | |
| download | rtems-3d7fa72bc2ba2f723e6bcf84180637fb8c84f713.tar.bz2 | |
2007-09-12 Joel Sherrill <joel.sherrill@OARcorp.com>
PR 1257/bsps
* sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/score/cpu_asm.c,
sh7045/timer/timer.c, sh7750/score/cpu_asm.c, sh7750/timer/timer.c:
Code outside of cpukit should use the public API for
rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the
public API and directly accessing _CPU_ISR_Disable and
_CPU_ISR_Enable, they were bypassing the compiler memory barrier
directive which could lead to problems. This patch also changes the
type of the variable passed into these routines and addresses minor
style issues.
Diffstat (limited to 'c/src/lib/libcpu/sh/sh7032/score')
| -rw-r--r-- | c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c index 4a1e87995a..6c16cfa733 100644 --- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c +++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @@ -68,10 +68,10 @@ unsigned int sh_set_irq_priority( unsigned int irq, unsigned int prio ) { - uint32_t shiftcount; - uint32_t prioreg; - uint16_t temp16; - uint32_t level; + uint32_t shiftcount; + uint32_t prioreg; + uint16_t temp16; + ISR_Level level; /* * first check for valid interrupt @@ -112,14 +112,14 @@ unsigned int sh_set_irq_priority( /* * Set the interrupt priority register */ - _CPU_ISR_Disable( level ); + _ISR_Disable( level ); - temp16 = read16( prioreg); - temp16 &= ~( 15 << shiftcount); - temp16 |= prio << shiftcount; - write16( temp16, prioreg); + temp16 = read16( prioreg); + temp16 &= ~( 15 << shiftcount); + temp16 |= prio << shiftcount; + write16( temp16, prioreg); - _CPU_ISR_Enable( level ); + _ISR_Enable( level ); return 0; } @@ -257,9 +257,9 @@ asm volatile( void __ISR_Handler( uint32_t vector) { - register uint32_t level; + ISR_Level level; - _CPU_ISR_Disable( level ); + _ISR_Disable( level ); _Thread_Dispatch_disable_level++; @@ -275,13 +275,13 @@ void __ISR_Handler( uint32_t vector) _ISR_Nest_level++; - _CPU_ISR_Enable( level ); + _ISR_Enable( level ); /* call isp */ if( _ISR_Vector_table[ vector]) (*_ISR_Vector_table[ vector ])( vector ); - _CPU_ISR_Disable( level ); + _ISR_Disable( level ); _Thread_Dispatch_disable_level--; @@ -294,7 +294,7 @@ void __ISR_Handler( uint32_t vector) stack_ptr = _old_stack_ptr; #endif - _CPU_ISR_Enable( level ); + _ISR_Enable( level ); if ( _ISR_Nest_level ) return; |