mpc5xx libcpu and ss555 BSP: Fix warnings

7 files changed, 38 insertions, 47 deletions

diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c
index c3442711a9..9f843cee4f 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c
@@ -1,7 +1,6 @@
 /*
- *
  *  This routine initializes the PIT on the MPC5xx.
- *  The tick frequency is specified by the bsp.
+ *  The tick frequency is specified by the BSP.
  */
 
 /*
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c
index f00d111524..22fee2d719 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c
@@ -9,8 +9,9 @@
  *   resource   minor                note
  *	SCI1	  0
  *	SCI2	  1
- *
- *
+ */
+
+/*
  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
  *
@@ -266,11 +267,11 @@ m5xx_sci_interrupt_handler (rtems_irq_hdl_param unused)
   }
 }
 
-void m5xx_sci_nop(const rtems_irq_connect_data* ptr)
+static void m5xx_sci_nop(const rtems_irq_connect_data* ptr)
 {
 }
 
-int m5xx_sci_isOn(const rtems_irq_connect_data* ptr)
+static int m5xx_sci_isOn(const rtems_irq_connect_data* ptr)
 {
   return 1;
 }
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
index 51838428c5..fc9b756cbf 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
@@ -1,9 +1,9 @@
 /*
- * mpc5xx.h
  *
  * MPC5xx Internal I/O Definitions
- *
- *
+ */
+
+/*
  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
  *
@@ -609,6 +609,14 @@ typedef struct imb_ {
 extern volatile imb_t imb;		/* defined in linkcmds */
 
 
+/*
+ * Methods shared across libcpu and the BSP.
+ */
+void clockOn(void* unused);
+void clockOff(void* unused);
+int clockIsOn(void* unused);
+rtems_isr Clock_isr(rtems_vector_number vector);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c
index 943c79fb56..0eb444c3fd 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c
@@ -1,8 +1,8 @@
 /*
- * irq.c
- *
  *  This file contains the implementation of the function described in irq.h
- *
+ */
+
+/*
  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
  *
@@ -21,12 +21,12 @@
 #include <libcpu/vectors.h>
 #include <libcpu/raw_exception.h>
 #include <libcpu/irq.h>
+#include <bsp/irq.h>
 
 /*
  * Convert an rtems_irq_number constant to an interrupt level
  * suitable for programming into an I/O device's interrupt level field.
  */
-
 int CPU_irq_level_from_symbolic_name(const rtems_irq_number name)
 {
   if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7)
@@ -138,28 +138,21 @@ static int isValidInterrupt(int irq)
   return 1;
 }
 
-int CPU_irq_enable_at_uimb(const rtems_irq_number irqLine)
+static int CPU_irq_enable_at_uimb(const rtems_irq_number irqLine)
 {
   if (!is_uimb_irq(irqLine))
     return 1;
   return 0;
 }
 
-int CPU_irq_disable_at_uimb(const rtems_irq_number irqLine)
+static int CPU_irq_disable_at_uimb(const rtems_irq_number irqLine)
 {
   if (!is_uimb_irq(irqLine))
     return 1;
   return 0;
 }
 
-int CPU_irq_enabled_at_uimb(const rtems_irq_number irqLine)
-{
-  if (!is_uimb_irq(irqLine))
-    return 0;
-  return 1;
-}
-
-int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine)
+static int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine)
 {
   int usiu_irq_index;
 
@@ -173,7 +166,7 @@ int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine)
   return 0;
 }
 
-int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine)
+static int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine)
 {
   int usiu_irq_index;
 
@@ -187,17 +180,6 @@ int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine)
   return 0;
 }
 
-int CPU_irq_enabled_at_usiu(const rtems_irq_number irqLine)
-{
-  int usiu_irq_index;
-
-  if (!is_usiu_irq(irqLine))
-    return 0;
-
-  usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET);
-  return ppc_cached_irq_mask & (1 << (31-usiu_irq_index));
-}
-
 /*
  * --------------- RTEMS Single Irq Handler Mngt Routines ----------------
  */
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c
index 7b9cfd079d..3ba7e8f505 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c
@@ -3,8 +3,9 @@
  *
  *  This file contains the implementation of rtems initialization
  *  related to interrupt handling.
- *
- *
+ */
+
+/*
  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
  *
@@ -89,7 +90,7 @@ static rtems_irq_prio irqPrioTable[CPU_IRQ_COUNT]={
   0
 };
 
-void CPU_USIU_irq_init(void)
+static void CPU_USIU_irq_init(void)
 {
   /*
    * In theory we should initialize two registers at least : SIMASK and
@@ -106,8 +107,7 @@ void CPU_USIU_irq_init(void)
 /*
  * Initialize UIMB interrupt management
  */
-void
-CPU_UIMB_irq_init(void)
+static void CPU_UIMB_irq_init(void)
 {
 }
 
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
index c46002757d..2c8914e2a4 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h
@@ -85,9 +85,9 @@
  * default raw exception handlers
  */
 
-extern	void default_exception_vector_code_prolog();
+extern	void default_exception_vector_code_prolog(void);
 extern	int  default_exception_vector_code_prolog_size;
-extern  void initialize_exceptions();
+extern  void initialize_exceptions(void);
 
 typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr);
 /*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c
index 768bd04306..4a6c5be5c2 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c
@@ -3,8 +3,9 @@
  *
  *  This include file describe the data structure and the functions implemented
  *  by rtems to handle exceptions.
- *
- *
+ */
+
+/*
  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
  *
@@ -19,6 +20,7 @@
 #include <rtems/bspIo.h>
 #include <libcpu/vectors.h>
 #include <libcpu/raw_exception.h>
+#include <bsp/irq.h>
 
 extern rtems_exception_handler_t default_exception_handler;
 
@@ -26,7 +28,6 @@ static rtems_raw_except_global_settings exception_config;
 static rtems_raw_except_connect_data    exception_table[NUM_EXCEPTIONS];
 rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS];
 
-
 void C_default_exception_handler(CPU_Exception_frame* excPtr)
 {
   int recoverable = 0;
@@ -84,11 +85,11 @@ void C_default_exception_handler(CPU_Exception_frame* excPtr)
     }
 }
 
-void nop_except_enable(const rtems_raw_except_connect_data* ptr)
+static void nop_except_enable(const rtems_raw_except_connect_data* ptr)
 {
 }
 
-int except_always_enabled(const rtems_raw_except_connect_data* ptr)
+static int except_always_enabled(const rtems_raw_except_connect_data* ptr)
 {
   return 1;
 }