diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-14 15:38:08 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-14 15:38:08 +0000 |
commit | abd9401a4a9f871baddc7569f355386ec06ae196 (patch) | |
tree | 280955c9e320a81dae920ae0191bb4fffdc27f27 /c/src/lib/libcpu/powerpc/shared/include/spr.h | |
parent | Moved from score/cpu/PowerPC. (diff) | |
download | rtems-abd9401a4a9f871baddc7569f355386ec06ae196.tar.bz2 |
Functionality moved from directory above to accomodate building
shared source code.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/spr.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/shared/include/spr.h b/c/src/lib/libcpu/powerpc/shared/include/spr.h new file mode 100644 index 0000000000..2df38f5644 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/shared/include/spr.h @@ -0,0 +1,80 @@ +/* + * spr.h -- Access to special purpose registers. + * + * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + */ + + +#ifndef _PPC_SPR_H +#define _PPC_SPR_H + +#include <libcpu/cpu.h> + +#define __MFSPR(reg, val) \ + __asm__ __volatile__("mfspr %0,"#reg : "=r" (val)) + +#define __MTSPR(val, reg) \ + __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val)) + + +#define SPR_RW(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg, val);\ + return val;\ +}\ +static inline void _write_##reg(unsigned long val)\ +{\ + __MTSPR(val,reg);\ + return;\ +} + +#define SPR_RO(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg,val);\ + return val;\ +} + +static inline unsigned long _read_MSR(void) +{ + unsigned long val; + asm volatile("mfmsr %0" : "=r" (val)); + return val; +} + +static inline void _write_MSR(unsigned long val) +{ + asm volatile("mtmsr %0" : : "r" (val)); + return; +} + +static inline unsigned long _read_SR(void * va) +{ + unsigned long val; + asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); + return val; +} + +static inline void _write_SR(unsigned long val, void * va) +{ + asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory"); + return; +} + + +#endif |